公开(公告)号：US20070206406A1

公开(公告)日：2007-09-06

申请号：US11673241

申请日：2007-02-09

申请人： Yoshihiro Ueda ,  Kenji Tsuchida ,  Tsuneo Inaba ,  Kiyotaro Itagaki

发明人： Yoshihiro Ueda ,  Kenji Tsuchida ,  Tsuneo Inaba ,  Kiyotaro Itagaki

IPC分类号： G11C11/00

CPC分类号： G11C11/16 ,  Y10S977/935

摘要： A spin injection write type magnetic memory device includes memory cells which have a magnetoresistance effect element and a select transistor. The magnetoresistance effect element has one end connected to a first node. The select transistor has a first diffusion area connected to another end of the magnetoresistance effect element and a second diffusion area connected to a second node. A select line extends along a first direction and is connected to a gate electrode of the select transistor. A first interconnect extends along a second direction and is connected to the first node. A second interconnect extends along the second direction and is connected to the second node. Two of the memory cells adjacent along the first direction share the first node. Two of the memory cells adjacent along the second direction share the second node.

摘要翻译： 自旋注入写入型磁存储器件包括具有磁阻效应元件和选择晶体管的存储单元。 磁阻效应元件的一端连接到第一节点。 选择晶体管具有连接到磁阻效应元件的另一端的第一扩散区域和连接到第二节点的第二扩散区域。 选择线沿着第一方向延伸并连接到选择晶体管的栅电极。 第一互连沿着第二方向延伸并连接到第一节点。 第二互连沿着第二方向延伸并且连接到第二节点。 沿着第一方向相邻的两个存储单元共享第一节点。 沿着第二方向相邻的两个存储单元共享第二节点。

公开(公告)号：US07545672B2

公开(公告)日：2009-06-09

申请号：US11673241

申请日：2007-02-09

申请人： Yoshihiro Ueda ,  Kenji Tsuchida ,  Tsuneo Inaba ,  Kiyotaro Itagaki

发明人： Yoshihiro Ueda ,  Kenji Tsuchida ,  Tsuneo Inaba ,  Kiyotaro Itagaki

IPC分类号： G11C11/00

CPC分类号： G11C11/16 ,  Y10S977/935

摘要： A spin injection write type magnetic memory device includes memory cells which have a magnetoresistance effect element and a select transistor. The magnetoresistance effect element has one end connected to a first node. The select transistor has a first diffusion area connected to another end of the magnetoresistance effect element and a second diffusion area connected to a second node. A select line extends along a first direction and is connected to a gate electrode of the select transistor. A first interconnect extends along a second direction and is connected to the first node. A second interconnect extends along the second direction and is connected to the second node. Two of the memory cells adjacent along the first direction share the first node. Two of the memory cells adjacent along the second direction share the second node.

摘要翻译： 自旋注入写入型磁存储器件包括具有磁阻效应元件和选择晶体管的存储单元。 磁阻效应元件的一端连接到第一节点。 选择晶体管具有连接到磁阻效应元件的另一端的第一扩散区域和连接到第二节点的第二扩散区域。 选择线沿着第一方向延伸并连接到选择晶体管的栅电极。 第一互连沿着第二方向延伸并连接到第一节点。 第二互连沿着第二方向延伸并且连接到第二节点。 沿着第一方向相邻的两个存储单元共享第一节点。 沿着第二方向相邻的两个存储单元共享第二节点。

公开(公告)号：US07916522B2

公开(公告)日：2011-03-29

申请号：US12400262

申请日：2009-03-09

申请人： Kiyotaro Itagaki ,  Tsuneo Inaba ,  Yoshihiro Ueda ,  Yoshiaki Asao

发明人： Kiyotaro Itagaki ,  Tsuneo Inaba ,  Yoshihiro Ueda ,  Yoshiaki Asao

IPC分类号： G11C11/15

CPC分类号： G11C11/5607 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1675 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/003 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2013/0078 ,  G11C2013/0092 ,  G11C2213/75 ,  G11C2213/78

摘要： A semiconductor memory device includes n resistance change elements which are arranged in one cell, have a low-resistance state and a high resistance state, are connected in series or parallel, have different resistance values in the same resistance state, and change between the low-resistance state and the high-resistance state under different conditions, and a write circuit which is connected to one end of the n resistance change elements, and applies a pulse current m (1≦m≦n) times to the n resistance change elements during a write operation. Letting Im be a current value of an mth pulse current, condition I1>I2> . . . >Im holds.

摘要翻译： 半导体存储器件包括在一个单元中布置的具有低电阻状态和高电阻状态的n个电阻变化元件串联或并联连接，在相同电阻状态下具有不同的电阻值，并且在低电平 电阻状态和不同条件下的高电阻状态，以及与n个电阻变化元件的一端连接的写入电路，并向n个电阻变化元件施加脉冲电流m（1＆nlE; m＆nlE; n）次 在写操作期间。 令Im为第m个脉冲电流的当前值，条件I1> I2>。 。 。 > Im持有。

公开(公告)号：US20090257274A1

公开(公告)日：2009-10-15

申请号：US12400262

申请日：2009-03-09

申请人： Kiyotaro Itagaki ,  Tsuneo Inaba ,  Yoshihiro Ueda ,  Yoshiaki Asao

发明人： Kiyotaro Itagaki ,  Tsuneo Inaba ,  Yoshihiro Ueda ,  Yoshiaki Asao

IPC分类号： G11C11/16 ,  G11C11/14

CPC分类号： G11C11/5607 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1675 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/003 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2013/0078 ,  G11C2013/0092 ,  G11C2213/75 ,  G11C2213/78

摘要： A semiconductor memory device includes n resistance change elements which are arranged in one cell, have a low-resistance state and a high resistance state, are connected in series or parallel, have different resistance values in the same resistance state, and change between the low-resistance state and the high-resistance state under different conditions, and a write circuit which is connected to one end of the n resistance change elements, and applies a pulse current m (1≦m≦n) times to the n resistance change elements during a write operation. Letting Im be a current value of an mth pulse current, condition I1>I2> . . . >Im holds.

摘要翻译： 半导体存储器件包括在一个单元中布置的具有低电阻状态和高电阻状态的n个电阻变化元件串联或并联连接，在相同电阻状态下具有不同的电阻值，并且在低电平 电阻状态和不同条件下的高电阻状态，以及与n个电阻变化元件的一端连接的写入电路，并向n个电阻施加脉冲电流m（1 <= m <= n）次 在写入操作期间更改元素。 令Im为第m个脉冲电流的当前值，条件I1> I2>。 。 。 > Im持有。

公开(公告)号：US08036015B2

公开(公告)日：2011-10-11

申请号：US12536341

申请日：2009-08-05

申请人： Yoshihiro Ueda ,  Kenji Tsuchida ,  Kiyotaro Itagaki

发明人： Yoshihiro Ueda ,  Kenji Tsuchida ,  Kiyotaro Itagaki

IPC分类号： G11C11/00 ,  G11C7/10

CPC分类号： G11C13/00 ,  G11C11/16 ,  G11C11/1659 ,  G11C11/1673 ,  G11C13/0004 ,  G11C13/004 ,  G11C29/02 ,  G11C29/026 ,  G11C2013/0054 ,  G11C2213/79

摘要： A resistive memory includes a plurality of memory cells, a plurality of reference cells having mutually different resistance values, at least one sense amplifier having a first input terminal connected to one selected memory cell which is selected from the plurality of memory cells at a time of read, and a second input terminal connected to one selected reference cell which is selected from the plurality of reference cells at the time of read, and one latch circuit which holds offset information of the at least one sense amplifier. The resistive memory further includes a decoder which selects, in accordance with the offset information, the one selected reference cell from the plurality of reference cells, and connects the one selected reference cell to the second input terminal of the at least one sense amplifier.

摘要翻译： 电阻存储器包括多个存储单元，具有相互不同的电阻值的多个参考单元，至少一个读出放大器，其具有连接到从多个存储单元中选择的一个选定存储单元的第一输入端， 读取，以及连接到在读取时从多个参考单元中选择的一个选择的参考单元的第二输入端子，以及保持所述至少一个读出放大器的偏移信息的一个锁存电路。 电阻存储器还包括解码器，其根据偏移信息从多个参考单元中选择一个选定的参考单元，并将所选择的一个参考单元连接到至少一个读出放大器的第二输入端。

公开(公告)号：US07936591B2

公开(公告)日：2011-05-03

申请号：US12356722

申请日：2009-01-21

申请人： Kiyotaro Itagaki ,  Yoshihiro Ueda

发明人： Kiyotaro Itagaki ,  Yoshihiro Ueda

IPC分类号： G11C11/00

CPC分类号： G11C11/1675 ,  G11C11/1673

摘要： A word line voltage is applied to a plurality of word lines. A read/write voltage is applied to a plurality of bit lines. The read/write voltage is applied to a plurality of source lines. A word line selector selects the word line and applies the word line voltage. A driver applies a predetermined voltage to the bit line and the source line, thereby supplying a current to the memory cell. A read circuit reads a first current having flowed through the memory cell, and determines data stored in the memory cell. When performing the read, the driver supplies a second current to second bit lines among other bit lines, which are adjacent to the first bit line through which the first current has flowed. The second current generates a magnetic field in a direction to suppress a write error in the memory cell from which data is to be read.

摘要翻译： 字线电压被施加到多个字线。 读/写电压被施加到多个位线。 读/写电压被施加到多条源极线。 字线选择器选择字线并施加字线电压。 驱动器将预定电压施加到位线和源极线，从而向存储器单元提供电流。 读取电路读取已经流过存储器单元的第一电流，并且确定存储在存储单元中的数据。 当执行读取时，驱动器向与第一电流流过的第一位线相邻的其它位线中的第二位线提供第二电流。 第二电流在抑制要从其读取数据的存储单元中的写入错误的方向上产生磁场。

公开(公告)号：US07529113B2

公开(公告)日：2009-05-05

申请号：US11736300

申请日：2007-04-17

申请人： Yoshihiro Ueda ,  Tsuneo Inaba

发明人： Yoshihiro Ueda ,  Tsuneo Inaba

IPC分类号： G11C5/06

CPC分类号： G11C11/16

摘要： A magnetic storage device includes magnetoresistance effect elements. First and second write lines extend along a first direction. Current flows in the first and second write lines only in the first direction and a second direction opposite to the first direction, respectively. A third write line extends along a third direction orthogonal to the first direction. The elements are respectively placed where the first and third write lines cross and the second and third write lines cross. First and second electrodes are provided between the first and third write lines and between the second and third write lines. First and second plugs are respectively connected to the first and second electrodes. The first plug stands at a position apart from the first write line along the third direction. The second plug stands at a position apart from the second write line along the opposite direction to the third direction.

摘要翻译： 磁存储装置包括磁阻效应元件。 第一和第二写入线沿着第一方向延伸。 电流仅在第一方向和与第一方向相反的第二方向上分别在第一和第二写入线中流动。 第三写入线沿着与第一方向正交的第三方向延伸。 元件分别放置在第一和第三写入线交叉的位置，第二和第三写入线交叉。 第一和第二电极设置在第一和第三写入线之间以及第二和第三写入线之间。 第一和第二插头分别连接到第一和第二电极。 第一插头位于沿着第三方向与第一写入线分开的位置处。 第二插头沿着与第三方向相反的方向站立在与第二写入线分开的位置处。

公开(公告)号：US08189363B2

公开(公告)日：2012-05-29

申请号：US12543793

申请日：2009-08-19

申请人： Kenji Tsuchida ,  Yoshihiro Ueda

发明人： Kenji Tsuchida ,  Yoshihiro Ueda

IPC分类号： G11C11/00 ,  G11C7/02

CPC分类号： G11C11/1673 ,  G11C11/1659 ,  G11C11/1675

摘要： A resistance change memory includes two memory cell arrays each including a plurality of memory cells, the memory cells including variable resistive elements, two reference cell arrays provided to correspond to the two memory cell arrays, respectively, and each including a plurality of reference cells, the reference cells having a reference value, and a sense amplifier shared by the two memory cell arrays and detecting data in an accessed memory cell by use of a reference cell array corresponding to a second memory cell array different from a first memory cell array including the accessed memory cell. In reading the data, a particular reference cell in one reference cell array is always activated for an address space based on one memory cell array as a unit.

摘要翻译： 电阻变化存储器包括两个存储单元阵列，每个存储单元阵列包括多个存储单元，存储单元包括可变电阻元件，分别提供给两个存储单元阵列的两个参考单元阵列，每个参考单元阵列包括多个参考单元， 所述参考单元具有参考值，以及由所述两个存储单元阵列共享的读出放大器，并且通过使用与包括所述存储单元阵列的第一存储单元阵列不同的第二存储单元阵列对应的参考单元阵列来检测所访问的存储器单元中的数据 存取存储单元 在读取数据时，一个参考单元阵列中的特定参考单元总是基于一个存储单元阵列作为单元而被激活用于地址空间。

公开(公告)号：US08514614B2

公开(公告)日：2013-08-20

申请号：US12885175

申请日：2010-09-17

申请人： Takafumi Shimizu ,  Kenji Tsuchida ,  Yoshihiro Ueda

发明人： Takafumi Shimizu ,  Kenji Tsuchida ,  Yoshihiro Ueda

IPC分类号： G11C11/00

CPC分类号： G11C11/1675 ,  G11C11/1673

摘要： According to one embodiment, a magnetic memory includes a magnetoresistive element includes a fixed layer whose magnetization direction is fixed, a recording layer whose magnetization direction is variable and a nonmagnetic layer disposed between the fixed layer and the recording layer. A direction of a read current is set to a first direction in a case where an expression of MR ratio ≧|Ic+/Ic−|−1 is satisfied if a critical current of the first direction used to write the magnetoresistive element to the parallel state is set to Ic− and a critical current of a second direction used to write the magnetoresistive element to the anti-parallel state is set to Ic+.

摘要翻译： 根据一个实施例，磁存储器包括磁阻元件，其包括其磁化方向固定的固定层，其磁化方向可变的记录层和设置在固定层和记录层之间的非磁性层。 如果用于将磁阻元件写入平行的第一方向的临界电流满足MR ratio> = | Ic + / Ic- | -1的表达式的情况下，将读取电流的方向设置为第一方向 状态被设定为Ic-，将用于将磁阻元件写入反并联状态的第二方向的临界电流设定为Ic +。

公开(公告)号：US07952916B2

公开(公告)日：2011-05-31

申请号：US12366396

申请日：2009-02-05

申请人： Takashi Maeda ,  Yoshihiro Ueda ,  Kenji Tsuchida

发明人： Takashi Maeda ,  Yoshihiro Ueda ,  Kenji Tsuchida

IPC分类号： G11C11/00

CPC分类号： G11C11/1653 ,  G11C11/1673 ,  G11C11/1675

摘要： A resistance-change memory includes first and second bit lines running in the same direction, a third bit line running parallel to the first and second bit lines, fourth and fifth bit lines running in the same direction, a sixth bit line running parallel to the fourth and fifth bit lines, a first memory element which has one and the other terminals connected to the first and third bit lines, and changes to one of first and second resistance states, a first reference element having one and the other terminals connected to the fourth and sixth bit lines, and set in the first resistance state, a second reference element having one and the other terminals connected to the fifth and sixth bit lines, and set in the second resistance state, and a sense amplifier having first and second input terminals connected to the first and fourth bit lines.

摘要翻译： 电阻变化存储器包括沿相同方向运行的第一和第二位线，与第一和第二位线并行运行的第三位线，沿相同方向运行的第四和第五位线，平行于第一位线的第六位线 第四和第五位线，第一存储器元件，其具有连接到第一和第三位线的一个端子和另一个端子，并且改变为第一和第二电阻状态中的一个;第一参考元件，其中一个和另一个端子连接到 第四和第六位线，并且设置在第一电阻状态，第二参考元件，其中一个和另一个端子连接到第五和第六位线，并被设置在第二电阻状态，以及读出放大器，具有第一和第二输入 连接到第一和第四位线的端子。