公开(公告)号：US20090170252A1

公开(公告)日：2009-07-02

申请号：US12227714

申请日：2007-05-21

申请人： Takashi Nakagawa ,  Toru Tatsumi ,  Makiko Oshida ,  Nobuyuki Ikarashi ,  Kensuke Takahashi ,  Kenzo Manabe

发明人： Takashi Nakagawa ,  Toru Tatsumi ,  Makiko Oshida ,  Nobuyuki Ikarashi ,  Kensuke Takahashi ,  Kenzo Manabe

IPC分类号： H01L21/8234 ,  B05C11/00 ,  H01L21/285

CPC分类号： H01L21/28518 ,  H01L21/28052 ,  H01L21/28097 ,  H01L29/665

摘要： A formation method of a metallic compound layer includes preparing, in a chamber, a substrate having a surface on which a semiconductor material of silicon, germanium, or silicon germanium is exposed, and forming a metallic compound layer, includes: supplying a raw material gas containing a metal for forming a metallic compound with the semiconductor material to the chamber; heating the substrate to a temperature at which the raw material gas is pyrolyzed; and forming a metallic compound layer by reaction of the metal with the semiconductor material so that no layer of the metal is deposited on the substrate. A manufacturing method of a semiconductor device employs this formation method of a metallic compound layer.

摘要翻译： 金属化合物层的形成方法包括在室内制备具有硅，锗或硅锗的半导体材料露出的表面的基板，形成金属化合物层，包括：供给原料气体 含有用于与所述室形成具有所述半导体材料的金属化合物的金属; 将基板加热到原料气体被热解的温度; 以及通过金属与半导体材料的反应形成金属化合物层，使得金属层不沉积在基板上。 半导体器件的制造方法采用这种金属化合物层的形成方法。

公开(公告)号：US07968463B2

公开(公告)日：2011-06-28

申请号：US12227714

申请日：2007-05-21

申请人： Takashi Nakagawa ,  Toru Tatsumi ,  Makiko Oshida ,  Nobuyuki Ikarashi ,  Kensuke Takahashi ,  Kenzo Manabe

发明人： Takashi Nakagawa ,  Toru Tatsumi ,  Makiko Oshida ,  Nobuyuki Ikarashi ,  Kensuke Takahashi ,  Kenzo Manabe

IPC分类号： H01L21/44

CPC分类号： H01L21/28518 ,  H01L21/28052 ,  H01L21/28097 ,  H01L29/665

摘要： A formation method of a metallic compound layer includes preparing, in a chamber, a substrate having a surface on which a semiconductor material of silicon, germanium, or silicon germanium is exposed, and forming a metallic compound layer, includes: supplying a raw material gas containing a metal for forming a metallic compound with the semiconductor material to the chamber; heating the substrate to a temperature at which the raw material gas is pyrolyzed; and forming a metallic compound layer by reaction of the metal with the semiconductor material so that no layer of the metal is deposited on the substrate. A manufacturing method of a semiconductor device employs this formation method of a metallic compound layer.

摘要翻译： 金属化合物层的形成方法包括在室内制备具有硅，锗或硅锗的半导体材料露出的表面的基板，形成金属化合物层，包括：供给原料气体 含有用于与所述室形成具有所述半导体材料的金属化合物的金属; 将基板加热到原料气体被热解的温度; 以及通过金属与半导体材料的反应形成金属化合物层，使得金属层不沉积在基板上。 半导体器件的制造方法采用这种金属化合物层的形成方法。

公开(公告)号：US20100084713A1

公开(公告)日：2010-04-08

申请号：US12311428

申请日：2007-09-27

申请人： Takashi Nakagawa ,  Toru Tatsumi ,  Kenzo Manabe ,  Kensuke Takahashi ,  Makiko Oshida

发明人： Takashi Nakagawa ,  Toru Tatsumi ,  Kenzo Manabe ,  Kensuke Takahashi ,  Makiko Oshida

IPC分类号： H01L27/092 ,  H01L21/8238

CPC分类号： H01L21/823835 ,  H01L21/28079 ,  H01L21/823842 ,  H01L29/4975 ,  H01L29/66545 ,  H01L29/7833

摘要： A second mask is provided so as to cover a second gate pattern and a first gate pattern is heated to a temperature at which a material gas containing a first metal thermally decomposes, polysilicon constituting the first gate pattern is reacted with the first metal for silicidation under the conditions that the layer of the first metal does not deposit, and thus the first gate pattern is turned into a first gate electrode constituted by a silicide of the first metal. After the second mask is removed, a first mask is provided so as to cover the first electrode and the second gate pattern is heated to a temperature at which the material gas thermally decomposes, polysilicon constituting the second gate pattern is reacted with the first metal for silicidation under the conditions that the layer of the first metal does not deposit, and thus the second gate pattern is turned into a second gate electrode constituted by the silicide of the first metal. Then, the first mask is removed. With such a manufacturing method, a silicide layer is formed without adding an annealing process.

摘要翻译： 提供第二掩模以覆盖第二栅极图案，并且将第一栅极图案加热到含有第一金属的材料气体热分解的温度，构成第一栅极图案的多晶硅与第一金属进行硅化反应 第一金属层不沉积的条件，因此第一栅极图案变成由第一金属的硅化物构成的第一栅电极。 在去除第二掩模之后，提供第一掩模以覆盖第一电极，并且将第二栅极图案加热到材料气体热分解的温度，构成第二栅极图案的多晶硅与第一金属反应， 在第一金属层不沉积的条件下进行硅化，因此第二栅极图案变成由第一金属的硅化物构成的第二栅电极。 然后，删除第一个掩模。 通过这样的制造方法，不添加退火处理而形成硅化物层。

公开(公告)号：US08203176B2

公开(公告)日：2012-06-19

申请号：US12526238

申请日：2008-02-04

申请人： Takashi Nakagawa ,  Toru Tatsumi ,  Nobuyuki Ikarashi ,  Makiko Oshida

发明人： Takashi Nakagawa ,  Toru Tatsumi ,  Nobuyuki Ikarashi ,  Makiko Oshida

IPC分类号： H01L21/00

CPC分类号： H01L21/02178 ,  C01G25/00 ,  C01P2002/72 ,  C01P2006/40 ,  C04B35/4885 ,  C04B35/6325 ,  C04B2235/44 ,  C23C16/40 ,  H01B3/10 ,  H01L21/02189 ,  H01L21/02194 ,  H01L21/022 ,  H01L21/02271 ,  H01L21/0228 ,  H01L21/28194 ,  H01L21/3142 ,  H01L21/31604 ,  H01L21/31616 ,  H01L21/31641 ,  H01L27/1085 ,  H01L28/40 ,  H01L29/517 ,  H01L29/7833

摘要： To make it possible to significantly suppress the leakage current in a semiconductor device having a capacitor structure using a dielectric film. There is provided a composite oxide dielectric which is mainly composed of Zr, Al and O, and which has a composition ratio of Zr and Al in a range of (1−x):x where 0.01≦x≦0.15, and has a crystal structure. When the dielectric is set to have the Al composition in the above described range and is crystallized, the relative dielectric constant of the dielectric can be significantly increased. When the dielectric is used as a dielectric film of a capacitor of a semiconductor device, the leakage current of the capacitor can be significantly reduced.

摘要翻译： 为了能够显着地抑制具有使用电介质膜的电容器结构的半导体器件中的漏电流。 提供了主要由Zr，Al和O组成的复合氧化物电介质，其组成比为（1-x）：x，其中0.01和nlE; x＆ 晶体结构。 当电介质被设定为具有上述范围内的Al组成并且被结晶时，电介质的相对介电常数可以显着提高。 当电介质用作半导体器件的电容器的电介质膜时，电容器的漏电流可以显着降低。

公开(公告)号：US20100320520A1

公开(公告)日：2010-12-23

申请号：US12526238

申请日：2008-02-04

申请人： Takashi Nakagawa ,  Toru Tatsumi ,  Nobuyuki Ikarashi ,  Makiko Oshida

发明人： Takashi Nakagawa ,  Toru Tatsumi ,  Nobuyuki Ikarashi ,  Makiko Oshida

IPC分类号： H01L27/06 ,  H01G4/06 ,  C04B35/48 ,  B05D5/12

CPC分类号： H01L21/02178 ,  C01G25/00 ,  C01P2002/72 ,  C01P2006/40 ,  C04B35/4885 ,  C04B35/6325 ,  C04B2235/44 ,  C23C16/40 ,  H01B3/10 ,  H01L21/02189 ,  H01L21/02194 ,  H01L21/022 ,  H01L21/02271 ,  H01L21/0228 ,  H01L21/28194 ,  H01L21/3142 ,  H01L21/31604 ,  H01L21/31616 ,  H01L21/31641 ,  H01L27/1085 ,  H01L28/40 ,  H01L29/517 ,  H01L29/7833

摘要： To make it possible to significantly suppress the leakage current in a semiconductor device having a capacitor structure using a dielectric film. There is provided a composite oxide dielectric which is mainly composed of Zr, Al and O, and which has a composition ratio of Zr and Al in a range of (1−x):x where 0.01≦x≦0.15, and has a crystal structure. When the dielectric is set to have the Al composition in the above described range and is crystallized, the relative dielectric constant of the dielectric can be significantly increased. When the dielectric is used as a dielectric film of a capacitor of a semiconductor device, the leakage current of the capacitor can be significantly reduced.

摘要翻译： 为了能够显着地抑制具有使用电介质膜的电容器结构的半导体器件中的漏电流。 提供了主要由Zr，Al和O组成的复合氧化物电介质，其组成比为（1-x）：x，其中0.01和nlE; x＆ 晶体结构。 当电介质被设定为具有上述范围内的Al组成并且被结晶时，电介质的相对介电常数可以显着提高。 当电介质用作半导体器件的电容器的电介质膜时，电容器的漏电流可以显着降低。

公开(公告)号：US20110018100A1

公开(公告)日：2011-01-27

申请号：US12933946

申请日：2009-03-27

申请人： Takashi Nakagawa ,  Kaoru Mori ,  Nobuyuki Ikarashi ,  Makiko Oshida

发明人： Takashi Nakagawa ,  Kaoru Mori ,  Nobuyuki Ikarashi ,  Makiko Oshida

IPC分类号： H01L27/08 ,  H01L21/02

CPC分类号： H01L21/3142 ,  H01L21/02178 ,  H01L21/02189 ,  H01L21/02194 ,  H01L21/022 ,  H01L21/02271 ,  H01L21/0228 ,  H01L21/316 ,  H01L27/10811 ,  H01L27/10852 ,  H01L28/40

摘要： Provided is a capacitor that realizes a capacitance insulation film having a large relative permittivity and has sufficient capacitance even if an occupied space is small with a reduced amount of leakage current. A capacitor includes: a capacitance insulation film; and an upper electrode and lower electrode each formed on both sides of the capacitance insulation film. The capacitance insulation film is a complex oxide whose main ingredients are Zr, Al and O with the composition ratio of Zr to Al being set at (1−x): x (0.01≦x≦0.15) and is composed of a dielectric substance having a crystal structure. The lower electrode is composed of a conductor whose surface contiguous to at least the dielectric film has an amorphous structure.

摘要翻译： 提供一种电容器，其实现具有大的相对介电常数的电容绝缘膜，并且即使占用空间小，漏电流减少，也具有足够的电容。 电容器包括：电容绝缘膜; 以及各自形成在电容绝缘膜的两侧的上电极和下电极。 电容绝缘膜是主要成分为Zr，Al和O的复合氧化物，Zr与Al的组成比设定为（1-x）：x（0.01＆nlE; x＆nlE; 0.15），由介电材料 具有晶体结构。 下电极由与至少电介质膜相邻的表面具有非晶结构的导体构成。

公开(公告)号：US08368175B2

公开(公告)日：2013-02-05

申请号：US12933946

申请日：2009-03-27

申请人： Takashi Nakagawa ,  Kaoru Mori ,  Nobuyuki Ikarashi ,  Makiko Oshida

发明人： Takashi Nakagawa ,  Kaoru Mori ,  Nobuyuki Ikarashi ,  Makiko Oshida

IPC分类号： H01L21/02 ,  H01L21/8242

CPC分类号： H01L21/3142 ,  H01L21/02178 ,  H01L21/02189 ,  H01L21/02194 ,  H01L21/022 ,  H01L21/02271 ,  H01L21/0228 ,  H01L21/316 ,  H01L27/10811 ,  H01L27/10852 ,  H01L28/40

摘要： Provided is a capacitor that realizes a capacitance insulation film having a large relative permittivity and has sufficient capacitance even if an occupied space is small with a reduced amount of leakage current. A capacitor includes: a capacitance insulation film; and an upper electrode and lower electrode each formed on both sides of the capacitance insulation film. The capacitance insulation film is a complex oxide whose main ingredients are Zr, Al and O with the composition ratio of Zr to Al being set at (1−x): x (0.01≦x≦0.15) and is composed of a dielectric substance having a crystal structure. The lower electrode is composed of a conductor whose surface contiguous to at least the dielectric film has an amorphous structure.

摘要翻译： 提供一种电容器，其实现具有大的相对介电常数的电容绝缘膜，并且即使占用空间小，漏电流减少，也具有足够的电容。 电容器包括：电容绝缘膜; 以及各自形成在电容绝缘膜的两侧的上电极和下电极。 电容绝缘膜是主要成分为Zr，Al和O的复合氧化物，Zr与Al的组成比设定为（1-x）：x（0.01＆nlE; x＆nlE; 0.15），由介电材料 具有晶体结构。 下电极由与至少电介质膜相邻的表面具有非晶结构的导体构成。