-
1.发明申请Formation method of metallic compound layer, manufacturing method of semiconductor device, and formation apparatus for metallic compound layer 有权金属化合物层的形成方法，半导体装置的制造方法以及金属化合物层的形成装置公开(公告)号：US20090170252A1
公开(公告)日：2009-07-02
申请号：US12227714
申请日：2007-05-21
申请人： Takashi Nakagawa , Toru Tatsumi , Makiko Oshida , Nobuyuki Ikarashi , Kensuke Takahashi , Kenzo Manabe
发明人： Takashi Nakagawa , Toru Tatsumi , Makiko Oshida , Nobuyuki Ikarashi , Kensuke Takahashi , Kenzo Manabe
IPC分类号： H01L21/8234 , B05C11/00 , H01L21/285
CPC分类号： H01L21/28518 , H01L21/28052 , H01L21/28097 , H01L29/665
摘要： A formation method of a metallic compound layer includes preparing, in a chamber, a substrate having a surface on which a semiconductor material of silicon, germanium, or silicon germanium is exposed, and forming a metallic compound layer, includes: supplying a raw material gas containing a metal for forming a metallic compound with the semiconductor material to the chamber; heating the substrate to a temperature at which the raw material gas is pyrolyzed; and forming a metallic compound layer by reaction of the metal with the semiconductor material so that no layer of the metal is deposited on the substrate. A manufacturing method of a semiconductor device employs this formation method of a metallic compound layer.
摘要翻译： 金属化合物层的形成方法包括在室内制备具有硅，锗或硅锗的半导体材料露出的表面的基板，形成金属化合物层，包括：供给原料气体 含有用于与所述室形成具有所述半导体材料的金属化合物的金属; 将基板加热到原料气体被热解的温度; 以及通过金属与半导体材料的反应形成金属化合物层，使得金属层不沉积在基板上。 半导体器件的制造方法采用这种金属化合物层的形成方法。
-
2.发明授权Formation method of metallic compound layer, manufacturing method of semiconductor device, and formation apparatus for metallic compound layer 有权金属化合物层的形成方法，半导体装置的制造方法以及金属化合物层的形成装置公开(公告)号：US07968463B2
公开(公告)日：2011-06-28
申请号：US12227714
申请日：2007-05-21
申请人： Takashi Nakagawa , Toru Tatsumi , Makiko Oshida , Nobuyuki Ikarashi , Kensuke Takahashi , Kenzo Manabe
发明人： Takashi Nakagawa , Toru Tatsumi , Makiko Oshida , Nobuyuki Ikarashi , Kensuke Takahashi , Kenzo Manabe
IPC分类号： H01L21/44
CPC分类号： H01L21/28518 , H01L21/28052 , H01L21/28097 , H01L29/665
摘要： A formation method of a metallic compound layer includes preparing, in a chamber, a substrate having a surface on which a semiconductor material of silicon, germanium, or silicon germanium is exposed, and forming a metallic compound layer, includes: supplying a raw material gas containing a metal for forming a metallic compound with the semiconductor material to the chamber; heating the substrate to a temperature at which the raw material gas is pyrolyzed; and forming a metallic compound layer by reaction of the metal with the semiconductor material so that no layer of the metal is deposited on the substrate. A manufacturing method of a semiconductor device employs this formation method of a metallic compound layer.
摘要翻译： 金属化合物层的形成方法包括在室内制备具有硅，锗或硅锗的半导体材料露出的表面的基板，形成金属化合物层，包括：供给原料气体 含有用于与所述室形成具有所述半导体材料的金属化合物的金属; 将基板加热到原料气体被热解的温度; 以及通过金属与半导体材料的反应形成金属化合物层，使得金属层不沉积在基板上。 半导体器件的制造方法采用这种金属化合物层的形成方法。
-
公开(公告)号：US20100084713A1
公开(公告)日：2010-04-08
申请号：US12311428
申请日：2007-09-27
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/823835 , H01L21/28079 , H01L21/823842 , H01L29/4975 , H01L29/66545 , H01L29/7833
摘要： A second mask is provided so as to cover a second gate pattern and a first gate pattern is heated to a temperature at which a material gas containing a first metal thermally decomposes, polysilicon constituting the first gate pattern is reacted with the first metal for silicidation under the conditions that the layer of the first metal does not deposit, and thus the first gate pattern is turned into a first gate electrode constituted by a silicide of the first metal. After the second mask is removed, a first mask is provided so as to cover the first electrode and the second gate pattern is heated to a temperature at which the material gas thermally decomposes, polysilicon constituting the second gate pattern is reacted with the first metal for silicidation under the conditions that the layer of the first metal does not deposit, and thus the second gate pattern is turned into a second gate electrode constituted by the silicide of the first metal. Then, the first mask is removed. With such a manufacturing method, a silicide layer is formed without adding an annealing process.
摘要翻译： 提供第二掩模以覆盖第二栅极图案，并且将第一栅极图案加热到含有第一金属的材料气体热分解的温度，构成第一栅极图案的多晶硅与第一金属进行硅化反应 第一金属层不沉积的条件，因此第一栅极图案变成由第一金属的硅化物构成的第一栅电极。 在去除第二掩模之后，提供第一掩模以覆盖第一电极，并且将第二栅极图案加热到材料气体热分解的温度，构成第二栅极图案的多晶硅与第一金属反应， 在第一金属层不沉积的条件下进行硅化，因此第二栅极图案变成由第一金属的硅化物构成的第二栅电极。 然后，删除第一个掩模。 通过这样的制造方法，不添加退火处理而形成硅化物层。
-
4.发明授权Dielectric, capacitor using dielectric, semiconductor device using dielectric, and manufacturing method of dielectric 有权电介质，使用电介质的电容器，使用电介质的半导体器件，以及电介质的制造方法公开(公告)号：US08203176B2
公开(公告)日：2012-06-19
申请号：US12526238
申请日：2008-02-04
IPC分类号： H01L21/00
CPC分类号： H01L21/02178 , C01G25/00 , C01P2002/72 , C01P2006/40 , C04B35/4885 , C04B35/6325 , C04B2235/44 , C23C16/40 , H01B3/10 , H01L21/02189 , H01L21/02194 , H01L21/022 , H01L21/02271 , H01L21/0228 , H01L21/28194 , H01L21/3142 , H01L21/31604 , H01L21/31616 , H01L21/31641 , H01L27/1085 , H01L28/40 , H01L29/517 , H01L29/7833
摘要： To make it possible to significantly suppress the leakage current in a semiconductor device having a capacitor structure using a dielectric film. There is provided a composite oxide dielectric which is mainly composed of Zr, Al and O, and which has a composition ratio of Zr and Al in a range of (1−x):x where 0.01≦x≦0.15, and has a crystal structure. When the dielectric is set to have the Al composition in the above described range and is crystallized, the relative dielectric constant of the dielectric can be significantly increased. When the dielectric is used as a dielectric film of a capacitor of a semiconductor device, the leakage current of the capacitor can be significantly reduced.
摘要翻译： 为了能够显着地抑制具有使用电介质膜的电容器结构的半导体器件中的漏电流。 提供了主要由Zr，Al和O组成的复合氧化物电介质，其组成比为（1-x）：x，其中0.01和nlE; x＆ 晶体结构。 当电介质被设定为具有上述范围内的Al组成并且被结晶时，电介质的相对介电常数可以显着提高。 当电介质用作半导体器件的电容器的电介质膜时，电容器的漏电流可以显着降低。
-
公开(公告)号：US20070138580A1
公开(公告)日：2007-06-21
申请号：US10575785
申请日：2005-06-21
CPC分类号： H01L29/4975 , H01L21/823835 , H01L21/823842 , H01L29/66545
摘要： There is provided a semiconductor device which is capable of solving a problem of threshold control in CMOS transistor, accompanied with combination of a gate insulating film having a high dielectric constant and a metal gate electrode, and significantly enhancing performances without deterioration in reliability of a device. The semiconductor device includes a gate insulating film composed of a material having a high dielectric constant, and a gate electrode. A portion of the gate electrode making contact with the gate insulating film has a composition including silicide of metal M expressed with MxSi1-X (0 0.5) in a p-type MOSFET, and is equal to or smaller than 0.5 (X≦0.5) in a n-type MOSFET.
摘要翻译： 提供一种半导体器件，其能够解决CMOS晶体管中的阈值控制的问题，伴随着具有高介电常数的栅极绝缘膜和金属栅极电极的组合，并且显着提高性能而不劣化器件的可靠性 。 半导体器件包括由具有高介电常数的材料构成的栅极绝缘膜和栅电极。 与栅极绝缘膜接触的栅电极的一部分具有以MxSi 1-X（0
0.5），并且在n型MOSFET中等于或小于0.5（X <= 0.5）。 -
6.发明申请DIELECTRIC, CAPACITOR USING DIELECTRIC, SEMICONDUCTOR DEVICE USING DIELECTRIC, AND MANUFACTURING METHOD OF DIELECTRIC 有权使用电介质的电介质，电容器，使用介质的半导体器件以及电介质的制造方法公开(公告)号：US20100320520A1
公开(公告)日：2010-12-23
申请号：US12526238
申请日：2008-02-04
CPC分类号： H01L21/02178 , C01G25/00 , C01P2002/72 , C01P2006/40 , C04B35/4885 , C04B35/6325 , C04B2235/44 , C23C16/40 , H01B3/10 , H01L21/02189 , H01L21/02194 , H01L21/022 , H01L21/02271 , H01L21/0228 , H01L21/28194 , H01L21/3142 , H01L21/31604 , H01L21/31616 , H01L21/31641 , H01L27/1085 , H01L28/40 , H01L29/517 , H01L29/7833
摘要： To make it possible to significantly suppress the leakage current in a semiconductor device having a capacitor structure using a dielectric film. There is provided a composite oxide dielectric which is mainly composed of Zr, Al and O, and which has a composition ratio of Zr and Al in a range of (1−x):x where 0.01≦x≦0.15, and has a crystal structure. When the dielectric is set to have the Al composition in the above described range and is crystallized, the relative dielectric constant of the dielectric can be significantly increased. When the dielectric is used as a dielectric film of a capacitor of a semiconductor device, the leakage current of the capacitor can be significantly reduced.
摘要翻译： 为了能够显着地抑制具有使用电介质膜的电容器结构的半导体器件中的漏电流。 提供了主要由Zr，Al和O组成的复合氧化物电介质，其组成比为（1-x）：x，其中0.01和nlE; x＆ 晶体结构。 当电介质被设定为具有上述范围内的Al组成并且被结晶时，电介质的相对介电常数可以显着提高。 当电介质用作半导体器件的电容器的电介质膜时，电容器的漏电流可以显着降低。
-
7.发明授权Semiconductor device with silicide-containing gate electrode and method of fabricating the same 有权具有含硅化物的栅电极的半导体器件及其制造方法公开(公告)号：US07592674B2
公开(公告)日：2009-09-22
申请号：US10575785
申请日：2005-06-21
IPC分类号： H01L29/78 , H01L21/8234 , H01L21/8238
CPC分类号： H01L29/4975 , H01L21/823835 , H01L21/823842 , H01L29/66545
摘要： There is provided a semiconductor device which is capable of solving a problem of threshold control in CMOS transistor, accompanied with combination of a gate insulating film having a high dielectric constant and a metal gate electrode, and significantly enhancing performances without deterioration in reliability of a device. The semiconductor device includes a gate insulating film composed of a material having a high dielectric constant, and a gate electrode. A portion of the gate electrode making contact with the gate insulating film has a composition including silicide of metal M expressed with MxSi1-X (0 0.5) in a p-type MOSFET, and is equal to or smaller than 0.5 (X≦0.5) in a n-type MOSFET.
摘要翻译： 提供一种半导体器件，其能够解决CMOS晶体管中的阈值控制的问题，伴随着具有高介电常数的栅极绝缘膜和金属栅极电极的组合，并且显着提高性能而不劣化器件的可靠性 。 半导体器件包括由具有高介电常数的材料构成的栅极绝缘膜和栅电极。 与栅极绝缘膜接触的栅电极的一部分具有由MxSi1-X（0
0.5），并且在n型MOSFET中等于或小于0.5（X <= 0.5）。 -
公开(公告)号：US08524617B2
公开(公告)日：2013-09-03
申请号：US13147990
申请日：2010-02-26
申请人： Takashi Nakagawa , Naomu Kitano , Toru Tatsumi
发明人： Takashi Nakagawa , Naomu Kitano , Toru Tatsumi
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L21/02356 , C23C14/08 , C23C14/083 , C23C14/352 , H01L21/02145 , H01L21/02148 , H01L21/02159 , H01L21/02161 , H01L21/02178 , H01L21/02181 , H01L21/02189 , H01L21/02194 , H01L21/02266 , H01L21/28088 , H01L21/28176 , H01L21/28194 , H01L21/28282 , H01L21/316 , H01L28/40 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/6659 , H01L29/7833 , H01L29/7881 , H01L29/792 , H01L29/94
摘要： A method for manufacturing a dielectric film having a high dielectric constant is provided.The method is a method for forming, on a substrate, a dielectric film including a metal oxide containing O and elements A and B, wherein the element A comprises Hf or a mixture of Hf and Zr and the element B comprises Al or Si, which includes the steps of: forming a metal oxide having an amorphous structure which has a molar ratio between element A and element B, B/(A+B) of 0.02≦(B/(A+B))≦0.095 and a molar ratio between element A and O, O/A of 1.0
摘要翻译： 提供了具有高介电常数的电介质膜的制造方法。 该方法是在衬底上形成包含含有O和元素A和B的金属氧化物的电介质膜的方法，其中元素A包括Hf或Hf和Zr的混合物，元素B包含Al或Si， 包括以下步骤：形成具有元素A和元素B之间的摩尔比，B /（A + B）为0.02（B /（A + B））≤0.095的非晶结构的金属氧化物，摩尔比 在元素A和O之间，O / A为1.0 <（O / A）<2.0; 并在700℃以上退火具有非晶结构的金属氧化物，形成含有立方晶体含量为80％以上的结晶相的金属氧化物。
-
公开(公告)号：US20100221885A1
公开(公告)日：2010-09-02
申请号：US12761924
申请日：2010-04-16
申请人： Naomu Kitano , Takashi Nakagawa , Toru Tatsumi
发明人： Naomu Kitano , Takashi Nakagawa , Toru Tatsumi
IPC分类号： H01L21/336 , H01L21/28 , G06F19/00 , C23C14/35 , C01B21/20
CPC分类号： H01L29/42324 , C23C14/0676 , C23C14/225 , C23C14/3464 , H01L21/02178 , H01L21/02181 , H01L21/02194 , H01L21/02266 , H01L21/28273 , H01L21/28282 , H01L21/31604 , H01L21/318 , H01L29/4234 , H01L29/513 , H01L29/7881
摘要： The present invention provides a method of manufacturing a dielectric film having a high permittivity. An embodiment of the present invention is a method of manufacturing, on a substrate, a dielectric film including a metallic oxynitride containing an element A made of Hf or a mixture of Hf and Zr, an element B made of Al, and N and O. The manufacturing method includes: a step of forming a metallic oxynitride whose mole fractions of the element A, the element B, and N expressed as B/(A+B+N) has a range of 0.015≦(B/A+B+N))≦0.095 and N/(A+B+N) has a range of 0.045≦(N/(A+B+N)) and a mole fraction O/A of the element A and O has a range expressed as 1.0
摘要翻译： 本发明提供具有高介电常数的电介质膜的制造方法。 本发明的一个实施方式是在基板上制造包含含有由Hf或Hf和Zr的混合物构成的元素A的金属氮氧化物的电介质膜，由Al构成的元素B和N和O. 制造方法包括：形成金属氮氧化物的步骤，其中元素A，元素B和元素B的摩尔分数表示为B /（A + B + N）的范围为0.015＆amp; NlE;（B / A + B + N））＆nlE; 0.095和N /（A + B + N）的范围为0.045＆nlE;（N /（A + B + N）），元素A和O的摩尔分数O / 范围为1.0 <（O / A）<2.0，具有非晶结构; 以及在具有非结晶结构的金属氮氧化物上在700℃以上进行退火处理以形成具有80％以上立方晶结合比例的结晶相的金属氧氮化物的工序。
-
公开(公告)号：US08415753B2
公开(公告)日：2013-04-09
申请号：US13264955
申请日：2010-04-28
申请人： Takashi Nakagawa , Naomu Kitano , Kazuaki Matsuo , Motomu Kosuda , Toru Tatsumi
发明人： Takashi Nakagawa , Naomu Kitano , Kazuaki Matsuo , Motomu Kosuda , Toru Tatsumi
IPC分类号： H01L27/092 , H01L21/336
CPC分类号： H01L29/517 , H01L21/28088 , H01L21/823842 , H01L21/823857 , H01L29/4966 , H01L29/6659 , H01L29/7833
摘要： This invention provides a semiconductor device having a field effect transistor comprising a gate electrode comprising a metal nitride layer and a polycrystalline silicon layer, and the gate electrode is excellent in thermal stability and realizes a desired work function. In the semiconductor device, a gate insulating film 6 on a silicon substrate 5 has a high-permittivity insulating film formed of a metal oxide, a metal silicate, a metal oxide introduced with nitrogen, or a metal silicate introduced with nitrogen, the gate electrode has a first metal nitride layer 7 provided on the gate insulating film 6 and containing Ti and N, a second metal nitride layer 8 containing Ti and N, and a polycrystalline silicon layer 9, in the first metal nitride layer 7, a molar ratio between Ti and N (N/Ti) is not less than 1.1, and a crystalline orientation X1 is 1.1
摘要翻译： 本发明提供一种具有场效应晶体管的半导体器件，该场效应晶体管包括含有金属氮化物层和多晶硅层的栅电极，并且该栅电极具有优异的热稳定性并实现所需的功函数。 在半导体装置中，硅基板5上的栅极绝缘膜6具有由金属氧化物，金属硅酸盐，被引入氮的金属氧化物或导入氮的金属硅酸盐形成的高电容率绝缘膜，栅电极 具有设置在栅极绝缘膜6上并且含有Ti和N的第一金属氮化物层7，含有Ti和N的第二金属氮化物层8和多晶硅层9在第一金属氮化物层7中的摩尔比 Ti和N（N / Ti）不小于1.1，结晶取向X1为1.1
-
-
-
-
-
-
-
-
-
搜索结果
62 条记录 (耗时 0.022 秒)