公开(公告)号：US4791470A

公开(公告)日：1988-12-13

申请号：US63752

申请日：1987-06-22

申请人： Takashi Shinohe ,  Katsuhiko Takigami ,  Hiromichi Ohashi ,  Tsuneo Ogura ,  Masayuki Asaka

发明人： Takashi Shinohe ,  Katsuhiko Takigami ,  Hiromichi Ohashi ,  Tsuneo Ogura ,  Masayuki Asaka

IPC分类号： H01L29/423 ,  H01L29/74

CPC分类号： H01L29/7416 ,  H01L29/42308

摘要： A reverse conducting gate turn-off thyristor device in which a gate turn-off thyristor and a reverse conduction diode are integrally formed in the same semiconductor wafer is constituted in such a manner that a part of a gate electrode is arranged in an isolation region that is sandwiched by the gate turn-off thyristor section and the reverse conduction diode section.

摘要翻译： 在相同的半导体晶片中一体地形成栅极截止晶闸管和反向导通二极管的反向导通栅极截止晶闸管器件以这样的方式构成：栅电极的一部分被布置在隔离区 被栅极截止晶闸管部分和反向导通二极管部分夹在中间。

公开(公告)号：US4717940A

公开(公告)日：1988-01-05

申请号：US14608

申请日：1987-02-13

申请人： Takashi Shinohe ,  Katsuhiko Takigami ,  Hiromichi Ohashi ,  Akio Nakagawa

发明人： Takashi Shinohe ,  Katsuhiko Takigami ,  Hiromichi Ohashi ,  Akio Nakagawa

IPC分类号： H01L29/08 ,  H01L29/10 ,  H01L29/745 ,  H01L29/74

CPC分类号： H01L29/0839 ,  H01L29/102 ,  H01L29/7455

摘要： An MIS controlled gate turn-off thyristor includes a pnpn structure comprised of a first emitter layer, a first base layer, a second base layer and a second emitter layer, and a turn-off MIS transistor for short-circuiting the second base layer to the second emitter layer. A low impurity concentration layer is formed on the second base layer and the second emitter layer is so formed that it extends, through the low impurity concentration layer, into the second base layer. The MIS transistor is formed on the surface portion of said low impurity concentration layer.

摘要翻译： MIS控制栅极截止晶闸管包括由第一发射极层，第一基极层，第二基极层和第二发射极层构成的pnpn结构，以及用于将第二基极层短路的关断MIS晶体管 第二发射极层。 在第二基极层上形成低杂质浓度层，第二发射极层形成为通过低杂质浓度层延伸到第二基极层。 MIS晶体管形成在所述低杂质浓度层的表面部分上。

公开(公告)号：US4821083A

公开(公告)日：1989-04-11

申请号：US101790

申请日：1987-09-28

申请人： Tsuneo Ogura ,  Katsuhiko Takigami ,  Akio Nakagawa ,  Tomokazu Domon

发明人： Tsuneo Ogura ,  Katsuhiko Takigami ,  Akio Nakagawa ,  Tomokazu Domon

IPC分类号： H01L29/08 ,  H01L29/744 ,  H03K17/00 ,  H03K17/732

CPC分类号： H01L29/0834 ,  H01L29/744 ,  H03K17/732 ,  H03K2217/0036

摘要： A gate turn-off thyristor drive system with low power loss when it is in the turn-off mode, is disclosed. A first turn-off pulse of a predetermined amplitude is applied to a first gate electrode. A second turn-off pulse is applied to a second gate electrode. An amplitude of the second turn-off pulse is smaller in absolute value than that of the first turn-off pulse. The fall time of the anode current at the time of turn-off is reduced, and the initial value of the tail current of the anode current is reduced. The power loss as the product of the anode voltage and the anode current is reduced.

摘要翻译： 公开了一种在关闭模式时具有低功率损耗的栅极截止晶闸管驱动系统。 将预定幅度的第一关断脉冲施加到第一栅电极。 第二截止脉冲被施加到第二栅电极。 第二截止脉冲的幅度的绝对值小于第一截止脉冲的幅度。 在关断时的阳极电流的下降时间减少，阳极电流的尾电流的初始值减小。 作为阳极电压和阳极电流的乘积的功率损耗减小。

公开(公告)号：US5132767A

公开(公告)日：1992-07-21

申请号：US701002

申请日：1991-05-13

申请人： Tsuneo Ogura ,  Katsuhiko Takigami ,  Akio Nakagama ,  Tomokazu Domon

发明人： Tsuneo Ogura ,  Katsuhiko Takigami ,  Akio Nakagama ,  Tomokazu Domon

IPC分类号： H01L29/08 ,  H01L29/744 ,  H03K17/00 ,  H03K17/732

CPC分类号： H01L29/0834 ,  H01L29/744 ,  H03K17/732 ,  H03K2217/0036

摘要： There is disclosed a double gate GTO thyristor having a high gate gain and a high gate sensitivity, and capable of high speed turn-off. The double gate GTO thyristor comprises an anode/emitter layer, first and second base layers and cathode/emitter layer. A semiconductor layer having a conductivity type opposite to that of the anode/emitter layer is formed in the anode/emitter layer and located at a surface portion of the anode/emitter layer. A first gate electrode is connected to the first base layer, and a second gate electrode to the second base layer. An anode electrode is connected to the anode/emitter layer and all the surface of the semiconductor layer. A cathode electrode is connected to the cathode/emitter layer.

摘要翻译： 公开了具有高栅极增益和高栅极灵敏度并且能够高速关断的双栅极GTO晶闸管。 双栅极GTO晶闸管包括阳极/发射极层，第一和第二基极层以及阴极/发射极层。 在阳极/发射极层中形成具有与阳极/发射极层相反的导电类型的半导体层，并且位于阳极/发射极层的表面部分。 第一栅电极连接到第一基极层，第二栅电极连接到第二基极层。 阳极电极连接到阳极/发射极层和半导体层的所有表面。 阴极电极连接到阴极/发射极层。

公开(公告)号：US4392175A

公开(公告)日：1983-07-05

申请号：US212244

申请日：1980-12-02

申请人： Katsuhiko Takigami ,  Minami Takeuchi

发明人： Katsuhiko Takigami ,  Minami Takeuchi

IPC分类号： H03K17/082 ,  H02H3/20

CPC分类号： H03K17/0824

摘要： A protecting device includes a discriminating circuit and a protecting circuit. The GTO thyristor is operated in such a manner that a carrier storing is completed from a first time point at which the supply of a negative gate current is started to a second time point, an anode-cathode voltage increases from the second time point to a third time point and decreases from the third time point to a fourth time point, and increases again from the fourth time point. The discriminating circuit includes a circuit for obtaining an amount of change between the anode-cathode voltages at the third and fourth time points, a circuit for obtaining a ratio of the amount of change to the anode-cathode voltage at the third time point, and a comparing circuit for producing a control signal when the ratio is smaller than a given value. The protecting circuit, when receiving the control signal, stops the conduction of the GTO thyristor. It is judged whether or not the GTO thyristor is operated at a critical point to its break-down.

摘要翻译： 保护装置包括识别电路和保护电路。 GTO晶闸管的操作方式是从负栅极电流的供给开始到第二时间点的第一时间点完成载流子存储，阳极 - 阴极电压从第二时间点增加到 第三时间点，并且从第三时间点减少到第四时间点，并且从第四时间点开始再次增加。 识别电路包括用于获得在第三和第四时间点的阳极 - 阴极电压之间的变化量的电路，用于获得在第三时间点的变化量与阳极 - 阴极电压的比率的电路，以及 比较电路，用于当所述比值小于给定值时产生控制信号。 保护电路在接收到控制信号时，停止GTO晶闸管的导通。 判断GTO晶闸管是否在其分解的关键点运行。

公开(公告)号：US4156963A

公开(公告)日：1979-06-05

申请号：US863445

申请日：1977-12-22

申请人： Isamu Tsuji ,  Nobuo Itazu ,  Katsuhiko Takigami

发明人： Isamu Tsuji ,  Nobuo Itazu ,  Katsuhiko Takigami

IPC分类号： H01L29/74 ,  H01L21/331 ,  H01L21/52 ,  H01L23/48 ,  H01L23/482 ,  H01L29/41 ,  H01L29/73 ,  H01L29/744 ,  B01J17/00

CPC分类号： H01L23/4824 ,  H01L24/72 ,  H01L29/744 ,  H01L2224/48091 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/1301 ,  Y10T29/49169

摘要： A method for manufacturing a semiconductor device having a cathode layer divided into a plurality of mesa type cathode layer portions and used under pressure applied from the cathode layer side through a pressing plate, the method comprising steps of disposing a flat plate having a lateral width covering at least from the outer edge of a cathode electrode disposed on one outermost cathode layer portion to the outer edge of a cathode electrode disposed on the other outermost cathode layer portion, applying an external pressure through the flat plate, and then disposing the pressing plate.

摘要翻译： 一种半导体器件的制造方法，其具有分为多个台面型阴极层部分的阴极层，并且在通过压板从阴极层侧施加的压力下使用，该方法包括以下步骤：将具有横向宽度覆盖层 至少从设置在一个最外侧阴极层部分上的阴极电极的外边缘到设置在另一个最外侧阴极层部分上的阴极电极的外缘，通过平板板施加外部压力，然后设置压板。

公开(公告)号：US4500907A

公开(公告)日：1985-02-19

申请号：US419477

申请日：1982-09-17

申请人： Katsuhiko Takigami ,  Keiko Tokushuku

发明人： Katsuhiko Takigami ,  Keiko Tokushuku

IPC分类号： H01L21/58 ,  H01L23/48 ,  H01L23/492 ,  H01L21/603 ,  H01L23/04 ,  H01L23/10

CPC分类号： H01L24/83 ,  H01L23/492 ,  H01L24/33 ,  H01L24/72 ,  H01L2224/8319 ,  H01L2224/8385 ,  H01L2924/01005 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01061 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/1301

摘要： A pressure-applied type semiconductor device, in which a metal stamp for urging a semiconductor body is formed with a peripheral annular groove. When pressure is applied, the groove is elastically deformed. Thus, stress concentration in the semiconductor body directly under the edge of the metal stamp can be alleviated.

摘要翻译： 一种压力施加型半导体器件，其中用于推动半导体本体的金属压模形成有周边环形槽。 当施加压力时，槽弹性变形。 因此，可以减轻直接在金属印版边缘下方的半导体本体中的应力集中。

公开(公告)号：US4358785A

公开(公告)日：1982-11-09

申请号：US127092

申请日：1980-03-04

申请人： Katsuhiko Takigami ,  Makoto Azuma

发明人： Katsuhiko Takigami ,  Makoto Azuma

IPC分类号： H01L25/11 ,  H01L21/52 ,  H01L21/58 ,  H01L23/48 ,  H01L23/492 ,  H01L23/42

CPC分类号： H01L24/83 ,  H01L23/492 ,  H01L24/33 ,  H01L24/72 ,  H01L2224/8319 ,  H01L2224/8385 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01074 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/1301

摘要： A compression type semiconductor device includes a semiconductor element; at least one metal plate having substantially upright edge surfaces, a planar contacting surface engaging a first surface of the semiconductor element and a continuous curved surface interconnecting the edge surfaces and the contacting surface; and a means for pressing the contacting surface of the metal plate against the first surface of the semiconductor element. The continuous curved surface of the metal plate is so formed that at each point on the periphery of the contacting surface at least one plane normal to the contacting surface intersects the curved surface in an arcuate curve which tangentially joins the contacting surface.

摘要翻译： 压缩型半导体器件包括半导体元件; 至少一个金属板具有基本上直立的边缘表面，接合半导体元件的第一表面的平面接触表面和互连边缘表面和接触表面的连续弯曲表面; 以及用于将金属板的接触表面压靠在半导体元件的第一表面上的装置。 金属板的连续弯曲表面被形成为使得在接触表面的周边的每个点处，垂直于接触表面的至少一个平面与弯曲表面以切向连接接触表面的弧形曲线相交。