摘要:
Disclosed herein is a receiving apparatus for receiving an orthogonal frequency division multiplexing signal, namely, OFDM signal having a frame having one frame length of a plurality of patterns, including: an acquiring section configured to acquire information on a preamble signal from the OFDM signal transmitted from a transmitting apparatus in accordance with an OFDM system; a frame determining section configured to determine whether or not the one frame length is short in the frame based on the information on the preamble signal acquired from the acquiring section; and a time interpolating section configured to obtain transmission path characteristics by comparing a pilot contained in the preamble signal and a known pilot corresponding to the pilot in a phase of transmission with each other when the frame determining section determines that the one frame length is short in the frame, and interpolate a data portion in a time direction based on the transmission path characteristics thus obtained.
摘要:
Disclosed herein is A demodulating circuit including: an FFT processing section; an intercarrier interferential component removing section; an extracting section; a transmission path characteristics estimating section; an interpolating section; a symbol sequence estimating section; and an interference replica generating section.
摘要:
Disclosed herein is a reception apparatus, including, an orthogonal frequency division multiplexing signal reception section, a first filter section, a subtraction section, a second filter section, a coefficient production section, and a Fast Fourier Transformation mathematic operation section.
摘要:
A receiving apparatus includes: a deinterleaving device configured to perform a deinterleaving process on an LDPC-coded data signal having undergone an interleaving process, the LDPC representing Low Density Parity Check, by use of a memory which has columns capable of storing as many as “a” data, the “a” being an integer of at least 1; and a control device configured such that if the data signal is supplied in units of N data, the N being an integer smaller than the “a,” the control device controls the deinterleaving device to write the data signal to a predetermined address of the memory while reading previously written data from the predetermined address in a write period, the control device further controlling the deinterleaving device to stop writing the data signal to the predetermined address of the memory while reading the previously written data from the predetermined address in a write inhibit period.
摘要:
Disclosed herein is a decoding apparatus for decoding an LDPC (Low Density Parity Check) code received in a first format or a second format wherein a process to decode received values each obtained as a result of receiving the LDPC code in the first or second format includes at least F check-node processes carried out concurrently as processes of F check nodes respectively or F variable-node processes carried out concurrently as processes of F variable nodes respectively.
摘要:
A signal processing apparatus is disclosed which includes: a detection section configured such that based on a result of the error correction of a signal generated by a single carrier system, the detection section detects the presence or absence of spectrum inversion in the signal; and a selection section configured such that if the detection section detects the spectrum inversion, the selection section selects the spectrally inverted signal as the signal subject to the error correction, and that if the detection section does not detect the spectrum inversion, then the selection selects the spectrally uninverted signal as the signal subject to the error correction.
摘要:
A receiving apparatus includes: an LDPC decoding device configured such that when an LDPC-coded data signal, LDPC representing Low Density Parity Check, and an LDPC-coded transmission control signal are transmitted in multiplexed fashion, the LDPC decoding device can decode both the data signal and the transmission control signal; a holding device configured to be located upstream of the LDPC decoding device and to hold at least the transmission control signal upon receipt of the data signal and the transmission control signal; and a control device configured to control the LDPC decoding device to decode the data signal while the transmission control signal is being accumulated in the holding device and to interrupt the current decoding so as to control the LDPC decoding device to decode the transmission control signal when the transmission control signal has been accumulated in the holding device.
摘要:
Disclosed herein is a decoding apparatus for decoding an LDPC code, the decoding apparatus including: a message computation section configured to carry out a process of decoding received values, where notation F denotes a non-unity measure of the integer P, and outputting F messages; a shift section configured to carry out F×F cyclic shift operations on the F messages and output F messages; a storage section configured to store the F messages and allow the stored F messages to be read out or to store F received values cited above and allow the stored F received values to be read out; and a control section configured to control an operation to supply a unit composed of the F received values to the message computation section by carrying out at least a column rearrangement process or a process equivalent to the column rearrangement process on the received values.
摘要:
Disclosed herein is a decoding device including: an extracting section, a storing section, an allocating section, and a decoding section. The extracting section acquires data containing plural code words and information other than the plural code words in one frame, and extracts the plural code words from the data every one code word. The storing section at least stores the one code word extracted by the extracting section. The allocating section sets time obtained by dividing time for the one frame by the number of code words contained in the one frame as time allocated to decoding of one code word. The decoding section decodes the code word within the time allocated by the allocating section.