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1.发明授权Semiconductor memory device for performing parallel operations on hierarchical data lines 失效用于在分层数据线上执行并行操作的半导体存储器件
公开(公告)号：US5386394A
公开(公告)日：1995-01-31
申请号：US114633
申请日：1993-09-02
申请人： Takayuki Kawahara , Masakazu Aoki , Yoshinobu Nakagome , Makoto Hanawa , Kunio Uchiyama , Masayuki Nakamura , Goro Kitsukawa , Kanji Oishi
发明人： Takayuki Kawahara , Masakazu Aoki , Yoshinobu Nakagome , Makoto Hanawa , Kunio Uchiyama , Masayuki Nakamura , Goro Kitsukawa , Kanji Oishi
IPC分类号： G06F12/08 , G11C7/10 , G11C11/401 , G11C11/409 , G11C7/00 , G11C11/40
CPC分类号： G11C7/1048 , G11C7/1006
摘要： The semiconductor device has more-significant global data lines and less-significant data lines hierarchically formed, and switches for controlling the more-significant global data lines and the less-significant data lines to be connected each other. In addition, the semiconductor device has the unit for precharging the global data lines independently of the data lines.
摘要翻译： 半导体器件具有分层形成的更重要的全局数据线和较不重要的数据线，以及用于控制更有意义的全局数据线和不太重要的数据线彼此连接的开关。 此外，半导体器件具有用于独立于数据线预充电全局数据线的单元。
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2.发明授权Single chip pipeline data processor using instruction and operand cache memories for parallel operation of instruction control and executions unit 失效单芯片流水线数据处理器采用指令和操作数缓存存储器，用于并行操作指令控制和执行单元
公开(公告)号：US4989140A
公开(公告)日：1991-01-29
申请号：US323125
申请日：1989-03-13
IPC分类号： G06F9/30 , G06F9/312 , G06F9/34 , G06F9/345 , G06F9/38 , G06F9/445 , G06F12/00 , G06F12/02 , G06F12/08 , G06F12/10 , G06F12/12 , G06F13/16 , G06F15/78
CPC分类号： G06F9/30047 , G06F12/0848 , G06F12/0891 , G06F9/30043 , G06F9/3802 , G06F9/3824
摘要： A data processor for executing instructions using operand data stored in a main memory includes an instruction control unit having a first associative memory storing instruction read out from the main memory, and an instruction controller reading out an instruction from the first associative memory when the instruction is present in the first associative memory and from the main memory when the instruction is not present in the first associative memory the instruction control unit produces an output the instruction to be executed. An instruction execution unit has a second associative memory that stores operand data read out from the main memory, and an instruction executioner executing the instruction by using operand data read out from the second associative memory when the operand data is present in the second associative memory and from the main memory when the operand data is not present in the second associative memory.
摘要翻译： 用于使用存储在主存储器中的操作数数据执行指令的数据处理器包括指令控制单元，该指令控制单元具有从主存储器读出的第一相关存储器存储指令，以及指令控制器，当该指令为指令时，从第一关联存储器读出指令 存在于第一关联存储器中，并且当指令不存在于第一关联存储器中时，指令控制单元产生要执行的指令的输出。 指令执行单元具有第二关联存储器，其存储从主存储器读出的操作数数据，以及指令执行器，当所述操作数数据存在于所述第二关联存储器中时，通过使用从所述第二关联存储器读出的操作数据来执行所述指令; 当操作数数据不存在于第二关联存储器中时，从主存储器。
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公开(公告)号：US06272596B1
公开(公告)日：2001-08-07
申请号：US09396414
申请日：1999-09-15
IPC分类号： G06F1202
CPC分类号： G06F9/30047 , G06F9/30043 , G06F9/3802 , G06F9/3824 , G06F12/0848 , G06F12/0891
摘要： A data processor for executing instructions using operand data stored in a main memory includes an instruction control unit having a first associative memory storing instructions read out from the main. The data processor also includes an instruction controller reading out an instruction from the first associative memory when the instruction is present in the first associative memory and reading an instruction from the main memory when the instruction is not present in the first associative memory. The controller also has an output the instruction to be executed. An instruction execution unit has a second associative memory storing operand data read out from the main memory. An instruction executor executes the instruction by using operand data read out from the second associative memory when the operand data is present in the second associative memory and from the main memory when the operand data is not present in the second associative memory.
摘要翻译： 用于使用存储在主存储器中的操作数数据执行指令的数据处理器包括指令控制单元，其具有存储从主存储器读出的指令的第一关联存储器。 当指令存在于第一关联存储器中时，数据处理器还包括从第一关联存储器读取指令的指令控制器，并且当指令不存在于第一关联存储器中时，从主存储器读取指令。 控制器还具有要执行的指令的输出。 指令执行单元具有存储从主存储器读出的操作数数据的第二关联存储器。 当操作数数据存在于第二关联存储器中时，当操作数数据不存在于第二关联存储器中时，指令执行器通过使用从第二关联存储器读出的操作数数据执行指令。
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公开(公告)号：US5974533A
公开(公告)日：1999-10-26
申请号：US113550
申请日：1998-07-10
IPC分类号： G06F9/30 , G06F9/312 , G06F9/34 , G06F9/345 , G06F9/38 , G06F9/445 , G06F12/00 , G06F12/02 , G06F12/08 , G06F12/10 , G06F12/12 , G06F13/16 , G06F15/78
CPC分类号： G06F9/30047 , G06F12/0848 , G06F12/0891 , G06F9/30043 , G06F9/3802 , G06F9/3824
摘要： A data processor for executing instructions using operand data stored in a main memory includes an instruction control unit having a first associative memory storing instructions read out from the main memory. The data processor also includes an instruction controller reading out an instruction from the first associative memory when the instruction is present in the first associative memory and reading an instruction from the main memory when the instruction is not present in the first associative memory. The controller also has as an output instruction to be executed. An instruction execution unit has a second associative memory storing operand data read out from the main memory. An instruction executioner executes the instruction by using operand data read out from the second associative memory when the operand data is present in the second associative memory and from the main memory when the operand data is not present in the second associative memory.
摘要翻译： 用于使用存储在主存储器中的操作数数据执行指令的数据处理器包括指令控制单元，其具有存储从主存储器读出的指令的第一关联存储器。 当指令存在于第一关联存储器中时，数据处理器还包括从第一关联存储器读取指令的指令控制器，并且当指令不存在于第一关联存储器中时，从主存储器读取指令。 控制器还具有要执行的输出指令。 指令执行单元具有存储从主存储器读出的操作数数据的第二关联存储器。 当操作数数据存在于第二关联存储器中时，当操作数数据不存在于第二关联存储器中时，指令执行器通过使用从第二关联存储器读出的操作数数据执行指令。
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5.发明授权
公开(公告)号：US5349672A
公开(公告)日：1994-09-20
申请号：US503128
申请日：1990-04-03
CPC分类号： G06F9/3802 , G06F12/0848 , G06F12/0891 , G06F9/3824
摘要： A data processor is used with a main memory that stores operand data and instructions. The data processor itself includes two cache memories, one of which stores logical instruction addresses and corresponding instructions while the other stores logical operand addresses and corresponding operand data. A selector chooses whether a logical operand address or logical instruction address should access the respective cache memory or the main memory to obtain an instruction or operand data. Furthermore, the processor includes the capability of invalidating all of the data in either the instruction cache memory or operand cache memory based on a software instruction signal received at a purge unit.
摘要翻译： 数据处理器与存储操作数数据和指令的主存储器一起使用。 数据处理器本身包括两个高速缓冲存储器，其中之一存储逻辑指令地址和对应的指令，而另一个存储逻辑操作数地址和相应的操作数数据。 选择器选择逻辑操作数地址或逻辑指令地址是否应该访问相应的高速缓冲存储器或主存储器以获得指令或操作数据。 此外，处理器包括基于在清除单元处接收的软件指令信号使指令高速缓冲存储器或操作数高速缓冲存储器中的所有数据无效的能力。
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6.发明授权Data processor capable of executing an instruction that makes a cache memory ineffective 失效能够执行使高速缓冲存储器无效的指令的数据处理器公开(公告)号：US06779102B2
公开(公告)日：2004-08-17
申请号：US09886267
申请日：2001-06-22
IPC分类号： G06F1578
CPC分类号： G06F9/30047 , G06F9/30043 , G06F9/3802 , G06F9/3824 , G06F12/0848 , G06F12/0891
摘要： A data processor formed on a LSI chip has an instruction address generator, an instruction cache memory having entries each storing an instruction address and an instruction corresponding to the instruction address, an instruction decoder decoding an instruction from said cache memory corresponding to an instruction address from said instruction address generator, an operand address generator generating an operand address in response to an output signal of said instruction decoder, and an operand cache memory having entries each storing an operand address and operand data corresponding to the operand address in its entry. The data processor executes an instruction that makes entries in both of said instruction cache memory and said operand cache memory ineffective.
摘要翻译： 形成在LSI芯片上的数据处理器具有指令地址发生器，指令高速缓冲存储器，其具有各自存储指令地址的条目和与该指令地址对应的指令，指令译码器从对应于指令地址的所述高速缓冲存储器解码指令 所述指令地址生成器，响应于所述指令解码器的输出信号产生操作数地址的操作数地址生成器和具有条目的操作数高速缓存存储器，每个存储操作数地址和对应于其操作数地址的操作数数据。 数据处理器执行使得在所述指令高速缓冲存储器和所述操作数高速缓冲存储器两者中的条目无效的指令。
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公开(公告)号：US5809274A
公开(公告)日：1998-09-15
申请号：US886464
申请日：1997-07-01
IPC分类号： G06F9/30 , G06F9/312 , G06F9/34 , G06F9/345 , G06F9/38 , G06F9/445 , G06F12/00 , G06F12/02 , G06F12/08 , G06F12/10 , G06F12/12 , G06F13/16 , G06F15/78
CPC分类号： G06F9/30047 , G06F12/0848 , G06F12/0891 , G06F9/30043 , G06F9/3802 , G06F9/3824
摘要： A data processor for executing instructions using operand data stored in a main memory includes an instruction control unit having a first associative memory storing instructions read out from the main memory. The data processor also includes an instruction controller reading out an instruction from the first associative memory when the instructioon is present in the first associative memory and reading an instruction from the main memory when the instruction is not present in the first associative memory. The controller also has as an output the instruction to be executed. An instruction execution unit has a second associative memory storing operand data read out from the main memory. An instruction executioner executes the instruction by using operand data read out from the second associative memory when the operand data is present in the second associative memory and from the main memory when the operand data is not present in the second associative memory.
摘要翻译： 用于使用存储在主存储器中的操作数数据执行指令的数据处理器包括指令控制单元，其具有存储从主存储器读出的指令的第一关联存储器。 当指令存在于第一关联存储器中时，数据处理器还包括从第一关联存储器读取指令的指令控制器，并且当指令不存在于第一关联存储器中时，从主存储器读取指令。 控制器还具有要执行的指令作为输出。 指令执行单元具有存储从主存储器读出的操作数数据的第二关联存储器。 当操作数数据存在于第二关联存储器中时，当操作数数据不存在于第二关联存储器中时，指令执行器通过使用从第二关联存储器读出的操作数数据执行指令。
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8.发明授权Data processor with on-chip cache memory and purge controller responsive to external signal for controlling access to the cache memory 失效具有片上高速缓冲存储器和清除控制器的数据处理器，响应于外部信号，用于控制对高速缓冲存储器的访问
公开(公告)号：US5680631A
公开(公告)日：1997-10-21
申请号：US978069
申请日：1992-11-18
IPC分类号： G06F9/30 , G06F9/312 , G06F9/34 , G06F9/345 , G06F9/38 , G06F9/445 , G06F12/00 , G06F12/02 , G06F12/08 , G06F12/10 , G06F12/12 , G06F13/16 , G06F15/78
CPC分类号： G06F9/30047 , G06F12/0848 , G06F12/0891 , G06F9/30043 , G06F9/3802 , G06F9/3824
摘要： A data processor for executing instructions using operand data stored in a main memory includes an instruction control unit having a first associative memory storing instructions read out from the main memory. The data processor also includes an instruction controller reading out an instruction from the first associative memory when the instruction is present in the first associative memory and reading an instruction from the main memory when the instruction is not present in the first associative memory. The controller also has as an output; and an instruction execution unit has a second associative memory storing operand data read out from the main memory. An instruction executioner executes the instruction by using operand data read out from the second associative memory when the operand data is present in the second associative memory and from the main memory when the operand data is not present in the second associative memory.
摘要翻译： 用于使用存储在主存储器中的操作数数据执行指令的数据处理器包括指令控制单元，其具有存储从主存储器读出的指令的第一关联存储器。 当指令存在于第一关联存储器中时，数据处理器还包括从第一关联存储器读取指令的指令控制器，并且当指令不存在于第一关联存储器中时，从主存储器读取指令。 控制器也有输出; 并且指令执行单元具有存储从主存储器读出的操作数数据的第二关联存储器。 当操作数数据存在于第二关联存储器中时，当操作数数据不存在于第二关联存储器中时，指令执行器通过使用从第二关联存储器读出的操作数数据执行指令。
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9.发明授权Data processor having two instruction registers connected in cascade and two instruction decoders 失效数据处理器具有串联连接的两个指令寄存器和两个指令解码器
公开(公告)号：US5301285A
公开(公告)日：1994-04-05
申请号：US940762
申请日：1992-09-04
申请人： Makoto Hanawa , Osamu Nishii , Susumu Narita , Kunio Uchiyama
发明人： Makoto Hanawa , Osamu Nishii , Susumu Narita , Kunio Uchiyama
CPC分类号： G06F9/3822
摘要： A data processor is provided with a first register storing a first half word of one instruction; a second register storing a second half word of the instruction; a first decoder decoding the first half word and at the same time detecting whether there exists an addressing extension portion between the first half word and the second half word; a second decoder decoding the second half word; and, a decode result generating circuit, to which a detection signal of the first decoder indicates whether the addressing extension portion exists. A decode result of the first decoder and a decode result of the second decoder are supplied to the decode result generating circuit. An extension portion register is provided to store the addressing extension portion. When the first decoder detects the addressing extension portion, the decode result generating circuit invalidates the decode result of the second decoder. On the other hand, in the case where there exists no addressing extension portion, the decode result generating circuit judges, on the basis of the detection signal, that the decode result of the second decoder is valid.
摘要翻译： 数据处理器设置有存储一个指令的前半字的第一寄存器; 存储指令的第二个半字的第二寄存器; 解码所述前半字，并且同时检测在所述前半字和所述第二半字之间是否存在寻址扩展部分的第一解码器; 解码所述第二半字的第二解码器; 以及第一解码器的检测信号指示寻址扩展部分是否存在的解码结果生成电路。 第一解码器的解码结果和第二解码器的解码结果被提供给解码结果生成电路。 提供扩展部分寄存器以存储寻址扩展部分。 当第一解码器检测到寻址扩展部分时，解码结果生成电路使第二解码器的解码结果无效。 另一方面，在不存在寻址扩展部的情况下，解码结果生成电路根据检测信号判断第二解码器的解码结果有效。
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10.发明授权Single-chip pipeline processor for fetching/flushing instruction/data caches in response to first/second hit/mishit signal respectively detected in corresponding to their logical addresses 失效单芯片流水线处理器，用于根据其逻辑地址分别检测到的第一/第二命中/虚拟信号来提取/刷新指令/数据高速缓存
公开(公告)号：US5206945A
公开(公告)日：1993-04-27
申请号：US606804
申请日：1990-10-31
CPC分类号： G06F9/3802 , G06F12/0848 , G06F12/0891 , G06F9/30047 , G06F9/3824
摘要： A data processor for executing instructions using operand data stored in a main memory includes an instruction control unit having a first associative memory storing instructions read out from the main memory, and an instruction controller reading out an instruction from the first associative memory when the instruction is present in the first associative memory and from the main memory when the instruction is not present in the first associative memory the instruction control unit produces an output to be executed. An instruction execution unit has a second associative memory that stores operand data read out from the main memory, and an instruction executioner executing the instruction by using operand data read out from the second associative memory when the operand data is present in the second associative memory and from the main memory when the operand data is not present in the second associative memory.
摘要翻译： 用于使用存储在主存储器中的操作数数据执行指令的数据处理器包括指令控制单元，该指令控制单元具有存储从主存储器读出的指令的第一关联存储器，以及指令控制单元，当指令为指令时，从第一关联存储器读出指令 存在于第一关联存储器中，并且当指令不存在于第一关联存储器中时，指令控制单元产生要执行的输出。 指令执行单元具有第二关联存储器，其存储从主存储器读出的操作数数据，以及指令执行器，当所述操作数数据存在于所述第二关联存储器中时，通过使用从所述第二关联存储器读出的操作数据来执行所述指令; 当操作数数据不存在于第二关联存储器中时，从主存储器。
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