公开(公告)号：US07394134B2

公开(公告)日：2008-07-01

申请号：US11095709

申请日：2005-03-31

申请人： Takayuki Saiki ,  Kazuhiko Okawa

发明人： Takayuki Saiki ,  Kazuhiko Okawa

IPC分类号： H01L23/62

CPC分类号： H01L27/0288

摘要： A semiconductor device is provided having a high performance resistance element. In an N-type well isolated by an insulating film, two higher concentration N-type regions are formed. An interlayer insulating film is also formed. In a plurality of openings in the interlayer insulating film, one electrode group having a plurality of electrodes is formed on one N-type region, while a second electrode group having a plurality of electrodes is formed on the other N-type region. The relationship between the two N-type regions is between an island region and an annular region surrounding the island. The annular region of the N-type well between the island region and the annular region serves as a resistor R. Thus, discharge channels for charges applied excessively because of ESD or the like evenly exist in the periphery (four regions) of the one N-type region.

摘要翻译： 提供具有高性能电阻元件的半导体器件。 在绝缘膜隔离的N型阱中，形成两个较高浓度的N型区域。 还形成层间绝缘膜。 在层间绝缘膜的多个开口中，在一个N型区域上形成具有多个电极的一个电极组，而在另一个N型区域上形成具有多个电极的第二电极组。 两个N型区域之间的关系在岛状区域和围绕岛状物的环状区域之间。 岛状区域和环状区域之间的N型阱的环状区域用作电阻R.因此，由于ESD等而过度施加的电荷的放电通道在一个N的周边（四个区域）中均匀地存在 型区域。

公开(公告)号：US06455897B1

公开(公告)日：2002-09-24

申请号：US09866782

申请日：2001-05-30

申请人： Kazuhiko Okawa ,  Takayuki Saiki

发明人： Kazuhiko Okawa ,  Takayuki Saiki

IPC分类号： H01L2972

CPC分类号： H01L27/0259 ,  H01L27/0288

摘要： A semiconductor device, including an electrostatic discharge protection circuit capable of preventing current from being concentrated in a hot spot through a silicide layer, includes an N-type MOS transistor having a first diffusion region on a semiconductor substrate. This N-type MOS transistor is isolated from another MOS transistor by a first element isolation region. A second diffusion region is formed between the first diffusion region and first element isolation region. The first and second diffusion regions are separated by a second element isolation region. A silicide is formed on the surface of the semiconductor substrate excluding the first and second element isolation regions. A pad is connected to the second N-type diffusion region through a contact. An electrostatic charge injection through the pad and contact is discharged mainly through a first discharge path guided to a channel (P-type well) of the N-type MOS transistor through the second diffusion region (N-type), N-type well under the second element isolation region, and second diffusion region (N-type). A discharge path passing through the silicide layer rarely functions as a discharge path, since the contact resistance value between the silicide layer and first diffusion region is greater than the resistance value of the first diffusion region.

摘要翻译： 包括能够防止电流通过硅化物层集中在热点中的静电放电保护电路的半导体器件包括在半导体衬底上具有第一扩散区域的N型MOS晶体管。 该N型MOS晶体管通过第一元件隔离区与另一MOS晶体管隔离。 在第一扩散区域和第一元件隔离区域之间形成第二扩散区域。 第一和第二扩散区域被第二元件隔离区隔开。 除了第一元件隔离区域和第二元件隔离区域之外，在半导体基板的表面上形成硅化物。 焊盘通过触点连接到第二N型扩散区域。 通过焊盘和触点的静电电荷注入主要通过第二扩散区（N型）引导到N型MOS晶体管的通道（P型阱）的第一放电路径，N型阱下 第二元件隔离区域和第二扩散区域（N型）。 由于硅化物层和第一扩散区域之间的接触电阻值大于第一扩散区域的电阻值，所以穿过硅化物层的放电路径很少用作放电路径。

公开(公告)号：US08076748B2

公开(公告)日：2011-12-13

申请号：US12126473

申请日：2008-05-23

申请人： Takayuki Saiki ,  Kazuhiko Okawa

发明人： Takayuki Saiki ,  Kazuhiko Okawa

IPC分类号： H01L23/60

CPC分类号： H01L27/0288

摘要： A semiconductor device is provided having a high performance resistance element. In an N-type well isolated by an insulating film, two higher concentration N-type regions are formed. An interlayer insulating film is also formed. In a plurality of openings in the interlayer insulating film, one electrode group having a plurality of electrodes is formed on one N-type region, while a second electrode group having a plurality of electrodes is formed on the other N-type region. The relationship between the two N-type regions is between an island region and an annular region surrounding the island. The annular region of the N-type well between the island region and the annular region serves as a resistor R. Thus, discharge channels for charges applied excessively because of ESD or the like evenly exist in the periphery (four regions) of the one N-type region.

摘要翻译： 提供具有高性能电阻元件的半导体器件。 在绝缘膜隔离的N型阱中，形成两个较高浓度的N型区域。 还形成层间绝缘膜。 在层间绝缘膜的多个开口中，在一个N型区域上形成具有多个电极的一个电极组，而在另一个N型区域上形成具有多个电极的第二电极组。 两个N型区域之间的关系在岛状区域和围绕岛状物的环状区域之间。 岛状区域和环状区域之间的N型阱的环状区域用作电阻R.因此，由于ESD等而过度施加的电荷的放电通道在一个N的周边（四个区域）中均匀地存在 型区域。

公开(公告)号：US07242061B2

公开(公告)日：2007-07-10

申请号：US10341464

申请日：2003-01-14

申请人： Kazuhiko Okawa ,  Takayuki Saiki

发明人： Kazuhiko Okawa ,  Takayuki Saiki

IPC分类号： H01L23/62 ,  H01L29/94

CPC分类号： H01L27/12 ,  H01L21/823481 ,  H01L21/84 ,  H01L21/86 ,  H01L27/0251 ,  H01L27/088

摘要： The invention provides semiconductor devices having an output circuit in which transistors do not fail to achieve their original capability, and electrostatic breakdown is difficult to occur. A semiconductor device is equipped with a semiconductor substrate, an element isolation region formed on the semiconductor substrate, a first impurity diffusion region that is formed in the semiconductor substrate and surrounds the element isolation region, a second impurity diffusion region that is formed in the semiconductor substrate, a first wiring electrode and a second wiring electrode that are electrically connected to the first impurity diffusion region on both sides of the element isolation region, an output terminal that outputs signals to outside, a wiring that electrically connects the first wiring electrode and the second wiring electrode to the output terminal, and a third wiring electrode and a fourth wiring electrode that are electrically connected to the second impurity diffusion region corresponding to the first and second wiring electrodes.

摘要翻译： 本发明提供具有输出电路的半导体器件，其中晶体管不能达到其原始能力，并且难以发生静电击穿。 半导体器件配备有半导体衬底，形成在半导体衬底上的元件隔离区域，形成在半导体衬底中并围绕元件隔离区域的第一杂质扩散区域，形成在半导体衬底中的第二杂质扩散区域 基板，与元件隔离区域两侧的第一杂质扩散区域电连接的第一布线电极和第二布线电极，向外部输出信号的输出端子，将第一布线电极和第二布线电极电连接的布线 第二布线电极到输出端子，以及第三布线电极和第四布线电极，电连接到与第一和第二布线电极对应的第二杂质扩散区域。

公开(公告)号：US20050218454A1

公开(公告)日：2005-10-06

申请号：US11095709

申请日：2005-03-31

申请人： Takayuki Saiki ,  Kazuhiko Okawa

发明人： Takayuki Saiki ,  Kazuhiko Okawa

IPC分类号： H01L21/28 ,  H01L21/822 ,  H01L23/62 ,  H01L27/04

CPC分类号： H01L27/0288

摘要： A semiconductor device is provided having a high performance resistance element. In an N-type well isolated by an insulating film, two higher concentration N-type regions are formed. An interlayer insulating film is also formed. In a plurality of openings in the interlayer insulating film, one electrode group having a plurality of electrodes is formed on one N-type region, while a second electrode group having a plurality of electrodes is formed on the other N-type region. The relationship between the two N-type regions is between an island region and an annular region surrounding the island. The annular region of the N-type well between the island region and the annular region serves as a resistor R. Thus, discharge channels for charges applied excessively because of ESD or the like evenly exist in the periphery (four regions) of the one N-type region.

摘要翻译： 提供具有高性能电阻元件的半导体器件。 在绝缘膜隔离的N型阱中，形成两个较高浓度的N型区域。 还形成层间绝缘膜。 在层间绝缘膜的多个开口中，在一个N型区域上形成具有多个电极的一个电极组，而在另一个N型区域上形成具有多个电极的第二电极组。 两个N型区域之间的关系在岛状区域和围绕岛状物的环状区域之间。 岛状区域和环状区域之间的N型阱的环状区域用作电阻R.因此，由于ESD等而过度施加的电荷的放电通道在一个N的周边（四个区域）中均匀地存在 型区域。

公开(公告)号：US06894351B2

公开(公告)日：2005-05-17

申请号：US10329676

申请日：2002-12-27

申请人： Kazuhiko Okawa ,  Takayuki Saiki

发明人： Kazuhiko Okawa ,  Takayuki Saiki

IPC分类号： H01L29/749 ,  H01L21/822 ,  H01L21/8238 ,  H01L27/02 ,  H01L27/04 ,  H01L27/06 ,  H01L27/08 ,  H01L27/092 ,  H01L27/12 ,  H01L29/74 ,  H01L27/01 ,  H01L31/111

CPC分类号： H01L27/0262 ,  H01L27/12 ,  H01L29/7436

摘要： The invention makes it possible to form thyristers and SCRs that show a good discharge efficiency upon application of static electricity in semiconductor devices using a SOI substrate. A semiconductor device is equipped with a connection terminal for connection with an external element, a dielectric substrate having a semiconductor layer formed therein, a first region of a first conductive type that is formed in the semiconductor layer and electrically connected to the connection terminal, a second region of a second conductive type that is formed in the semiconductor layer and electrically connected to the first region, a third region of the first conductive type that is formed adjacent to the second region in the semiconductor layer, and a fourth region of the second conductive type that is formed adjacent to the third region in the semiconductor layer.

摘要翻译： 本发明使得可以形成在使用SOI衬底的半导体器件中施加静电时显示出良好的放电效率的晶体管和SCR。 半导体器件配备有用于与外部元件连接的连接端子，其中形成有半导体层的电介质基板，形成在半导体层中并电连接到连接端子的第一导电类型的第一区域， 第二导电类型的第二区域，形成在所述半导体层中并电连接到所述第一区域;所述第一导电类型的第三区域与所述半导体层中的所述第二区域相邻形成;以及第二区域， 导电型，其形成在半导体层中与第三区相邻。

公开(公告)号：US06831334B2

公开(公告)日：2004-12-14

申请号：US09866800

申请日：2001-05-30

申请人： Kazuhiko Okawa ,  Takayuki Saiki

发明人： Kazuhiko Okawa ,  Takayuki Saiki

IPC分类号： H01L2362

CPC分类号： H01L27/0255 ,  H01L27/0259

摘要： A semiconductor device including an electrostatic protection circuit capable of preventing current from being concentrated in a hot spot through a silicide layer. A plurality of salicide N-type MOS transistors isolated by a first diffusion region are formed on a semiconductor substrate of this semiconductor device. An NPN lateral bipolar transistor and a Zener diode are formed as an electrostatic protection circuit for these MOS transistors. The NPN lateral bipolar transistor includes a P-type well and a second diffusion region which is formed in a region isolated by two second isolation regions. The Zener diode is formed by the PN junction between the first diffusion region of the MOS transistor and a third diffusion region. The breakdown start voltage of the Zener diode is set to be lower than the breakdown start voltage of the MOS transistor. A fourth diffusion region which makes up a Schottky diode together with the silicide layer is further provided between the silicide layer and the third diffusion region.

摘要翻译： 一种包括静电保护电路的半导体器件，能够防止电流通过硅化物层集中在热点上。 在该半导体器件的半导体衬底上形成由第一扩散区隔离的多个自对准硅化物N型MOS晶体管。 形成NPN横向双极晶体管和齐纳二极管作为这些MOS晶体管的静电保护电路。 NPN横向双极晶体管包括P型阱和形成在由两个第二隔离区域隔离的区域中的第二扩散区域。 齐纳二极管由MOS晶体管的第一扩散区域和第三扩散区域之间的PN结形成。 齐纳二极管的击穿启动电压设定为低于MOS晶体管的击穿开始电压。 在硅化物层和第三扩散区之间进一步设置与硅化物层一起构成肖特基二极管的第四扩散区域。

公开(公告)号：US20070002509A1

公开(公告)日：2007-01-04

申请号：US11477720

申请日：2006-06-30

申请人： Takashi Kumagai ,  Hisanobu Ishiyama ,  Kazuhiro Maekawa ,  Satoru Ito ,  Takashi Fujise ,  Junichi Karasawa ,  Satoru Kodaira ,  Takayuki Saiki ,  Hiroyuki Takamiya

发明人： Takashi Kumagai ,  Hisanobu Ishiyama ,  Kazuhiro Maekawa ,  Satoru Ito ,  Takashi Fujise ,  Junichi Karasawa ,  Satoru Kodaira ,  Takayuki Saiki ,  Hiroyuki Takamiya

IPC分类号： H02H9/00

CPC分类号： G09G3/3688 ,  G02F1/13452 ,  G02F2202/28 ,  G09G3/3696 ,  G09G2300/0426 ,  G09G2310/027

摘要： An integrated circuit device includes a pad PDx and an electrostatic discharge protection element ESDx formed in a rectangular region and electrically connected with the pad PDx. The pad PDx is disposed in an upper layer of the electrostatic discharge protection element ESDx so that an arrangement direction of the pads is parallel to a long side direction of the region in which the electrostatic discharge protection element ESDx is formed, and the pad PDx overlaps part or the entirety of the electrostatic discharge protection element ESDx.

摘要翻译： 集成电路器件包括形成在矩形区域中并与焊盘PDx电连接的焊盘PDx和静电放电保护元件ESDx。 垫PDx设置在静电放电保护元件ESDx的上层中，使得焊盘的布置方向平行于形成有静电放电保护元件ESDx的区域的长边方向，并且焊盘PDx重叠 部分或全部静电放电保护元件ESDx。

公开(公告)号：US08547773B2

公开(公告)日：2013-10-01

申请号：US11477714

申请日：2006-06-30

申请人： Takayuki Saiki ,  Satoru Ito ,  Masahiko Moriguchi ,  Takashi Kumagai ,  Hisanobu Ishiyama ,  Takashi Fujise ,  Junichi Karasawa ,  Satoru Kodaira ,  Kazuhiro Maekawa

发明人： Takayuki Saiki ,  Satoru Ito ,  Masahiko Moriguchi ,  Takashi Kumagai ,  Hisanobu Ishiyama ,  Takashi Fujise ,  Junichi Karasawa ,  Satoru Kodaira ,  Kazuhiro Maekawa

IPC分类号： G11C8/00

CPC分类号： G09G3/3674 ,  G09G3/3685

摘要： An integrated circuit device includes at least one data driver block for driving data lines, a plurality of control transistors TC1 and TC2, each of the control transistors being provided corresponding to each output line of the data driver block and controlled by using a common control signal, and a pad arrangement region in which data driver pads P1 and P2 for electrically connecting the data lines and the output lines QL1 and QL2 of the data driver block are disposed. The control transistors TC1 and TC2 are disposed in the pad arrangement region.

摘要翻译： 集成电路装置包括用于驱动数据线的至少一个数据驱动器块，多个控制晶体管TC1和TC2，每个控制晶体管对应于数据驱动器模块的每个输出线提供，并通过使用公共控制信号 以及其中设置用于电连接数据线和数据驱动器块的输出线QL1和QL2的数据驱动器焊盘P1和P2的焊盘布置区域。 控制晶体管TC1和TC2设置在焊盘布置区域中。

公开(公告)号：US20080252634A1

公开(公告)日：2008-10-16

申请号：US12081008

申请日：2008-04-09

申请人： Shinya Sato ,  Takayuki Saiki ,  Hiroyuki Takamiya ,  Masaaki Abe

发明人： Shinya Sato ,  Takayuki Saiki ,  Hiroyuki Takamiya ,  Masaaki Abe

IPC分类号： G06F3/038 ,  H03K19/0175

CPC分类号： H03K19/00315

摘要： An integrated circuit device includes a first circuit block that includes low-voltage transistors (LVTr) and operates using a first high-potential power supply voltage and a first low-potential power supply voltage, a second circuit block that includes low-voltage transistors (LVTr) and operates using a second high-potential power supply voltage and a second low-potential power supply voltage that differ in power supply system from the first circuit block, and an interface circuit (I/O buffer) provided between the first circuit block and the second circuit block. The interface circuit (I/O buffer) includes medium-voltage transistors (MVTr: transistors of which the thickness of the gate insulating film is larger than that of the low-voltage transistors (LVTr)). An electrostatic discharge protection circuit formed of bidirectional diodes is provided between a first and second low-potential power supply nodes.

摘要翻译： 集成电路器件包括包括低压晶体管（LVTr）的第一电路块，并且使用第一高电位电源电压和第一低电位电源电压进行操作，第二电路块包括低压晶体管（ LVTr），并且使用电源系统与第一电路块不同的第二高电位电源电压和第二低电位电源电压进行操作，以及设置在第一电路块之间的接口电路（I / O缓冲器） 和第二电路块。 接口电路（I / O缓冲器）包括中压晶体管（MVTr：栅极绝缘膜的厚度大于低压晶体管的厚度（LVTr）的晶体管）。 在第一和第二低电位电源节点之间设置由双向二极管形成的静电放电保护电路。