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公开(公告)号：US08433882B2
公开(公告)日：2013-04-30
申请号：US13157011
申请日：2011-06-09
申请人： Takehiko Kurashige , Junji Yano
发明人： Takehiko Kurashige , Junji Yano
IPC分类号： G06F12/00
CPC分类号： G06F3/0659 , G06F3/0605 , G06F3/0689
摘要： According to one embodiment, a disk array control device manages a plurality of drives as a single logical drive. The disk array control device includes a first register configured to store a to-be-accessed drive number which is designated by a host, and a control module. The control module is configured to receive a command from the host, determine whether the received command is a predetermined command which is used for maintenance of each of the drives, and execute, in a case where the received command is the predetermined command, a pass-through process of sending the received command to the drive which is designated by the to-be-accessed drive number in the first register.
摘要翻译： 根据一个实施例，磁盘阵列控制装置将多个驱动器管理为单个逻辑驱动器。 磁盘阵列控制装置包括被配置为存储由主机指定的要访问的驱动器号的第一寄存器和控制模块。 控制模块被配置为从主机接收命令，确定所接收的命令是否是用于维护每个驱动器的预定命令，并且在接收到的命令是预定命令的情况下执行通过 通过将接收到的命令发送到由第一寄存器中的被访问驱动器号指定的驱动器。
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公开(公告)号：US20110238913A1
公开(公告)日：2011-09-29
申请号：US13157011
申请日：2011-06-09
申请人： Takehiko Kurashige , Junji Yano
发明人： Takehiko Kurashige , Junji Yano
IPC分类号： G06F12/00
CPC分类号： G06F3/0659 , G06F3/0605 , G06F3/0689
摘要： According to one embodiment, a disk array control device manages a plurality of drives as a single logical drive. The disk array control device includes a first register configured to store a to-be-accessed drive number which is designated by a host, and a control module. The control module is configured to receive a command from the host, determine whether the received command is a predetermined command which is used for maintenance of each of the drives, and execute, in a case where the received command is the predetermined command, a pass-through process of sending the received command to the drive which is designated by the to-be-accessed drive number in the first register.
摘要翻译： 根据一个实施例，磁盘阵列控制装置将多个驱动器管理为单个逻辑驱动器。 磁盘阵列控制装置包括被配置为存储由主机指定的要访问的驱动器号的第一寄存器和控制模块。 控制模块被配置为从主机接收命令，确定所接收的命令是否是用于维护每个驱动器的预定命令，并且在接收到的命令是预定命令的情况下执行通过 通过将接收到的命令发送到由第一寄存器中的被访问驱动器号指定的驱动器。
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公开(公告)号：US20100106905A1
公开(公告)日：2010-04-29
申请号：US12485686
申请日：2009-06-16
申请人： Takehiko Kurashige , Junji Yano
发明人： Takehiko Kurashige , Junji Yano
IPC分类号： G06F12/00
CPC分类号： G06F3/0659 , G06F3/0605 , G06F3/0689
摘要： According to one embodiment, a disk array control device manages a plurality of drives as a single logical drive. The disk array control device includes a first register configured to store a to-he-accessed drive number which is designated by a host, and a control module. The control module is configured to receive a command from the host, determine whether the received command is a predetermined command which is used for maintenance of each of the drives, and execute, in a case where the received command is the predetermined command, a pass-through process of sending the received command to the drive which is designated by the to-be-accessed drive number in the first register.
摘要翻译： 根据一个实施例，磁盘阵列控制装置将多个驱动器管理为单个逻辑驱动器。 磁盘阵列控制装置包括配置成存储由主机指定的由他访问的驱动器号码的第一寄存器和控制模块。 控制模块被配置为从主机接收命令，确定所接收的命令是否是用于维护每个驱动器的预定命令，并且在接收到的命令是预定命令的情况下执行通过 通过将接收到的命令发送到由第一寄存器中的被访问驱动器号指定的驱动器。
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公开(公告)号：US08583972B2
公开(公告)日：2013-11-12
申请号：US13486718
申请日：2012-06-01
申请人： Toshikatsu Hida , Shinichi Kanno , Hirokuni Yano , Kazuya Kitsunai , Shigehiro Asano , Junji Yano
发明人： Toshikatsu Hida , Shinichi Kanno , Hirokuni Yano , Kazuya Kitsunai , Shigehiro Asano , Junji Yano
IPC分类号： G11C29/00
CPC分类号： G06F11/1412 , G06F11/1068 , G06F11/1402 , G06F12/02 , G11C16/0483 , G11C16/3418 , G11C16/3431
摘要： A method of controlling a nonvolatile semiconductor memory including a plurality of blocks, each one of the plurality of blocks being a unit of data erasing, includes determining a monitored block as a candidate for refresh operation from among the plurality of blocks based on a predetermined condition. The method includes monitoring an error count of data stored in the monitored block and not monitoring an error count of data stored in blocks excluding the monitored block among the plurality of blocks. The method also includes performing the refresh operation on data stored in the monitored block in which the error count is larger than a first threshold value.
摘要翻译： 一种控制包括多个块的非易失性半导体存储器的方法，所述多个块中的每一个是数据擦除单元，包括：基于预定条件，将所监视的块作为所述多个块中的刷新操作的候补确定 。 该方法包括监视存储在所监视的块中的数据的错误计数，并且不监视存储在多个块中的被监视块之外的块中存储的数据的错误计数。 该方法还包括对存储在监视块中的数据执行刷新操作，其中错误计数大于第一阈值。
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公开(公告)号：US08171208B2
公开(公告)日：2012-05-01
申请号：US12529126
申请日：2009-02-10
申请人： Junji Yano , Hidenori Matsuzaki , Kosuke Hatsuda
发明人： Junji Yano , Hidenori Matsuzaki , Kosuke Hatsuda
IPC分类号： G06F12/00
CPC分类号： G06F12/0866 , G06F11/1068 , G06F12/0246 , G06F12/0804 , G06F2212/1032 , G06F2212/2022 , G06F2212/7203
摘要： A memory system includes a DRAM 20 that performs writing and readout in a unit equal to or smaller than a cluster, a NAND memory 10 that performs writing and readout in a page unit, and a management table group in which management information including storage locations of data stored in the DRAM 20 and the NAND memory 10 is stored. When a readout request is received from the outside, a data managing unit 120 notifies, when an unwritten logical address area is present in a storage area of the NAND memory to which a logical address area requested to be read out is mapped, fixed data stored in the DRAM 20 to the outside in association with the logical address area.
摘要翻译： 存储器系统包括以等于或小于簇的单位执行写入和读出的DRAM 20，以页单元执行写入和读出的NAND存储器10以及管理表组，其中管理信息包括存储位置 存储在DRAM 20和NAND存储器10中的数据被存储。 当从外部接收到读出请求时，数据管理单元120在映射了要求读出的逻辑地址区域的NAND存储器的存储区域中存在未写入的逻辑地址区域时，通知存储的固定数据 在DRAM 20中与逻辑地址区域相关联到外部。
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公开(公告)号：US20110185108A1
公开(公告)日：2011-07-28
申请号：US12529235
申请日：2009-02-10
申请人： Junji Yano , Hidenori Matsuzaki , Kosuke Hatsuda
发明人： Junji Yano , Hidenori Matsuzaki , Kosuke Hatsuda
CPC分类号： G11C16/102 , G06F11/141 , G06F11/1443 , G06F11/1471 , G11C11/5628 , G11C16/0483 , G11C16/105 , G11C29/00
摘要： A memory system includes a volatile first storing unit, a nonvolatile second storing unit in which a plurality of memory cells that can store multi-value data are arranged, the memory cells having a plurality of pages, and a controller that performs data transfer between a host apparatus and the second storing unit via the first storing unit. The controller includes a save processing unit that backs up, when, before data is written in the second storing unit in a write-once manner, data is written in a lower order page of a memory cell same as that of a page in which the data is written, the data of the lower order page and a broken-information-restoration processing unit that restores, when the data in the lower order page is broken, the broken data using the backed-up data.
摘要翻译： 存储器系统包括易失性第一存储单元，非易失性第二存储单元，其中排列可存储多值数据的多个存储器单元，存储单元具有多个页面，以及控制器，其执行数据传输 主机设备和第二存储单元。 控制器包括一个保存处理单元，其在一次写入数据被写入第二存储单元之后，当数据被写入到存储单元的低位页面中时 写入数据，低位页的数据和破损信息恢复处理单元，当低位页中的数据被破坏时，使用备份数据恢复断开的数据。
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公开(公告)号：US07904640B2
公开(公告)日：2011-03-08
申请号：US12529270
申请日：2008-09-22
申请人： Junji Yano , Hidenori Matsuzaki , Kosuke Hatsuda
发明人： Junji Yano , Hidenori Matsuzaki , Kosuke Hatsuda
IPC分类号： G06F13/00
CPC分类号： G06F12/0804 , G06F12/0246 , G06F12/0866 , G06F12/0897 , G06F2212/1016 , G06F2212/7203 , G06F2212/7205
摘要： A controller executes first processing for writing a plurality of data in a sector unit in the first storing area; second processing for flushing the data stored in the first storing area to the first input buffer in a first management unit twice or larger natural number times as large as the sector unit; third processing for flushing the data stored in the first storing area to the second input buffer in a second management unit twice or larger natural number times as large as the first management unit; fourth processing for relocating a logical block in which all pages are written in the first input buffer to the second storing area; fifth processing for relocating a logical block in which all pages are written in the second input buffer to the third storing area; and sixth processing for flushing a plurality of data stored in the second storing area to the second input buffer in the second management unit.
摘要翻译： 控制器执行用于在第一存储区域中以扇区为单位写入多个数据的第一处理; 第二处理，用于将存储在第一存储区域中的数据在第一管理单元中的第一输入缓冲器中刷新自然数倍于扇区单元的两倍或更大; 在第二管理单元中将存储在第一存储区域中的数据刷新到与第一管理单元一样大的自然数倍的两倍或更大的第二处理; 将其中将所有页面写入所述第一输入缓冲器的逻辑块重定位到所述第二存储区域的第四处理; 将其中将所有页面写入第二输入缓冲器的逻辑块重新定位到第三存储区域的第五处理; 以及第六处理，用于将存储在第二存储区域中的多个数据刷新到第二管理单元中的第二输入缓冲器。
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公开(公告)号：US20110022784A1
公开(公告)日：2011-01-27
申请号：US12529139
申请日：2009-02-10
CPC分类号： G06F12/0246 , G06F2212/7202 , G06F2212/7207 , G06F2212/7208 , G06F2212/7211
摘要： A memory system according to an embodiment of the present invention comprises: a memory amount required for management table creation is reduced by adopting a nonvolatile semiconductor memory including a plurality of parallel operation elements respectively having a plurality of physical blocks as units of data erasing and a controller that can drive the parallel operation elements in parallel and has a number-of-times-of-erasing managing unit that manages the number of times of erasing in logical block units associated with a plurality of physical blocks driven in parallel.
摘要翻译： 根据本发明的实施例的存储器系统包括：通过采用包括分别具有多个物理块的多个并行操作元件作为数据擦除单元的非易失性半导体存储器来减少管理表创建所需的存储量，并且 控制器，其可以并行驱动并行操作元件，并且具有多个次数的擦除管理单元，其管理与并行驱动的多个物理块相关联的逻辑块单元中的擦除次数。
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公开(公告)号：US20100281204A1
公开(公告)日：2010-11-04
申请号：US12529193
申请日：2008-09-22
申请人： Junji Yano , Hidenori Matsuzaki , Kosuke Hatsuda
发明人： Junji Yano , Hidenori Matsuzaki , Kosuke Hatsuda
CPC分类号： G06F12/0246 , G06F12/0804 , G06F12/0866 , G06F12/0897 , G06F2212/1016 , G06F2212/7203
摘要： A memory system includes a WC 21 from which data is read out and to which data is written in sector units by a host apparatus, an FS 12 from which data is read out and to which data is written in page units, an MS 11 from which data is read out and to which data written in track units, an FSIB 12a functioning as an input buffer for the FS 12, and an MSIB 11a functioning as an input buffer to the MS 11. An FSBB 12ac that has a capacity equal to or larger than a storage capacity of the WC 21 and stores data written in the WC 21 is provided in the FSIB12a. A data managing unit 120 that manages the respective storing units suspends, when it is judged that one kind of processing performed among the storing units exceeds predetermined time, the processing judged as exceeding the predetermined time and controls the data written in the WC 21 to be saved in the FSBB 12ac.
摘要翻译： 存储器系统包括从其读出数据并由主机设备以扇区单元写入数据的WC 21，读出数据并以页为单位写入数据的FS12，MS11从MS 读出哪个数据，以轨道单位写入哪个数据，用作FS12的输入缓冲器的FSIB 12a和用作MS 11的输入缓冲器的MSIB 11a。具有等于 或大于WC 21的存储容量并且存储写入WC 21的数据被提供在FSIB12a中。 管理各个存储单元的数据管理单元120当判定存储单元之间执行的一种处理超过预定时间时，判断为超过预定时间的处理，并且将写入WC 21中的数据控制为 保存在FSBB 12ac中。
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公开(公告)号：US20100146228A1
公开(公告)日：2010-06-10
申请号：US12705431
申请日：2010-02-12
申请人： Shinichi Kanno , Hirokuni Yano , Toshikatsu Hida , Kazuya Kitsunai , Junji Yano
发明人： Shinichi Kanno , Hirokuni Yano , Toshikatsu Hida , Kazuya Kitsunai , Junji Yano
CPC分类号： G11C16/349 , G06F11/1068 , G06F12/0246 , G06F2212/7211 , G11C16/16 , G11C29/76
摘要： A memory system includes a nonvolatile memory including blocks as data erase units, a measuring unit which measures an erase time at which data in each block is erased, a block controller having a block table which associates a state value indicating one of a free state and a used state with the erase time for each block, a detector which detects blocks in which rewrite has collectively occurred within a short period, a first selector which selects a free block having an old erase time as a first block, a second selector which selects a block in use having an old erase time as a second block, and a leveling unit which moves data in the second block to the first block if the first block is included in the blocks detected by the detector.
摘要翻译： 一种存储器系统，包括：包括作为数据擦除单元的块的非易失性存储器，测量擦除每个块中的数据的擦除时间的测量单元;具有块表的块控制器，其将指示空闲状态之一的状态值和 具有每个块的擦除时间的使用状态，检测在短时间内共同发生重写的块的检测器，选择具有旧擦除时间的空闲块作为第一块的第一选择器，选择 如果第一块被包括在由检测器检测到的块中，则将具有旧擦除时间的块用作第二块;以及调平单元，其将第二块中的数据移动到第一块。
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