公开(公告)号：US08440524B2

公开(公告)日：2013-05-14

申请号：US13030790

申请日：2011-02-18

申请人： Hirokazu Fujiwara ,  Masaki Konishi ,  Jun Kawai ,  Takeo Yamamoto ,  Takeshi Endo ,  Takashi Katsuno ,  Yukihiko Watanabe ,  Narumasa Soejima

发明人： Hirokazu Fujiwara ,  Masaki Konishi ,  Jun Kawai ,  Takeo Yamamoto ,  Takeshi Endo ,  Takashi Katsuno ,  Yukihiko Watanabe ,  Narumasa Soejima

IPC分类号： H01L21/00

CPC分类号： H01L29/7811 ,  C21D1/09 ,  C22F1/10 ,  H01L21/0485 ,  H01L21/0495 ,  H01L21/268 ,  H01L21/324 ,  H01L21/67115 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/45 ,  H01L29/47 ,  H01L29/6606 ,  H01L29/66068 ,  H01L29/7813 ,  H01L29/872

摘要： A method for manufacturing a semiconductor device including a semiconductor substrate composed of silicon carbide, an upper surface electrode which contacts an upper surface of the substrate, and a lower surface electrode which contacts a lower surface of the substrate, the method including steps of: (a) forming an upper surface structure on the upper surface side of the substrate, and (b) forming a lower surface structure on the lower surface side of the substrate. The step (a) comprises steps of: (a1) depositing an upper surface electrode material layer on the upper surface of the substrate, the upper surface electrode material layer being a raw material layer of the upper surface electrode, and (a2) annealing the upper surface electrode material layer. The step (b) comprises steps of: (b1) depositing a lower surface electrode material layer on the lower surface of the substrate, the lower surface electrode material layer being a raw material layer of the lower surface electrode, and (b2) annealing the lower surface electrode material layer with a laser to make an ohmic contact between the lower surface electrode and the substrate.

摘要翻译： 一种半导体器件的制造方法，该半导体器件包括由碳化硅构成的半导体衬底，与衬底的上表面接触的上表面电极和与衬底的下表面接触的下表面电极，该方法包括以下步骤：（ a）在基板的上表面侧上形成上表面结构，（b）在基板的下表面侧形成下表面结构。 步骤（a）包括以下步骤：（a1）在基板的上表面上沉积上表面电极材料层，上表面电极材料层是上表面电极的原料层，（a2）使 上表面电极材料层。 步骤（b）包括以下步骤：（b1）在基板的下表面上沉积下表面电极材料层，下表面电极材料层是下表面电极的原料层，（b2）使 下表面电极材料层用激光器在下表面电极和衬底之间形成欧姆接触。

公开(公告)号：US08748975B2

公开(公告)日：2014-06-10

申请号：US13712343

申请日：2012-12-12

申请人： Hirokazu Fujiwara ,  Yukihiko Watanabe ,  Narumasa Soejima ,  Toshimasa Yamamoto ,  Yuichi Takeuchi

发明人： Hirokazu Fujiwara ,  Yukihiko Watanabe ,  Narumasa Soejima ,  Toshimasa Yamamoto ,  Yuichi Takeuchi

IPC分类号： H01L29/66 ,  H01L21/336

CPC分类号： H01L29/66666 ,  H01L21/26506 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/167 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/66068 ,  H01L29/7397 ,  H01L29/7813 ,  H01L29/7827

摘要： A switching element is provided having a semiconductor substrate. A trench gate electrode is formed in the upper surface of the semiconductor substrate. An n-type first semiconductor region, a p-type second semiconductor region, and an n-type third semiconductor region are formed in a region in contact with a gate insulating film in the semiconductor substrate. At a position below the second semiconductor region, there is formed a p-type fourth semiconductor region connected to the second semiconductor region and opposing the gate insulating film via the third semiconductor region and containing boron. A high-concentration-carbon containing region having a carbon concentration higher than that of a semiconductor region exposed on the lower surface of the semiconductor substrate is formed in at least a part of the portion of the third semiconductor region, positioned between the fourth semiconductor region and the gate insulating film, that is in contact with the fourth semiconductor region.

摘要翻译： 提供了具有半导体衬底的开关元件。 沟槽栅电极形成在半导体衬底的上表面中。 在与半导体衬底中的栅极绝缘膜接触的区域中形成n型第一半导体区域，p型第二半导体区域和n型第三半导体区域。 在第二半导体区域下方的位置处，形成连接到第二半导体区域的p型第四半导体区域，并且经由第三半导体区域与栅极绝缘膜相对并且含有硼。 在第三半导体区域的至少一部分中，形成具有比在半导体衬底的下表面露出的半导体区域更高的碳浓度的高浓度含碳区域，位于第四半导体区域 以及与第四半导体区域接触的栅极绝缘膜。

公开(公告)号：US09136372B2

公开(公告)日：2015-09-15

申请号：US13531793

申请日：2012-06-25

申请人： Shinichiro Miyahara ,  Masahiro Sugimoto ,  Hidefumi Takaya ,  Yukihiko Watanabe ,  Narumasa Soejima ,  Tsuyoshi Ishikawa

发明人： Shinichiro Miyahara ,  Masahiro Sugimoto ,  Hidefumi Takaya ,  Yukihiko Watanabe ,  Narumasa Soejima ,  Tsuyoshi Ishikawa

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L29/04 ,  H01L29/08 ,  H01L29/10 ,  H01L29/16

CPC分类号： H01L29/7813 ,  H01L29/045 ,  H01L29/0865 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/4236 ,  H01L29/66068 ,  H01L29/7825 ,  H01L29/7827

摘要： In a silicon carbide semiconductor device, a plurality of trenches has a longitudinal direction in one direction and is arranged in a stripe pattern. Each of the trenches has first and second sidewalls extending in the longitudinal direction. The first sidewall is at a first acute angle to one of a (11-20) plane and a (1-100) plane, the second sidewall is at a second acute angle to the one of the (11-20) plane and the (1-100) plane, and the first acute angle is smaller than the second acute angle. A first conductivity type region is in contact with only the first sidewall in the first and second sidewalls of each of the trenches, and a current path is formed on only the first sidewall in the first and second sidewalls.

摘要翻译： 在碳化硅半导体器件中，多个沟槽在一个方向上具有纵向方向并且被布置成条纹图案。 每个沟槽具有在纵向方向上延伸的第一和第二侧壁。 第一侧壁与（11-20）面和（1-100）面中的一个成锐角，第二侧壁与（11-20）面和 （1-100）平面，第一锐角小于第二锐角。 第一导电类型区域仅与每个沟槽的第一和第二侧壁中的第一侧壁接触，并且仅在第一和第二侧壁中的第一侧壁上形成电流路径。

公开(公告)号：US20140252465A1

公开(公告)日：2014-09-11

申请号：US14352142

申请日：2012-10-17

申请人： Hidefumi Takaya ,  Hideo Matsuki ,  Naohiro Suzuki ,  Tsuyoshi Ishikawa ,  Narumasa Soejima ,  Yukihiko Watanabe

发明人： Hidefumi Takaya ,  Hideo Matsuki ,  Naohiro Suzuki ,  Tsuyoshi Ishikawa ,  Narumasa Soejima ,  Yukihiko Watanabe

IPC分类号： H01L29/423 ,  H01L29/66 ,  H01L21/28 ,  H01L29/78

CPC分类号： H01L29/4236 ,  H01L21/047 ,  H01L21/28008 ,  H01L21/823487 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/1608 ,  H01L29/41741 ,  H01L29/42368 ,  H01L29/66068 ,  H01L29/66666 ,  H01L29/7806 ,  H01L29/7813 ,  H01L29/7827

摘要： A semiconductor device has a semiconductor substrate including a body region, a drift region, a trench that extends from a surface of the semiconductor substrate into the drift region through the body region, and a source region located adjacent to the trench in a range exposed to the surface of the semiconductor substrate, the source region being isolated from the drift region by the body region. A specific layer is disposed on a bottom of the trench, and it has a characteristic of forming a depletion layer at a junction between the specific layer and the drift region. An insulating layer covers an upper surface of the specific layer and a sidewall of the trench. A conductive portion is formed on a part of the side wall of the trench. The conductive portion is joined to the specific layer, and reaches the surface of the semiconductor substrate.

摘要翻译： 半导体器件具有半导体衬底，其包括体区，漂移区，从半导体衬底的表面延伸通过体区的漂移区的沟槽，以及与暴露于 半导体衬底的表面，源区域通过身体区域与漂移区隔离。 特定层设置在沟槽的底部，并且具有在特定层和漂移区之间的结处形成耗尽层的特征。 绝缘层覆盖特定层的上表面和沟槽的侧壁。 导电部分形成在沟槽的侧壁的一部分上。 导电部分连接到特定层，并到达半导体衬底的表面。

公开(公告)号：US20140175459A1

公开(公告)日：2014-06-26

申请号：US13994855

申请日：2012-02-06

申请人： Kensaku Yamamoto ,  Masato Noborio ,  Hideo Matsuki ,  Hidefumi Takaya ,  Masahiro Sugimoto ,  Narumasa Soejima ,  Tsuyoshi Ishikawa ,  Yukihiko Watanabe

发明人： Kensaku Yamamoto ,  Masato Noborio ,  Hideo Matsuki ,  Hidefumi Takaya ,  Masahiro Sugimoto ,  Narumasa Soejima ,  Tsuyoshi Ishikawa ,  Yukihiko Watanabe

IPC分类号： H01L29/78 ,  H01L29/16 ,  H01L29/66

CPC分类号： H01L29/7813 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/66348 ,  H01L29/7397

摘要： A SiC semiconductor device includes: a semiconductor switching element having: a substrate, a drift layer and a base region stacked in this order; a source region and a contact region in the base region; a trench extending from a surface of the source region to penetrate the base region; a gate electrode on a gate insulating film in the trench; a source electrode electrically coupled with the source region and the base region; a drain electrode on a back side of the substrate; and multiple deep layers in an upper portion of the drift layer deeper than the trench. Each deep layer has upper and lower portions. A width of the upper portion is smaller than the lower portion.

摘要翻译： SiC半导体器件包括：半导体开关元件，其具有：依次层叠的基板，漂移层和基极区域; 源极区域和基极区域中的接触区域; 从源极区域的表面延伸以穿透基部区域的沟槽; 沟槽中的栅极绝缘膜上的栅电极; 源极，与源极区域和基极区域电耦合; 位于所述基板的背面的漏电极; 以及在漂移层的上部比沟槽更深的多个深层。 每个深层具有上部和下部。 上部的宽度小于下部。

公开(公告)号：US09142411B2

公开(公告)日：2015-09-22

申请号：US14090424

申请日：2013-11-26

申请人： Masatoshi Tsujimura ,  Hirokazu Fujiwara ,  Tomoo Morino ,  Narumasa Soejima

发明人： Masatoshi Tsujimura ,  Hirokazu Fujiwara ,  Tomoo Morino ,  Narumasa Soejima

IPC分类号： H01L21/00 ,  H01L21/04 ,  H01L21/673 ,  H01L29/16

CPC分类号： H01L21/046 ,  H01L21/67303 ,  H01L29/1608

摘要： A method for producing a semiconductor device includes: an arranging process of arranging a plurality of silicon carbide wafers having opposed first and surfaces so that the first surface and the second surface of adjacent silicon carbide wafers face each other and are separated in parallel; and a heat treatment process of heating the arranged plurality of silicon carbide wafers so that the first surface of each silicon carbide wafer becomes higher in temperature than the second surface thereof, and, in the adjacent silicon carbide wafers, the second surface of one silicon carbide wafer becomes higher in temperature than the first surface of the other silicon carbide wafer that faces the second surface.

摘要翻译： 一种半导体器件的制造方法，其特征在于，包括：配置多个具有相对的第一面和表面的碳化硅晶片的布置处理，使得相邻碳化硅晶片的第一表面和第二表面彼此面对并且彼此平行分离; 以及加热配置的多个碳化硅晶片的热处理工序，使得碳化硅晶片的第一表面的温度比其第二表面变高，并且在相邻的碳化硅晶片中，一个碳化硅的第二表面 晶片的温度比面向第二表面的另一个碳化硅晶片的第一表面变得更高。

公开(公告)号：US08710586B2

公开(公告)日：2014-04-29

申请号：US13229892

申请日：2011-09-12

申请人： Toshimasa Yamamoto ,  Masahiro Sugimoto ,  Hidefumi Takaya ,  Jun Morimoto ,  Narumasa Soejima ,  Tsuyoshi Ishikawa ,  Yukihiko Watanabe

发明人： Toshimasa Yamamoto ,  Masahiro Sugimoto ,  Hidefumi Takaya ,  Jun Morimoto ,  Narumasa Soejima ,  Tsuyoshi Ishikawa ,  Yukihiko Watanabe

IPC分类号： H01L29/66 ,  H01L29/15

CPC分类号： H01L29/7813 ,  H01L29/086 ,  H01L29/1608 ,  H01L29/41766 ,  H01L29/45 ,  H01L29/66068

摘要： A SiC semiconductor device includes: a substrate, a drift layer, and a base region stacked in this order; first and second source regions and a contact layer in the base region; a trench penetrating the source and base regions; a gate electrode in the trench; an interlayer insulation film with a contact hole covering the gate electrode; a source electrode coupling with the source region and the contact layer via the contact hole; a drain electrode on the substrate; and a metal silicide film. The high concentration second source region is shallower than the low concentration first source region, and has a part covered with the interlayer insulation film, which includes a low concentration first portion near a surface and a high concentration second portion deeper than the first portion. The metal silicide film on the second part has a thickness larger than the first portion.

摘要翻译： SiC半导体器件包括：依次堆叠的衬底，漂移层和基极区域; 第一和第二源极区域和基极区域中的接触层; 穿透源区和基区的沟槽; 沟槽中的栅电极; 具有覆盖所述栅电极的接触孔的层间绝缘膜; 源极通过接触孔与源极区域和接触层耦合; 衬底上的漏电极; 和金属硅化物膜。 高浓度第二源区比低浓度第一源区浅，并且具有被层间绝缘膜覆盖的部分，其包括表面附近的低浓度第一部分和比第一部分更深的高浓度第二部分。 第二部分上的金属硅化物膜的厚度大于第一部分。

公开(公告)号：US08518809B2

公开(公告)日：2013-08-27

申请号：US13308721

申请日：2011-12-01

申请人： Hiroki Watanabe ,  Yasuo Kitou ,  Yasushi Furukawa ,  Kensaku Yamamoto ,  Hidefumi Takaya ,  Masahiro Sugimoto ,  Yukihiko Watanabe ,  Narumasa Soejima ,  Tsuyoshi Ishikawa

发明人： Hiroki Watanabe ,  Yasuo Kitou ,  Yasushi Furukawa ,  Kensaku Yamamoto ,  Hidefumi Takaya ,  Masahiro Sugimoto ,  Yukihiko Watanabe ,  Narumasa Soejima ,  Tsuyoshi Ishikawa

IPC分类号： H01L21/20

CPC分类号： H01L21/0262 ,  C30B25/186 ,  C30B29/36 ,  H01L21/02378 ,  H01L21/0243 ,  H01L21/02529 ,  H01L21/02658 ,  H01L21/046 ,  H01L21/0475 ,  H01L29/04

摘要： A manufacturing method of an SiC single crystal includes preparing an SiC substrate, implanting ions into a surface portion of the SiC substrate to form an ion implantation layer, activating the ions implanted into the surface portion of the SiC substrate by annealing, chemically etching the surface portion of the SiC substrate to form an etch pit that is caused by a threading screw dislocation included in the SiC substrate and performing an epitaxial growth of SiC to form an SiC growth layer on a surface of the SiC substrate including an inner wall of the etch pit in such a manner that portions of the SiC growth layer grown on the inner wall of the etch pit join with each other.

摘要翻译： SiC单晶的制造方法包括制备SiC衬底，将离子注入到SiC衬底的表面部分中以形成离子注入层，通过退火激活注入到SiC衬底的表面部分中的离子，化学蚀刻表面 以形成由SiC衬底中的螺纹位错引起的蚀刻坑，并且在SiC衬底的表面上进行SiC的外延生长以形成SiC生长层，所述SiC生长层包括蚀刻的内壁 以使得在蚀刻坑的内壁上生长的SiC生长层的部分彼此连接的方式形成凹坑。

公开(公告)号：US20130001592A1

公开(公告)日：2013-01-03

申请号：US13531793

申请日：2012-06-25

申请人： Shinichiro Miyahara ,  Masahiro Sugimoto ,  Hidefumi Takaya ,  Yukihiko Watanabe ,  Narumasa Soejima ,  Tsuyoshi Ishikawa

发明人： Shinichiro Miyahara ,  Masahiro Sugimoto ,  Hidefumi Takaya ,  Yukihiko Watanabe ,  Narumasa Soejima ,  Tsuyoshi Ishikawa

IPC分类号： H01L29/161

CPC分类号： H01L29/7813 ,  H01L29/045 ,  H01L29/0865 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/4236 ,  H01L29/66068 ,  H01L29/7825 ,  H01L29/7827

摘要： In a silicon carbide semiconductor device, a plurality of trenches has a longitudinal direction in one direction and is arranged in a stripe pattern. Each of the trenches has first and second sidewalls extending in the longitudinal direction. The first sidewall is at a first acute angle to one of a (11-20) plane and a (1-100) plane, the second sidewall is at a second acute angle to the one of the (11-20) plane and the (1-100) plane, and the first acute angle is smaller than the second acute angle. A first conductivity type region is in contact with only the first sidewall in the first and second sidewalls of each of the trenches, and a current path is formed on only the first sidewall in the first and second sidewalls.

摘要翻译： 在碳化硅半导体器件中，多个沟槽在一个方向上具有纵向方向并且被布置成条纹图案。 每个沟槽具有在纵向方向上延伸的第一和第二侧壁。 第一侧壁与（11-20）面和（1-100）面中的一个成锐角，第二侧壁与（11-20）面和 （1-100）平面，第一锐角小于第二锐角。 第一导电类型区域仅与每个沟槽的第一和第二侧壁中的第一侧壁接触，并且仅在第一和第二侧壁中的第一侧壁上形成电流通路。

公开(公告)号：US20120319136A1

公开(公告)日：2012-12-20

申请号：US13581497

申请日：2012-02-06

申请人： Masato Noborio ,  Kensaku Yamamoto ,  Hideo Matsuki ,  Hidefumi Takaya ,  Masahiro Sugimoto ,  Narumasa Soejima ,  Tsuyoshi Ishikawa ,  Yukihiko Watanabe

发明人： Masato Noborio ,  Kensaku Yamamoto ,  Hideo Matsuki ,  Hidefumi Takaya ,  Masahiro Sugimoto ,  Narumasa Soejima ,  Tsuyoshi Ishikawa ,  Yukihiko Watanabe

IPC分类号： H01L29/24 ,  H01L21/336

CPC分类号： H01L29/7813 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/66348 ,  H01L29/7397

摘要： A SiC device includes an inversion type MOSFET having: a substrate, a drift layer, and a base region stacked in this order; source and contact regions in upper portions of the base region; a trench penetrating the source and base regions; a gate electrode on a gate insulating film in the trench; a source electrode coupled with the source and base region; a drain electrode on a back of the substrate; and multiple deep layers in an upper portion of the drift layer deeper than the trench. Each deep layer has an impurity concentration distribution in a depth direction, and an inversion layer is provided in a portion of the deep layer on the side of the trench under application of the gate voltage.

摘要翻译： SiC器件包括反转型MOSFET，其具有：依次堆叠的衬底，漂移层和基极区域; 源极和接触区域在基极区域的上部; 穿透源区和基区的沟槽; 沟槽中的栅极绝缘膜上的栅电极; 源极与源极和基极区域耦合; 位于衬底背面的漏电极; 以及在漂移层的上部比沟槽更深的多个深层。 每个深层在深度方向上具有杂质浓度分布，并且在施加栅极电压下在沟槽侧的深层的一部分中设置反转层。