公开(公告)号：US20090224353A1

公开(公告)日：2009-09-10

申请号：US12382012

申请日：2009-03-05

申请人： Takeo Yamamoto ,  Takeshi Endo ,  Yukihiko Watanabe ,  Takashi Katsuno ,  Masayasu Ishiko ,  Hirokazu Fujiwara ,  Masaki Konishi

发明人： Takeo Yamamoto ,  Takeshi Endo ,  Yukihiko Watanabe ,  Takashi Katsuno ,  Masayasu Ishiko ,  Hirokazu Fujiwara ,  Masaki Konishi

IPC分类号： H01L29/872

CPC分类号： H01L29/872 ,  H01L27/0814 ,  H01L29/0649 ,  H01L29/417 ,  H01L29/861

摘要： A diode includes the following: an n type semiconductor region; a p type semiconductor region provided in a part of a front face of the n type semiconductor region; an anode electrode (front face electrode) which adjoins a front face of the n type semiconductor region and a front face of the p type semiconductor region while at least forming a Schottky junction on a front face of the n type semiconductor region; and an insulating region which has a right-hand side (first side) and a left-hand side (second side) adjacent to the n type semiconductor region, the right-hand side facing a second n type semiconductor region which is located below the Schottky junction, the left-hand side facing a first n type semiconductor region which is located below a pn junction between the n type semiconductor region and the p type semiconductor region.

摘要翻译： 二极管包括：n型半导体区域; 设置在n型半导体区域的正面的一部分中的p型半导体区域; 邻接n型半导体区域的前表面和p型半导体区域的正面的阳极电极（正面电极），同时至少在n型半导体区域的正面上形成肖特基结; 以及具有与n型半导体区域相邻的右侧（第一侧）和左侧（第二侧）的绝缘区域，所述右侧面向位于所述n型半导体区域下方的第二n型半导体区域 肖特基结，左手侧面对位于n型半导体区域和p型半导体区域之间的pn结的下方的第一n型半导体区域。

公开(公告)号：US20090230405A1

公开(公告)日：2009-09-17

申请号：US12382369

申请日：2009-03-13

申请人： Takeo Yamamoto ,  Takeshi Endo ,  Masaki Konishi ,  Hirokazu Fujiwara ,  Yukihiko Watanabe ,  Takashi Katsuno ,  Masayasu Ishiko

发明人： Takeo Yamamoto ,  Takeshi Endo ,  Masaki Konishi ,  Hirokazu Fujiwara ,  Yukihiko Watanabe ,  Takashi Katsuno ,  Masayasu Ishiko

IPC分类号： H01L29/24 ,  H01L21/04

CPC分类号： H01L29/872 ,  H01L29/0619 ,  H01L29/66136 ,  H01L29/66143 ,  H01L29/861

摘要： A manufacturing method of a diode includes: forming a P type semiconductor film on a N type semiconductor layer with a crystal growth method; forming a first metallic film on the P type semiconductor film so that the first metallic film contacts the P type semiconductor film with an ohmic contact; forming a mask having an opening on the first metallic film; etching a part of the first metallic film and a part of the P type semiconductor film via the opening so that a part of the N type semiconductor layer is exposed; and forming a second metallic film on the part of the N type semiconductor layer so that the second metallic film contacts the N type semiconductor layer with a Schottky contact.

摘要翻译： 二极管的制造方法包括：在晶体生长方法的N型半导体层上形成P型半导体膜; 在P型半导体膜上形成第一金属膜，使得第一金属膜与欧姆接触的P型半导体膜接触; 在所述第一金属膜上形成具有开口的掩模; 经由所述开口蚀刻所述第一金属膜的一部分和所述P型半导体膜的一部分，使得所述N型半导体层的一部分露出; 并且在N型半导体层的一部分上形成第二金属膜，使得第二金属膜以肖特基接触接触N型半导体层。

公开(公告)号：US08440524B2

公开(公告)日：2013-05-14

申请号：US13030790

申请日：2011-02-18

申请人： Hirokazu Fujiwara ,  Masaki Konishi ,  Jun Kawai ,  Takeo Yamamoto ,  Takeshi Endo ,  Takashi Katsuno ,  Yukihiko Watanabe ,  Narumasa Soejima

发明人： Hirokazu Fujiwara ,  Masaki Konishi ,  Jun Kawai ,  Takeo Yamamoto ,  Takeshi Endo ,  Takashi Katsuno ,  Yukihiko Watanabe ,  Narumasa Soejima

IPC分类号： H01L21/00

CPC分类号： H01L29/7811 ,  C21D1/09 ,  C22F1/10 ,  H01L21/0485 ,  H01L21/0495 ,  H01L21/268 ,  H01L21/324 ,  H01L21/67115 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/45 ,  H01L29/47 ,  H01L29/6606 ,  H01L29/66068 ,  H01L29/7813 ,  H01L29/872

摘要： A method for manufacturing a semiconductor device including a semiconductor substrate composed of silicon carbide, an upper surface electrode which contacts an upper surface of the substrate, and a lower surface electrode which contacts a lower surface of the substrate, the method including steps of: (a) forming an upper surface structure on the upper surface side of the substrate, and (b) forming a lower surface structure on the lower surface side of the substrate. The step (a) comprises steps of: (a1) depositing an upper surface electrode material layer on the upper surface of the substrate, the upper surface electrode material layer being a raw material layer of the upper surface electrode, and (a2) annealing the upper surface electrode material layer. The step (b) comprises steps of: (b1) depositing a lower surface electrode material layer on the lower surface of the substrate, the lower surface electrode material layer being a raw material layer of the lower surface electrode, and (b2) annealing the lower surface electrode material layer with a laser to make an ohmic contact between the lower surface electrode and the substrate.

摘要翻译： 一种半导体器件的制造方法，该半导体器件包括由碳化硅构成的半导体衬底，与衬底的上表面接触的上表面电极和与衬底的下表面接触的下表面电极，该方法包括以下步骤：（ a）在基板的上表面侧上形成上表面结构，（b）在基板的下表面侧形成下表面结构。 步骤（a）包括以下步骤：（a1）在基板的上表面上沉积上表面电极材料层，上表面电极材料层是上表面电极的原料层，（a2）使 上表面电极材料层。 步骤（b）包括以下步骤：（b1）在基板的下表面上沉积下表面电极材料层，下表面电极材料层是下表面电极的原料层，（b2）使 下表面电极材料层用激光器在下表面电极和衬底之间形成欧姆接触。

公开(公告)号：US08324704B2

公开(公告)日：2012-12-04

申请号：US12659853

申请日：2010-03-23

申请人： Takeo Yamamoto ,  Takeshi Endo ,  Eiichi Okuno ,  Hirokazu Fujiwara ,  Masaki Konishi ,  Takashi Katsuno ,  Yukihiko Watanabe

发明人： Takeo Yamamoto ,  Takeshi Endo ,  Eiichi Okuno ,  Hirokazu Fujiwara ,  Masaki Konishi ,  Takashi Katsuno ,  Yukihiko Watanabe

IPC分类号： H01L29/24 ,  H01L29/47 ,  H01L21/04

CPC分类号： H01L29/47 ,  H01L21/0465 ,  H01L21/0495 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/1608 ,  H01L29/6606 ,  H01L29/66143 ,  H01L29/872

摘要： A silicon carbide semiconductor device with a Schottky barrier diode includes a first conductivity type silicon carbide substrate, a first conductivity type silicon carbide drift layer on a first surface of the substrate, a Schottky electrode forming a Schottky contact with the drift layer, and an ohmic electrode on a second surface of the substrate. The Schottky electrode includes an oxide layer in direct contact with the drift layer. The oxide layer is made of an oxide of molybdenum, titanium, nickel, or an alloy of at least two of these elements.

摘要翻译： 具有肖特基势垒二极管的碳化硅半导体器件包括第一导电型碳化硅衬底，在衬底的第一表面上的第一导电型碳化硅漂移层，与漂移层形成肖特基接触的肖特基电极和欧姆 电极在基板的第二表面上。 肖特基电极包括与漂移层直接接触的氧化物层。 氧化物层由钼，钛，镍或这些元素中的至少两种的合金的氧化物制成。

公开(公告)号：US08168485B2

公开(公告)日：2012-05-01

申请号：US12461205

申请日：2009-08-04

申请人： Takeshi Endo ,  Eiichi Okuno ,  Takeo Yamamoto ,  Hirokazu Fujiwara ,  Masaki Konishi ,  Yukihiko Watanabe ,  Takashi Katsuno

发明人： Takeshi Endo ,  Eiichi Okuno ,  Takeo Yamamoto ,  Hirokazu Fujiwara ,  Masaki Konishi ,  Yukihiko Watanabe ,  Takashi Katsuno

IPC分类号： H01L29/812 ,  H01L21/338

CPC分类号： H01L29/872 ,  H01L29/456 ,  H01L29/47 ,  H01L29/66136 ,  H01L29/66143 ,  H01L29/861

摘要： A method of making a semiconductor device includes forming a p-type semiconductor region to an n-type semiconductor substrate in such a manner that the p-type semiconductor region is partially exposed to a top surface of the semiconductor substrate, forming a Schottky electrode of a first material in such a manner that the Schottky electrode is in Schottky contact with an n-type semiconductor region exposed to the top surface of the semiconductor substrate, and forming an ohmic electrode of a second material different from the first material in such a manner that the ohmic electrode is in ohmic contact with the exposed p-type semiconductor region. The Schottky electrode is formed earlier than the ohmic electrode.

摘要翻译： 制造半导体器件的方法包括：以p型半导体区域部分地暴露于半导体衬底的顶表面，形成p型半导体区域到n型半导体衬底，形成肖特基电极 以使肖特基电极与暴露于半导体衬底的顶表面的n型半导体区域肖特基接触的方式形成第一材料，并且以这种方式形成不同于第一材料的第二材料的欧姆电极 欧姆电极与暴露的p型半导体区域欧姆接触。 肖特基电极比欧姆电极早。

公开(公告)号：US20100032730A1

公开(公告)日：2010-02-11

申请号：US12461205

申请日：2009-08-04

申请人： Takeshi Endo ,  Eiichi Okuno ,  Takeo Yamamoto ,  Hirokazu Fujiwara ,  Masaki Konishi ,  Yukihiko Watanabe ,  Takashi Katsuno

发明人： Takeshi Endo ,  Eiichi Okuno ,  Takeo Yamamoto ,  Hirokazu Fujiwara ,  Masaki Konishi ,  Yukihiko Watanabe ,  Takashi Katsuno

IPC分类号： H01L29/812 ,  H01L21/338

CPC分类号： H01L29/872 ,  H01L29/456 ,  H01L29/47 ,  H01L29/66136 ,  H01L29/66143 ,  H01L29/861

摘要： A method of making a semiconductor device includes forming a p-type semiconductor region to an n-type semiconductor substrate in such a manner that the p-type semiconductor region is partially exposed to a top surface of the semiconductor substrate, forming a Schottky electrode of a first material in such a manner that the Schottky electrode is in Schottky contact with an n-type semiconductor region exposed to the top surface of the semiconductor substrate, and forming an ohmic electrode of a second material different from the first material in such a manner that the ohmic electrode is in ohmic contact with the exposed p-type semiconductor region. The Schottky electrode is formed earlier than the ohmic electrode.

摘要翻译： 制造半导体器件的方法包括：以p型半导体区域部分地暴露于半导体衬底的顶表面，形成p型半导体区域到n型半导体衬底，形成肖特基电极 以使肖特基电极与暴露于半导体衬底的顶表面的n型半导体区域肖特基接触的方式形成第一材料，并且以这种方式形成不同于第一材料的第二材料的欧姆电极 欧姆电极与暴露的p型半导体区域欧姆接触。 肖特基电极比欧姆电极早。

公开(公告)号：US08163637B2

公开(公告)日：2012-04-24

申请号：US12975832

申请日：2010-12-22

申请人： Masaki Konishi ,  Hirokazu Fujiwara ,  Takeshi Endo ,  Takeo Yamamoto ,  Takashi Katsuno ,  Yukihiko Watanabe

发明人： Masaki Konishi ,  Hirokazu Fujiwara ,  Takeshi Endo ,  Takeo Yamamoto ,  Takashi Katsuno ,  Yukihiko Watanabe

IPC分类号： H01L21/425

CPC分类号： H01L21/0465 ,  H01L29/1608 ,  H01L29/6606 ,  H01L29/872

摘要： First, a first layer made of Ni or an alloy including Ni may be formed on an upper surface of a semiconductor layer. Next, a second layer made of silicon oxide may be formed on an upper surface of the first layer. Next, a part, which corresponds to a semiconductor region, of the second layer may be removed. Next, second conductive type ion impurities may be injected from upper sides of the first and second layers to the semiconductor layer after the removing step.

摘要翻译： 首先，可以在半导体层的上表面上形成由Ni构成的第一层或包含Ni的合金。 接下来，可以在第一层的上表面上形成由氧化硅制成的第二层。 接下来，可以去除对应于第二层的半导体区域的部分。 接下来，可以在去除步骤之后，将第二导电型离子杂质从第一层和第二层的上侧注入半导体层。

公开(公告)号：US20100244049A1

公开(公告)日：2010-09-30

申请号：US12659853

申请日：2010-03-23

申请人： Takeo Yamamoto ,  Takeshi Endo ,  Eiichi Okuno ,  Hirokazu Fujiwara ,  Masaki Konishi ,  Takashi Katsuno ,  Yukihiko Watanabe

发明人： Takeo Yamamoto ,  Takeshi Endo ,  Eiichi Okuno ,  Hirokazu Fujiwara ,  Masaki Konishi ,  Takashi Katsuno ,  Yukihiko Watanabe

IPC分类号： H01L29/47 ,  H01L29/24 ,  H01L21/04

CPC分类号： H01L29/47 ,  H01L21/0465 ,  H01L21/0495 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/1608 ,  H01L29/6606 ,  H01L29/66143 ,  H01L29/872

摘要： A silicon carbide semiconductor device with a Schottky barrier diode includes a first conductivity type silicon carbide substrate, a first conductivity type silicon carbide drift layer on a first surface of the substrate, a Schottky electrode forming a Schottky contact with the drift layer, and an ohmic electrode on a second surface of the substrate. The Schottky electrode includes an oxide layer in direct contact with the drift layer. The oxide layer is made of an oxide of molybdenum, titanium, nickel, or an alloy of at least two of these elements.

摘要翻译： 具有肖特基势垒二极管的碳化硅半导体器件包括第一导电型碳化硅衬底，在衬底的第一表面上的第一导电型碳化硅漂移层，与漂移层形成肖特基接触的肖特基电极和欧姆 电极在基板的第二表面上。 肖特基电极包括与漂移层直接接触的氧化物层。 氧化物层由钼，钛，镍或这些元素中的至少两种的合金的氧化物制成。

公开(公告)号：US20090269908A1

公开(公告)日：2009-10-29

申请号：US12385782

申请日：2009-04-20

申请人： Hirokazu Fujiwara ,  Masaki Konishi ,  Takeo Yamamoto ,  Eiichi Okuno ,  Yukihiko Watanabe ,  Takashi Katsuno

发明人： Hirokazu Fujiwara ,  Masaki Konishi ,  Takeo Yamamoto ,  Eiichi Okuno ,  Yukihiko Watanabe ,  Takashi Katsuno

IPC分类号： H01L21/04

CPC分类号： H01L29/47 ,  H01L21/046 ,  H01L29/1608 ,  H01L29/66143 ,  H01L29/872

摘要： A manufacturing method of a semiconductor device comprises a process of doping conductive impurities in a silicon carbide substrate, a process of forming a cap layer on a surface of the silicon carbide substrate, a process of activating the conductive impurities doped in the silicon carbide substrate, a process of oxidizing the cap layer after a first annealing process, and a process of removing the oxidized cap layer. It is preferred that the cap layer is formed from material that includes metal carbide. Since the oxidation onset temperature of metal carbide is comparatively low, the oxidization of the cap layer becomes easy if metal carbide is included in the cap layer. Specifically, it is preferred that the cap layer is formed from metal carbide that has an oxidation onset temperature of 1000 degrees Celsius or below, such as tantalum carbide.

摘要翻译： 半导体器件的制造方法包括在碳化硅衬底中掺杂导电杂质的工艺，在碳化硅衬底的表面上形成覆盖层的工艺，激活掺杂在碳化硅衬底中的导电杂质的工艺， 在第一退火工艺之后氧化盖层的工艺，以及去除氧化的盖层的工艺。 优选的是，盖层由包括金属碳化物的材料形成。 由于金属碳化物的氧化开始温度相对较低，如果在盖层中包括金属碳化物，则盖层的氧化变得容易。 具体而言，优选由碳化钽等氧化开始温度为1000℃以下的金属碳化物形成盖层。

公开(公告)号：US08470672B2

公开(公告)日：2013-06-25

申请号：US13220756

申请日：2011-08-30

申请人： Takeshi Endo ,  Shinichiro Miyahara ,  Tomoo Morino ,  Masaki Konishi ,  Hirokazu Fujiwara ,  Jun Morimoto ,  Tsuyoshi Ishikawa ,  Takashi Katsuno ,  Yukihiko Watanabe

发明人： Takeshi Endo ,  Shinichiro Miyahara ,  Tomoo Morino ,  Masaki Konishi ,  Hirokazu Fujiwara ,  Jun Morimoto ,  Tsuyoshi Ishikawa ,  Takashi Katsuno ,  Yukihiko Watanabe

IPC分类号： H01L21/336 ,  H01L21/265

CPC分类号： H01L29/7813 ,  H01L21/30604 ,  H01L21/3065 ,  H01L29/1608 ,  H01L29/4236 ,  H01L29/66068

摘要： A method of manufacturing a semiconductor device includes forming a drift layer on a substrate; forming a base layer on the drift layer; forming a trench to penetrate the base layer and to reach the drift layer; rounding off a part of a shoulder corner and a part of a bottom corner of the trench; covering an inner wall of the trench with an organic film; implanting an impurity to a surface portion of the base layer; forming a source region by activating the implanted impurity; and removing the organic film after the source region is formed, in which the substrate, the drift layer, the base layer and the source region are made of silicon carbide, and the implanting and the activating of the impurity are performed under a condition that the trench is covered with the organic film.

摘要翻译： 制造半导体器件的方法包括在衬底上形成漂移层; 在漂移层上形成基层; 形成沟槽以穿透基层并到达漂移层; 将沟槽的一部分肩部角落和底角的一部分倒圆; 用有机膜覆盖沟槽的内壁; 将杂质注入基层的表面部分; 通过激活注入的杂质形成源区; 在形成源极区域之后除去有机膜，其中基板，漂移层，基极层和源极区域由碳化硅构成，并且杂质的注入和活化在 沟槽被有机膜覆盖。