公开(公告)号：US20050086433A1

公开(公告)日：2005-04-21

申请号：US10499646

申请日：2003-10-07

Applicant: Takumi Okaue ,  Shigeo Araki ,  Junko Sasaki ,  Kenichi Nakanishi

Inventor： Takumi Okaue ,  Shigeo Araki ,  Junko Sasaki ,  Kenichi Nakanishi

IPC: G06K19/07 ,  G06F3/08 ,  G06F12/00 ,  G06F12/06 ,  G06K17/00 ,  G06K19/00 ,  G06K19/077 ,  G11C5/00

CPC classification number: G06K19/07732 ,  G06K7/0013 ,  G06K19/072 ,  G06K19/077

Abstract: This invention provides a memory card (1) that is to be used as a storage medium in a host apparatus that can record and reproduce data. The memory card has a first memory (12-1), a second memory (12-2), a first switch (13) for changing over one memory to the other, and a second switch (14) for connecting and disconnecting an insertion/removal detecting terminal INS. The first and second switches work as a slide switch (6) provided on the housing is operated. The first switch has a contact for selecting the first memory, a contact for selecting the second memory, and a contact located between these two contacts, for selecting neither memory. The second switch connects the terminal INS to the ground while the first switch remains connected to the contact for selecting the first memory or the contact for selecting the second memory. The second switch opens the terminal INS while the first switch remains connected to the contact for selecting neither memory.

Abstract translation: 本发明提供一种存储卡（1），其用作可以记录和再现数据的主机设备中的存储介质。 存储卡具有第一存储器（12-1），第二存储器（12-2），用于将一个存储器切换到另一存储器的第一开关（13）和用于连接和断开插入件的第二开关（14） /去除检测端子INS。 第一和第二开关的作用是设置在壳体上的滑动开关（6）。 第一开关具有用于选择第一存储器的触点，用于选择第二存储器的触点，以及位于这两个触点之间的触点，用于不选择存储器。 第二开关将端子INS连接到地，同时第一开关保持连接到触点用于选择第一存储器或用于选择第二存储器的触点。 第二开关打开端子INS，而第一开关保持连接到触点用于选择两个存储器。

公开(公告)号：US06944703B2

公开(公告)日：2005-09-13

申请号：US10362635

申请日：2002-06-26

Applicant: Takumi Okaue ,  Junko Sasaki

Inventor： Takumi Okaue ,  Junko Sasaki

IPC: G06F3/06 ,  G06F13/38 ,  G06F13/00

CPC classification number: G06F3/0607 ,  G06F3/0634 ,  G06F3/0656 ,  G06F3/0679 ,  G06F13/385

Abstract: An electronic device, information processing device, and adapter device enabling smooth internal circuit switching and other operations are provided. In the electronic device 200, the serial interface 21 and parallel interface 22 are connected via a data bus 23 to the register 24 and data buffer 25, and this data buffer 25 is connected to an ECC circuit 26. The register 24, data buffer 25 and ECC circuit 26 are connected to the memory 28 via a memory interface and sequencer circuit 27. The register 24 is connected to the controller 29, and data input and output is controlled. The interfaces 21 and 22 are switched by means of control signals from this controller 29. That is, switching between these interfaces 21 and 22 is performed through discrimination, by the controller 29, of a portion of the data written to the register 24.

Abstract translation: 提供了能够实现平滑的内部电路切换和其他操作的电子设备，信息处理设备和适配器设备。 在电子设备200中，串行接口21和并行接口22经由数据总线23连接到寄存器24和数据缓冲器25，并且该数据缓冲器25连接到ECC电路26。 寄存器24，数据缓冲器25和ECC电路26经由存储器接口和定序器电路27连接到存储器28。 寄存器24连接到控制器29，并且数据输入和输出被控制。 接口21和22通过来自该控制器29的控制信号来切换。 也就是说，通过控制器29对写入寄存器24的数据的一部分进行区分来执行这些接口21和22之间的切换。

公开(公告)号：US07490198B2

公开(公告)日：2009-02-10

申请号：US10499646

申请日：2003-10-07

Applicant: Takumi Okaue ,  Shigeo Araki ,  Junko Sasaki ,  Kenichi Nakanishi

Inventor： Takumi Okaue ,  Shigeo Araki ,  Junko Sasaki ,  Kenichi Nakanishi

IPC: G06F12/00

CPC classification number: G06K19/07732 ,  G06K7/0013 ,  G06K19/072 ,  G06K19/077

Abstract: This invention provides a memory card (1) that is to be used as a storage medium in a host apparatus that can record and reproduce data. The memory card has a first memory (12-1), a second memory (12-2), a first switch (13) for changing over one memory to the other, and a second switch (14) for connecting and disconnecting an insertion/removal detecting terminal INS. The first and second switches work as a slide switch (6) provided on the housing is operated. The first switch has a contact for selecting the first memory, a contact for selecting the second memory, and a contact located between these two contacts, for selecting neither memory. The second switch connects the terminal INS to the ground while the first switch remains connected to the contact for selecting the first memory or the contact for selecting the second memory. The second switch opens the terminal INS while the first switch remains connected to the contact for selecting neither memory.

Abstract translation: 本发明提供一种存储卡（1），其用作可以记录和再现数据的主机设备中的存储介质。 存储卡具有第一存储器（12-1），第二存储器（12-2），用于将一个存储器切换到另一存储器的第一开关（13）和用于连接和断开插入件的第二开关（14） /去除检测端子INS。 第一和第二开关的作用是设置在壳体上的滑动开关（6）。 第一开关具有用于选择第一存储器的触点，用于选择第二存储器的触点和位于这两个触点之间的触点，用于既不选择存储器也不选择。 第二开关将端子INS连接到地，同时第一开关保持连接到触点用于选择第一存储器或用于选择第二存储器的触点。 第二开关打开端子INS，而第一开关保持连接到触点用于选择两个存储器。

公开(公告)号：US07560461B2

公开(公告)日：2009-07-14

申请号：US11210028

申请日：2005-08-22

Applicant: Anjali Pandey ,  Robert M. Scarborough ,  Kenji Matsuno ,  Michio Ichimura ,  Yuji Nomoto ,  Shinichi Ide ,  Eiji Tsukuda ,  Junko Sasaki ,  Shoji Oda

Inventor： Anjali Pandey ,  Robert M. Scarborough ,  Kenji Matsuno ,  Michio Ichimura ,  Yuji Nomoto ,  Shinichi Ide ,  Eiji Tsukuda ,  Junko Sasaki ,  Shoji Oda

IPC: A61K31/497 ,  A61K31/535 ,  C07D413/12 ,  C07D239/94

CPC classification number: C07D239/94 ,  A61K31/517 ,  C07D401/12 ,  C07D403/12

Abstract: The present invention relates to nitrogen-containing heterocyclic compounds and pharmaceutically acceptable salts thereof which have inhibitory activity on the phosphorylation of kinases, which inhibits the activity of such kinases. The invention is also related to a method of inhibiting kinases and treating disease states in a mammal by inhibiting the phosphorylation of kinases. In a particular aspect the present invention provides nitrogen-containing heterocyclic compounds and pharmaceutically acceptable salts thereof which inhibit phosphorylation of a PDGF receptor to hinder abnormal cell growth and cell wandering, and a method for preventing or treating cell-proliferative diseases such as arteriosclerosis, vascular reobstruction, cancer and glomerulosclerosis.

Abstract translation: 本发明涉及对抑制这种激酶活性的激酶磷酸化具有抑制活性的含氮杂环化合物及其药学上可接受的盐。 本发明还涉及通过抑制激酶的磷酸化来抑制哺乳动物的激酶和治疗疾病状态的方法。 在一个特定方面，本发明提供了抑制PDGF受体的磷酸化以阻止异常细胞生长和细胞游动的含氮杂环化合物及其药学上可接受的盐，以及预防或治疗细胞增殖性疾病如动脉硬化，血管 重建，癌症和肾小球硬化症。

公开(公告)号：US07329655B2

公开(公告)日：2008-02-12

申请号：US10344625

申请日：2001-08-17

Applicant: Anjali Pandey ,  Robert M. Scarborough ,  Kenji Matsuno ,  Michio Ichimura ,  Yuji Nomoto ,  Shinichi Ide ,  Eiji Tsukuda ,  Junko Sasaki ,  Shoji Oda

Inventor： Anjali Pandey ,  Robert M. Scarborough ,  Kenji Matsuno ,  Michio Ichimura ,  Yuji Nomoto ,  Shinichi Ide ,  Eiji Tsukuda ,  Junko Sasaki ,  Shoji Oda

IPC: A61K31/54 ,  C07D417/14 ,  C07D413/14 ,  C07D43/14

CPC classification number: C07D401/12 ,  C07D239/94 ,  C07D403/12 ,  C07D405/12 ,  C07D409/12 ,  C07D417/12

Abstract: The present invention relates to nitrogen-containing heterocyclic compounds and pharmaceutically acceptable salts thereof which have inhibitory activity on the phosphorylation of kinases, which inhibits the activity of such kinases. The invention is also related to a method of inhibiting kinases and treating disease states in a mammal by inhibiting the phosphorylation of kinases. In a particular aspect the present invention provides nitrogen-containing heterocyclic compounds and pharmaceutically acceptable salts thereof which inhibit phosphorylation of a PDGF receptor to hinder abnormal cell growth and cell wandering, and a method for preventing or treating cell-proliferative diseases such as arteriosclerosis, vascular reobstruction, cancer and glomeruloscierosis.

Abstract translation: 本发明涉及对抑制这种激酶活性的激酶磷酸化具有抑制活性的含氮杂环化合物及其药学上可接受的盐。 本发明还涉及通过抑制激酶的磷酸化来抑制哺乳动物的激酶和治疗疾病状态的方法。 在一个特定方面，本发明提供了抑制PDGF受体的磷酸化以阻止异常细胞生长和细胞游动的含氮杂环化合物及其药学上可接受的盐，以及预防或治疗细胞增殖性疾病如动脉硬化，血管 重建，癌症和肾小球硬化。

公开(公告)号：US06889287B2

公开(公告)日：2005-05-03

申请号：US10149552

申请日：2001-10-12

Applicant: Junko Sasaki

Inventor： Junko Sasaki

IPC: G06F12/16 ,  G06F11/00 ,  G06F12/00 ,  G06F12/02 ,  G06F12/08 ,  G06F12/06

CPC classification number: G06F12/0246 ,  G06F12/0292

Abstract: A data read request for a logical address Nlog is supplied from a host system to a memory apparatus. A data processing portion calculates a physical block number Nphy corresponding to the logical address Nlog using a logical-physical conversion criterion value NBASE and a logical-physical conversion multiplier NMUL of the mapping reference information. By referencing an unusable block correlation table, it is determined whether the physical block number Nphy represents an unusable block. When the physical block number Nphy represents an unusable block, a substitute block number replaces the physical block number Nphy. The data located at the physical block number Nphy or at the substitute block number is then read from a memory portion. The read data is supplied from the data processing portion to a communicating portion which supplies the read data to the host system.

Abstract translation: 从主机系统向存储器装置提供对逻辑地址N 的数据读取请求。 数据处理部分使用逻辑 - 物理转换标准值N SUB BASE来计算与逻辑地址N＆gt; log＆lt;＆gt;相对应的物理块号码N SUB， 映射参考信息的逻辑 - 物理转换乘数N MUL 。 通过引用不可用的块相关表，确定物理块号N SUB是否表示不可用的块。 当物理块号N SUB表示不可用块时，替代块号代替物理块号N SUB phy。 然后从存储器部分读取位于物理块编号N＆gt; phy / /或替代块编号处的数据。 读取数据从数据处理部分提供给将读取的数据提供给主机系统的通信部分。

公开(公告)号：US07296119B2

公开(公告)日：2007-11-13

申请号：US11115713

申请日：2005-04-27

Applicant: Junko Sasaki

Inventor： Junko Sasaki

IPC: G06F12/06 ,  G06F11/00

CPC classification number: G06F12/0246 ,  G06F12/0292

Abstract: A block correlation table includes block addresses of unusable block portions in an irreversibly writeable memory and includes addresses of associated substitute block portions in the irreversibly writeable memory. A request for data stored at a logical address is received from a host processor. A physical address in the irreversibly writeable memory is calculated from the logical address using a fixed mathematical relation. The physical address is compared with the block addresses in the block correlation table. When the physical address does not match any of the block addresses in the table, the irreversibly writeable memory is referenced to read data stored at the physical address, and when the physical address matches one of the block addresses in the table, the irreversibly writeable memory is referenced to read data stored at the address of its associated substitute block portion. The read data is transmitted to the host processor.

公开(公告)号：US07203958B2

公开(公告)日：2007-04-10

申请号：US10190735

申请日：2002-07-09

Applicant: Hiroshi Tanaka ,  Junko Sasaki

Inventor： Hiroshi Tanaka ,  Junko Sasaki

IPC: H04L9/00

CPC classification number: H04L9/0863 ,  H04L9/3226

Abstract: First and second codes specific to each program are prepared. The first code is encrypted to generate a first encrypted code that encrypts the second code to generate a second encrypted code. The second encrypted code is stored in a memory medium. An install key that the user needs to input is made by combining the first code and the second code. To authorize installation, the first code contained in the input install key is converted into the first encrypted code in the medium, and a computer on which a program is installed obtains the first encrypted code and generates the second encrypted code by encrypting the second code contained in the install key on the basis of the first encrypted code. Then, the computer reads out the second encrypted code stored in the medium and compares both of them, thereby giving the installation authorization.

Abstract translation: 准备每个程序专用的第一和第二代码。 第一代码被加密以产生加密第二代码以生成第二加密代码的第一加密代码。 第二加密代码被存储在存储介质中。 通过组合第一个代码和第二个代码来完成用户需要输入的安装密钥。 要授权安装，输入安装密钥中包含的第一个代码被转换为介质中的第一个加密代码，并且安装了程序的计算机获取第一个加密代码，并通过加密第二个加密代码来生成第二个加密代码 在安装密钥的基础上第一个加密的代码。 然后，计算机读出存储在介质中的第二加密代码，并比较两者，从而给出安装授权。

公开(公告)号：US20060047889A1

公开(公告)日：2006-03-02

申请号：US11207340

申请日：2005-08-19

Applicant: Junko Sasaki ,  Kenichi Nakanishi ,  Nobuhiro Kaneko

Inventor： Junko Sasaki ,  Kenichi Nakanishi ,  Nobuhiro Kaneko

IPC: G06F12/10

CPC classification number: G06F12/0246

Abstract: A memory device and controlling method for nonvolatile memory are provided. The memory device and the controlling method for a nonvolatile memory are provided by which, where a file management system wherein there is a tendency that lower logic addresses are used frequently like the MS-DOS is adopted, physical blocks of a flash memory are used in an averaged fashion and the life of the flash memory can be elongated thereby.

Abstract translation: 提供了一种用于非易失性存储器的存储器件和控制方法。 提供了一种用于非易失性存储器的存储器件和控制方法，其中采用如MS-DOS那样经常使用较低逻辑地址的趋势的文件管理系统，其中使用闪速存储器的物理块 平均的时尚和闪存的使用寿命可以延长。

公开(公告)号：US20050174857A1

公开(公告)日：2005-08-11

申请号：US11047723

申请日：2005-02-02

Applicant: Takahiro Fukushige ,  Kenichi Satori ,  Kenichi Nakanishi ,  Hideaki Bando ,  Junko Sasaki ,  Kunihiko Miura ,  Toshinori Nakamura ,  Kensuke Hatsukawa

Inventor： Takahiro Fukushige ,  Kenichi Satori ,  Kenichi Nakanishi ,  Hideaki Bando ,  Junko Sasaki ,  Kunihiko Miura ,  Toshinori Nakamura ,  Kensuke Hatsukawa

IPC: G06F12/06 ,  G06F12/00 ,  G11C5/00 ,  G11C16/10

CPC classification number: G11C16/10 ,  G11C2216/22

Abstract: A nonvolatile-memory controlling method is disclosed which continuously accesses a plurality of memory banks structured so as to have each memory bank accessible independently. The method comprises the steps of: in a busy cycle of one of the plurality of memory banks being accessed, issuing access information to a second memory bank for access thereto; bringing the second memory bank into a selected state while the access information is being issued to the second memory bank using a selection signal for controlling a selected state and an unselected state for any one of the plurality of memory banks; bringing the memory bank in the busy cycle into an unselected state while the access information is being issued; and accessing the plurality of memory banks continuously based on the access information issued to the second memory bank in the busy cycle of one of the memory banks being accessed and in keeping with the selection signal for controlling the second memory bank.

Abstract translation: 公开了一种非易失性存储器控制方法，其连续地访问结构化以使每个存储体可独立访问的多个存储体。 该方法包括以下步骤：在被访问的多个存储器组之一的繁忙周期中，向第二存储体发出访问信息以访问它; 当使用用于控制所选状态的选择信号和所述多个存储体中的任何一个的未选择状态向所述第二存储体发出访问信息时，使所述第二存储体进入选择状态; 在正在发出访问信息的同时，将忙碌周期中的存储器置于未选择状态; 以及基于在被访问的一个存储体组的忙周期中发送到第二存储体的访问信息并且与用于控制第二存储体的选择信号一起存取多个存储体。