公开(公告)号：US08472259B2

公开(公告)日：2013-06-25

申请号：US13175176

申请日：2011-07-01

申请人： Takuya Futatsuyama ,  Mitsuaki Honma

发明人： Takuya Futatsuyama ,  Mitsuaki Honma

IPC分类号： G11C16/06

CPC分类号： G11C11/5628 ,  G11C16/0483 ,  G11C16/3418 ,  G11C16/3459 ,  G11C2211/5621

摘要： A non-volatile semiconductor memory device according to an embodiment includes a data write portion, the data write portion includes, in a write loop, a first operation mode of sequentially performing a program operation and a first verify operation, and a second operation mode of sequentially performing the program operation, the first verify operation, and a second verify operation, and the data write portion includes, in the first verify operation, precharging a bit-line connected to the first memory cell and a bit-line connected to a second memory cell adjacent to the first memory cell and verifying data of the first memory cell, then in the second verify operation, when the write to the second memory cell is completed, without precharging the bit-line connected to the second memory cell, precharging the bit-line connected to the first memory cell and verifying data of the first memory cell.

摘要翻译： 根据实施例的非易失性半导体存储器件包括数据写入部分，数据写入部分在写入循环中包括顺序地执行编程操作和第一校验操作的第一操作模式和第二操作模式 顺序地执行编程操作，第一验证操作和第二验证操作，并且数据写入部分在第一验证操作中包括对连接到第一存储器单元的位线和连接到第二存储器单元的位线进行预充电 与所述第一存储单元相邻并且验证所述第一存储器单元的数据，则在所述第二验证操作中，当对所述第二存储单元的写入完成时，在不预先充电连接到所述第二存储单元的位线的情况下， 位线连接到第一存储器单元并且验证第一存储器单元的数据。

公开(公告)号：US08233325B2

公开(公告)日：2012-07-31

申请号：US13108641

申请日：2011-05-16

申请人： Kiyofumi Sakurai ,  Takuya Futatsuyama

发明人： Kiyofumi Sakurai ,  Takuya Futatsuyama

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： G11C16/08 ,  G11C8/08 ,  G11C16/0483

摘要： A method of controlling a programming of a flash memory with memory blocks. The method includes checking whether a selected block among the memory blocks belongs to a first group or a second group. The method further includes executing the programming from a least bit address when the selected block belongs to the first group. The method also includes executing the programming from a most bit address when the selected block belongs to the second group.

摘要翻译： 一种利用存储块控制闪速存储器编程的方法。 该方法包括检查存储器块中的所选块是否属于第一组或第二组。 该方法还包括当所选择的块属于第一组时从最小位地址执行编程。 该方法还包括当所选择的块属于第二组时从大多数位地址执行编程。

公开(公告)号：US20110267867A1

公开(公告)日：2011-11-03

申请号：US13183103

申请日：2011-07-14

申请人： Makoto SAKUMA ,  Takuya Futatsuyama

发明人： Makoto SAKUMA ,  Takuya Futatsuyama

IPC分类号： G11C5/06

CPC分类号： G11C5/063 ,  H01L27/0207 ,  H01L27/105

摘要： A semiconductor device includes a memory cell array area, a peripheral circuit area on a periphery of the memory cell array area, and a boundary area having a specific width between the memory cell array area and the peripheral circuit area, the memory cell array area including a cell area including nonvolatile semiconductor memory cells, linear wirings extending from inside of the cell area to an area outside the cell area, and lower layer wirings in a lower layer than the linear wirings in the boundary area and electrically connected to the linear wirings, and wiring widths of the lower layer wirings being larger than widths of the linear wirings, the peripheral circuit area including a patterns electrically connected to the linear wirings via the lower layer wirings, the boundary area failing to be provided with the linear wirings and a wiring in same layer as the linear wirings.

摘要翻译： 半导体器件包括存储单元阵列区域，存储单元阵列区域的外围的外围电路区域和存储单元阵列区域与外围电路区域之间具有特定宽度的边界区域，存储单元阵列区域包括 包括非易失性半导体存储单元的单元区域，从单元区域的内部延伸到单元区域外的线性布线，以及比边界区域中的线性布线更下层的布线，并且电连接到线性布线， 并且下层布线的布线宽度大于线性布线的宽度，外围电路区域包括经由下层布线电连接到线性布线的图案，不能设置线性布线的边界区域和布线 与线性配线相同。

公开(公告)号：US20110242892A1

公开(公告)日：2011-10-06

申请号：US13161147

申请日：2011-06-15

申请人： Yuko NAMIKI ,  Takuya Futatsuyama ,  Yuui Shimizu

发明人： Yuko NAMIKI ,  Takuya Futatsuyama ,  Yuui Shimizu

IPC分类号： G11C16/04

CPC分类号： G11C16/0483 ,  G11C16/26 ,  G11C16/3454

摘要： A non-volatile semiconductor memory device including: a NAND string having multiple memory cells connected in series and first and second select gate transistors disposed on the both ends; word lines coupled to the memory cells; and first and second select gate lines coupled to the first and second select gate transistors, wherein a data read mode is defined by the following bias condition: a selected word line is applied with a read voltage; one adjacent to the selected word line within first unselected word lines disposed on the first select gate line side is applied with a first read pass voltage while the others are applied with a second read pass voltage lower than the first read pass voltage; and second unselected word lines disposed on the second select gate line side are applied with a third read pass voltage higher than the first read voltage.

摘要翻译： 一种非易失性半导体存储器件，包括：串联多个存储单元的NAND串和设置在两端的第一和第二选择栅晶体管; 耦合到存储器单元的字线; 以及耦合到第一和第二选择栅晶体管的第一和第二选择栅极线，其中数据读取模式由以下偏置条件定义：所选择的字线被施加有读取电压; 在第一选择栅极线侧的第一非选择字线内的与选定字线相邻的一个被施加第一读取通过电压，而其它被施加的低于第一读取通过电压的第二读取通过电压; 并且布置在第二选择栅线侧的第二未选择字线被施加有高于第一读取电压的第三读取通过电压。

公开(公告)号：US08023327B2

公开(公告)日：2011-09-20

申请号：US12499237

申请日：2009-07-08

申请人： Takuya Futatsuyama

发明人： Takuya Futatsuyama

IPC分类号： G11C16/04 ,  G11C16/06

CPC分类号： G11C11/5642 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/26 ,  G11C16/344

摘要： A memory device including a NAND string with multiple memory cells connected in series, one end of the NAND string being coupled to a bit line via a first select gate transistor while the other end is coupled to a source line via a second select gate transistor, wherein the device has a data read mode performed under the bias condition of: a selected cell is applied with a read voltage; and unselected cells are applied with read pass voltages, and wherein in the data read mode, one of the unselected cells adjacent to one of the first and second select gate transistor is applied with a first read pass voltage while the other unselected cells are applied with a second read pass voltage lower than the first read pass voltage.

摘要翻译： 一种存储器件，包括具有串联连接的多个存储器单元的NAND串，所述NAND串的一端经由第一选择栅极晶体管耦合到位线，而另一端经由第二选择栅极晶体管耦合到源极线， 其中所述设备具有在偏置条件下执行的数据读取模式：所选择的单元被施加读取电压; 并且未选择的单元被施加读通道电压，并且其中在数据读取模式中，与第一和第二选择栅极晶体管中的一个相邻的未选择单元之一被施加第一读取通过电压，而另一个未选择的单元被施加 第二读通过电压低于第一读通道电压。

公开(公告)号：US07916548B2

公开(公告)日：2011-03-29

申请号：US12418215

申请日：2009-04-03

申请人： Takuya Futatsuyama

发明人： Takuya Futatsuyama

IPC分类号： G11C16/06

CPC分类号： G11C16/344

摘要： A non-volatile semiconductor storage device includes: a memory cell array including memory strings, each of the memory strings having: a first end; a second end; and a plurality of memory cells connected in series between the first end and the second end, the memory cells being categorized into memory cell groups; a first end that is one end of the memory string; and a second end that is the other end of the memory string; first selection transistors connected to the respective first ends of the memory strings; a plurality of second selection transistors connected to the respective second ends of the memory strings; bit lines connected to the respective second selection transistors; word lines connected to the memory cells; and a control circuit configured to apply different control voltages to the respective word lines.

摘要翻译： 非挥发性半导体存储装置包括：包括存储器串的存储单元阵列，每个存储器串具有：第一端; 第二端 以及在所述第一端和所述第二端之间串联连接的多个存储单元，所述存储单元被分类为存储单元组; 第一端是存储器字符串的一端; 和作为存储器串的另一端的第二端; 连接到存储器串的各个第一端的第一选择晶体管; 连接到存储器串的相应第二端的多个第二选择晶体管; 连接到相应的第二选择晶体管的位线; 连接到存储单元的字线; 以及控制电路，被配置为对各个字线施加不同的控制电压。

公开(公告)号：US20100264547A1

公开(公告)日：2010-10-21

申请号：US12774160

申请日：2010-05-05

申请人： KOSUKE YANAGIDAIRA ,  Takuya Futatsuyama ,  Toshiya Kotani

发明人： KOSUKE YANAGIDAIRA ,  Takuya Futatsuyama ,  Toshiya Kotani

IPC分类号： H01L23/52 ,  H01L23/544

CPC分类号： G11C5/02 ,  G11C5/063 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11573

摘要： A first region having a first metal wiring, the first metal wiring being buried into an insulation film with a first minimum dimension, and a second region having a second metal wiring, the second metal wiring being buried in the insulation film with a second minimum dimension which is larger than the first minimum dimension, the second region being arranged adjacent to the first region, wherein a thickness of the first metal wiring and a thickness of the second metal wiring are different.

摘要翻译： 具有第一金属布线的第一区域，所述第一金属布线被掩埋在具有第一最小尺寸的绝缘膜中，所述第二区域具有第二金属布线，所述第二金属布线以第二最小尺寸被掩埋在所述绝缘膜中 其大于第一最小尺寸，第二区域布置成与第一区域相邻，其中第一金属布线的厚度和第二金属布线的厚度不同。

公开(公告)号：US07764542B2

公开(公告)日：2010-07-27

申请号：US12061105

申请日：2008-04-02

申请人： Toshiaki Edahiro ,  Takuya Futatsuyama ,  Toshiyuki Enda

发明人： Toshiaki Edahiro ,  Takuya Futatsuyama ,  Toshiyuki Enda

IPC分类号： G11C16/04

CPC分类号： G11C16/3418 ,  G11C16/3427

摘要： A method for programming a semiconductor memory device including such a program sequence as to program target threshold levels constituting multi-level data into multiple memory cells, which are simultaneously selected, wherein the program sequence is controlled to finish programming the multiple memory cells in order of height of the target threshold levels.

摘要翻译： 一种用于将包括这样的程序序列的半导体存储器件编程的方法，所述程序序列用于将构成多级数据的程序目标阈值水平同时选择为多个存储器单元，其中控制程序序列以完成多个存储器单元的编程， 目标阈值水平的高度。

公开(公告)号：US20100080061A1

公开(公告)日：2010-04-01

申请号：US12630220

申请日：2009-12-03

申请人： NAOFUMI ABIKO ,  Takuya Futatsuyama

发明人： NAOFUMI ABIKO ,  Takuya Futatsuyama

IPC分类号： G11C16/04

CPC分类号： G11C16/0483 ,  G11C11/5628 ,  G11C16/10 ,  G11C16/3454 ,  G11C2211/5621 ,  G11C2211/5634 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： According to an embodiment, a nonvolatile semiconductor memory system includes: a nonvolatile semiconductor memory; and a memory controller having: a memory interface unit that inputs commands to the nonvolatile semiconductor memory and inputs or outputs data between the nonvolatile semiconductor memory; a memory that stores writing information indicating a memory cell transistor that is written the latest in each of the NAND cell units; and a processor that sets a read voltage based on the writing information to read out data from the memory cell transistors connected to a first word line; wherein a row controller is configured to set a plurality of levels of the read voltage to be applied to the first word line, with respect to one threshold for discriminating data stored in a memory cell transistors.

摘要翻译： 根据实施例，非易失性半导体存储器系统包括：非易失性半导体存储器; 以及存储器控制器，具有：存储器接口单元，其向非易失性半导体存储器输入命令并在非易失性半导体存储器之间输入或输出数据; 存储器，其存储表示在每个NAND单元单元中写入最新的存储单元晶体管的写入信息; 以及处理器，其基于写入信息设置读取电压，以从连接到第一字线的存储单元晶体管读出数据; 其中行控制器被配置为相对于用于识别存储在存储单元晶体管中的数据的一个阈值来设置要施加到第一字线的读取电压的多个电平。

公开(公告)号：US07646646B2

公开(公告)日：2010-01-12

申请号：US12032206

申请日：2008-02-15

申请人： Yoshikazu Hosomura ,  Takuya Futatsuyama

发明人： Yoshikazu Hosomura ,  Takuya Futatsuyama

IPC分类号： G11C16/06 ,  G11C16/04

CPC分类号： G11C16/3418

摘要： According to one embodiment, a nonvolatile semiconductor memory device includes: a memory cell array having: a cell string including a plurality of memory cells connected in series; a plurality of word lines respectively connected to the plurality of memory cells; a source side selecting gate connected to one end of the cell string; and a drain side selecting gate connected to the other end of the cell string; a word line selector that selects one of the word lines connected to a target memory cell to be written; and an equalizing unit that equalizes voltages of the plurality of word lines after data write of the target memory cell is finished.

摘要翻译： 根据一个实施例，非易失性半导体存储器件包括：存储单元阵列，具有：具有串联连接的多个存储单元的单元串; 分别连接到所述多个存储单元的多个字线; 连接到单元串的一端的源极侧选择栅极; 和连接到电池串的另一端的漏极侧选择栅极; 字线选择器，其选择连接到要写入的目标存储器单元的字线之一; 以及在目标存储单元的数据写入之后均衡多个字线的电压的均衡单元结束。