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1.发明授权公开(公告)号：US09153502B2
公开(公告)日：2015-10-06
申请号：US13494553
申请日：2012-06-12
CPC分类号： H01L22/14 , G01R31/2894 , H01L22/20
摘要： A semiconductor chip testing method includes: (a) testing the electrical characteristics of each of semiconductor chips in the form of wafers or in the form of chips formed on a predetermined number of semiconductor wafers having certain relationship, and determining if the semiconductor chip is non-defective or defective; (b) calculating a percentage of semiconductor chips determined to be defective as a fraction defective for each of wafer addresses based on determination results about the semiconductor chips on the predetermined number of semiconductor wafers, the wafer addresses indicating the respective positions of the semiconductor chips on the semiconductor wafers; and (c) changing a determination result about a semiconductor chip determined to be non-defective to defective, the semiconductor chip being at a wafer address determined to have a fraction defective at a threshold or higher than the threshold.
摘要翻译： 半导体芯片测试方法包括：（a）测试晶片形式的半导体芯片或形成在具有一定关系的预定数量的半导体晶片上的芯片形式的每个半导体芯片的电特性，以及确定半导体芯片是否为非 有缺陷或有缺陷的; （b）基于关于预定数量的半导体晶片上的半导体芯片的确定结果，计算确定为有缺陷的半导体芯片的百分比，作为每个晶片地址的分数缺陷，晶片地址指示半导体芯片的相应位置 半导体晶圆; 以及（c）将确定为无缺陷的半导体芯片的确定结果改变为不合格，所述半导体芯片处于被确定为具有阈值以上或阈值以下的部分缺陷的晶片地址。
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2.发明申请公开(公告)号：US20130080088A1
公开(公告)日：2013-03-28
申请号：US13494553
申请日：2012-06-12
CPC分类号： H01L22/14 , G01R31/2894 , H01L22/20
摘要： A semiconductor chip testing method includes: (a) testing the electrical characteristics of each of semiconductor chips in the form of wafers or in the form of chips formed on a predetermined number of semiconductor wafers having certain relationship, and determining if the semiconductor chip is non-defective or defective; (b) calculating a percentage of semiconductor chips determined to be defective as a fraction defective for each of wafer addresses based on determination results about the semiconductor chips on the predetermined number of semiconductor wafers, the wafer addresses indicating the respective positions of the semiconductor chips on the semiconductor wafers; and (c) changing a determination result about a semiconductor chip determined to be non-defective to defective, the semiconductor chip being at a wafer address determined to have a fraction defective at a threshold or higher than the threshold.
摘要翻译： 半导体芯片测试方法包括：（a）测试晶片形式的半导体芯片或形成在具有一定关系的预定数量的半导体晶片上的芯片形式的每个半导体芯片的电特性，以及确定半导体芯片是否为非 有缺陷或有缺陷的; （b）基于关于预定数量的半导体晶片上的半导体芯片的确定结果，计算确定为有缺陷的半导体芯片的百分比，作为每个晶片地址的分数缺陷，晶片地址指示半导体芯片的各个位置 半导体晶圆; 以及（c）将确定为无缺陷的半导体芯片的确定结果改变为不合格，所述半导体芯片处于被确定为具有阈值以上或阈值以下的部分缺陷的晶片地址。
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公开(公告)号：US20110024896A1
公开(公告)日：2011-02-03
申请号：US12934127
申请日：2008-07-07
IPC分类号： H01L23/34
CPC分类号： H01L23/492 , H01L23/3735 , H01L24/29 , H01L24/32 , H01L24/33 , H01L25/072 , H01L25/18 , H01L2224/32057 , H01L2224/83385 , H01L2924/01004 , H01L2924/01005 , H01L2924/01033 , H01L2924/01042 , H01L2924/014 , H01L2924/1305 , H01L2924/13055 , H01L2924/30107 , H01L2924/351 , H01L2924/00
摘要： A power semiconductor device that can reduce the mounting area thereof will be provided. A first metal plate is connected to a first power terminal of a power chip. A second metal plate facing the first metal plate is connected to a second power terminal of the power chip. An insulating cover coats the power chip from outside of the first and second metal plates. An exterior signal terminal connected to the signal terminal of the power chip is derived from an upper surface of the insulating cover. The first and second metal plate respectively includes first and second exterior electric power terminals derived from a lower surface of the insulating cover. The first and second exterior electric power terminals are bent to opposite directions. In a bending direction of the first exterior electric power terminal or the second exterior electric power terminal, the second exterior electric power terminal is not present on opposite side of the first exterior electric power terminal across the insulating cover, and the first exterior electric power terminal is not present on opposite side of the second exterior electric power terminal across the insulating cover.
摘要翻译： 将提供能够减小其安装面积的功率半导体器件。 第一金属板连接到功率芯片的第一电源端子。 面对第一金属板的第二金属板连接到功率芯片的第二电源端子。 绝缘盖从第一和第二金属板的外部涂覆功率芯片。 连接到功率芯片的信号端子的外部信号端子从绝缘盖的上表面导出。 第一和第二金属板分别包括从绝缘盖的下表面衍生的第一和第二外部电功率端子。 第一和第二外部电力端子被弯曲到相反的方向。 在第一外部电力端子或第二外部电力端子的弯曲方向上，第二外部电力端子不存在于穿过绝缘盖的第一外部电力端子的相对侧，并且第一外部电力端子 不在绝缘盖上的第二外部电力端子的相对侧。
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4.发明授权公开(公告)号：US08390097B2
公开(公告)日：2013-03-05
申请号：US11623932
申请日：2007-01-17
IPC分类号： H01L27/082
CPC分类号： H01L29/7397 , H01L29/0696 , H01L29/66348
摘要： An IGBT comprises trenches arranged in strips, first emitter diffusion layers formed so as to extend in a direction intersecting the trenches, and contact regions formed to have a rectangular shape. The portions of the contact regions on the first emitter diffusion layers have a smaller width than the other portions, the width extending in the direction intersecting the trenches. This configuration allows for an increase in the emitter ballast resistance of the emitter diffusion layers, resulting in enhanced resistance to electrical breakdown due to short circuit.
摘要翻译： IGBT包括排列成条的沟槽，形成为沿与沟槽交叉的方向延伸的第一发射极扩散层和形成为矩形形状的接触区域。 第一发射极扩散层上的接触区域的部分宽度比其他部分宽，宽度在与沟槽相交的方向上延伸。 这种配置允许发射极扩散层的发射极镇流电阻增加，导致由于短路而增强的电击穿耐性。
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5.发明授权Semiconductor device with enhanced switching speed and method for manufacturing the same 有权具有增强的开关速度的半导体器件及其制造方法公开(公告)号：US07777249B2
公开(公告)日：2010-08-17
申请号：US11753886
申请日：2007-05-25
CPC分类号： H01L29/7397 , H01L29/0619 , H01L29/0834 , H01L29/32 , H01L29/66348
摘要： A method for manufacturing a semiconductor device according to the present invention has a step of forming a plurality of MOSFETs each having a channel of a first conductivity type in a stripe on the first major surface of a wafer; a step of implanting an impurity of a first conductivity type into the second major surface of the wafer, and performing a laser annealing treatment in a stripe leaving equidistant gaps, to form a buffer layer that has been activated in a stripe; a step of implanting an impurity of a second conductivity type into the second major surface of the substrate after forming the buffer layer, and performing a laser annealing treatment on the entire surface of the second major surface, to form a collector layer, and to activate the buffer layer; and a step of forming an emitter electrode on the first major surface, and forming a collector electrode on the second major surface.
摘要翻译： 根据本发明的半导体器件的制造方法具有如下步骤：在晶片的第一主表面上形成具有第一导电类型的沟道的多个MOSFET; 将第一导电类型的杂质注入到晶片的第二主表面中的步骤，并且在条纹上进行激光退火处理，留出等距离的间隙，以形成已经被激活的缓冲层; 在形成缓冲层之后，将第二导电类型的杂质注入基板的第二主表面，并在第二主表面的整个表面上进行激光退火处理以形成集电体层并激活 缓冲层; 以及在所述第一主表面上形成发射极的步骤，以及在所述第二主表面上形成集电极。
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公开(公告)号：US20080079066A1
公开(公告)日：2008-04-03
申请号：US11623932
申请日：2007-01-17
IPC分类号： H01L29/94
CPC分类号： H01L29/7397 , H01L29/0696 , H01L29/66348
摘要： An IGBT comprises trenches arranged in strips, first emitter diffusion layers formed so as to extend in a direction intersecting the trenches, and contact regions formed to have a rectangular shape. The portions of the contact regions on the first emitter diffusion layers have a smaller width than the other portions, the width extending in the direction intersecting the trenches. This configuration allows for an increase in the emitter ballast resistance of the emitter diffusion layers, resulting in enhanced resistance to electrical breakdown due to short circuit.
摘要翻译： IGBT包括排列成条的沟槽，形成为沿与沟槽交叉的方向延伸的第一发射极扩散层和形成为矩形形状的接触区域。 第一发射极扩散层上的接触区域的部分宽度比其他部分宽，宽度在与沟槽相交的方向上延伸。 这种配置允许发射极扩散层的发射极镇流电阻增加，导致由于短路而增强的电击穿耐性。
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公开(公告)号：US20080173893A1
公开(公告)日：2008-07-24
申请号：US11753886
申请日：2007-05-25
IPC分类号： H01L29/74 , H01L21/332
CPC分类号： H01L29/7397 , H01L29/0619 , H01L29/0834 , H01L29/32 , H01L29/66348
摘要： A method for manufacturing a semiconductor device according to the present invention has a step of forming a plurality of MOSFETs each having a channel of a first conductivity type in a stripe on the first major surface of a wafer; a step of implanting an impurity of a first conductivity type into the second major surface of the wafer, and performing a laser annealing treatment in a stripe leaving equidistant gaps, to form a buffer layer that has been activated in a stripe; a step of implanting an impurity of a second conductivity type into the second major surface of the substrate after forming the buffer layer, and performing a laser annealing treatment on the entire surface of the second major surface, to form a collector layer, and to activate the buffer layer; and a step of forming an emitter electrode on the first major surface, and forming a collector electrode on the second major surface.
摘要翻译： 根据本发明的半导体器件的制造方法具有如下步骤：在晶片的第一主表面上形成具有第一导电类型的沟道的多个MOSFET; 将第一导电类型的杂质注入到晶片的第二主表面中的步骤，并且在条纹上进行激光退火处理，留出等距离的间隙，以形成已经被激活的缓冲层; 在形成缓冲层之后，将第二导电类型的杂质注入基板的第二主表面，并在第二主表面的整个表面上进行激光退火处理以形成集电体层并激活 缓冲层; 以及在所述第一主表面上形成发射极的步骤，以及在所述第二主表面上形成集电极。
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公开(公告)号：USD475012S1
公开(公告)日：2003-05-27
申请号：US29149963
申请日：2001-10-25
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公开(公告)号：US6002153A
公开(公告)日：1999-12-14
申请号：US760806
申请日：1996-12-05
IPC分类号： H01L27/02 , H01L29/739 , H01L29/76 , H01L29/74 , H01L29/94 , H01L31/062
CPC分类号： H01L27/0248 , H01L29/7395
摘要： In an IGBT with a current sensing function having a plurality of principal current cells and at least one current sensing cell, a P-type base region of the current sensing cell in a current sensing cell region is formed larger than a P-type base region of the principal current cell in a principal current cell region. The IGBT is so constituted that the influence of temperature characteristic of parasitic resistor between the principal current cells and current sensing cell upon detected current can be eliminated and the same interval between the P-type base regions can be set for all the cells.
摘要翻译： 在具有多个主电流单元和至少一个电流感测单元的具有电流感测功能的IGBT中，电流感测单元区域中的电流感测单元的P型基极区域形成为大于P型基极区域 的主要当前单元格区域。 IGBT被构造成可以消除在检测电流时主电流单元与电流感测单元之间的寄生电阻的温度特性的影响，并且可以为所有单元设置P型基极区之间的相同间隔。
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10.发明授权
公开(公告)号：US5124772A
公开(公告)日：1992-06-23
申请号：US579660
申请日：1990-09-10
IPC分类号： H01L29/78 , H01L21/336 , H01L29/06 , H01L29/08 , H01L29/32 , H01L29/36 , H01L29/739
CPC分类号： H01L29/7395 , H01L29/0696 , H01L29/32 , H01L29/36 , H01L29/0847 , Y10S438/904
摘要： In a power semiconductor device such as an IGBT, a fifth region of n conductivity type is provided. The fifth region is formed in a portion of a second region (drain region) contacting an insulating layer below the gate layer. The fifth region contacts a third region (base region) and has an impurity concentration higher than that of the second region. Therefore, even when a carrier life time is sufficiently short, an electron distribution density can be kept high in the entire fifth region and the second region under the third region (base region) near the fifth region, and the localization of a hole current is moderated (in a case of a p-type base and an n-type drain). As a result, a maximum controllable current is increased, and a wide safe operation area can be obtained.
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