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1.发明授权
公开(公告)号：US5124772A
公开(公告)日：1992-06-23
申请号：US579660
申请日：1990-09-10
IPC分类号： H01L29/78 , H01L21/336 , H01L29/06 , H01L29/08 , H01L29/32 , H01L29/36 , H01L29/739
CPC分类号： H01L29/7395 , H01L29/0696 , H01L29/32 , H01L29/36 , H01L29/0847 , Y10S438/904
摘要： In a power semiconductor device such as an IGBT, a fifth region of n conductivity type is provided. The fifth region is formed in a portion of a second region (drain region) contacting an insulating layer below the gate layer. The fifth region contacts a third region (base region) and has an impurity concentration higher than that of the second region. Therefore, even when a carrier life time is sufficiently short, an electron distribution density can be kept high in the entire fifth region and the second region under the third region (base region) near the fifth region, and the localization of a hole current is moderated (in a case of a p-type base and an n-type drain). As a result, a maximum controllable current is increased, and a wide safe operation area can be obtained.
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2.发明授权
公开(公告)号：US5143865A
公开(公告)日：1992-09-01
申请号：US731392
申请日：1991-07-17
IPC分类号： H01L21/60 , H01L23/485 , H01L23/532
CPC分类号： H01L24/10 , H01L23/53209 , H01L24/13 , H01L2224/0401 , H01L2224/05548 , H01L2224/05567 , H01L2224/13 , H01L2224/13007 , H01L2224/13022 , H01L2224/13099 , H01L2224/45124 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01018 , H01L2924/0102 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01042 , H01L2924/01047 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/10253 , H01L2924/1301 , H01L2924/1305 , H01L2924/15787 , Y10S438/928
摘要： A semiconductor element is formed in a semiconductor substrate. An electrode wiring pattern which is connected to the active region and contains aluminum as the main component is formed on the main surface of said semiconductor substrate. A metal bump is formed on the electrode wiring pattern. The metal bump contains zinc of 1 to 10% in mass percentage in addition to at least one element selected from a group consisting of tin, lead and aluminum a second metal bump is formed having a lower melting point than that of first bump. The second bump contains lead, tin and at least one of silver and copper.
摘要翻译： 在半导体衬底中形成半导体元件。 在所述半导体衬底的主表面上形成连接到有源区并含有铝作为主要成分的电极布线图案。 在电极布线图案上形成金属凸块。 除了选自由锡，铅和铝组成的组中的至少一种元素之外，金属凸块还含有质量百分比为1〜10％的锌，形成熔点低于第一凸点的第二金属凸块。 第二个凸起包含铅，锡和至少一种银和铜。
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公开(公告)号：US5115300A
公开(公告)日：1992-05-19
申请号：US622591
申请日：1990-12-05
申请人： Shingo Yanagida , Tetsujiro Tsunoda
发明人： Shingo Yanagida , Tetsujiro Tsunoda
CPC分类号： H01L23/62 , H01L2224/05553 , H01L2224/451 , H01L2224/48091 , H01L2224/48227 , H01L2224/48472 , H01L24/45 , H01L24/48 , H01L2924/00014 , H01L2924/01014 , H01L2924/1301 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/14
摘要： A high-power semiconductor device comprises a overcurrent detecting terminal. One of conductive layers selectively adhered to a substrate of the semiconductor device is thinner than the other conductive layers. One of terminals for an electrode of the semiconductor element of the high-power semiconductor device is connected to one end of the thinner conductive layer. The overcurrent detecting terminal is electrically connected to said electrode, and to the other end of the thinner conductive layer. A potential difference between the terminal and the overcurrent detecting terminal is measured, in order to detect a current, to prevent an overcurrent from flowing through the semiconductor element.
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公开(公告)号：USD475012S1
公开(公告)日：2003-05-27
申请号：US29149963
申请日：2001-10-25
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公开(公告)号：US6002153A
公开(公告)日：1999-12-14
申请号：US760806
申请日：1996-12-05
IPC分类号： H01L27/02 , H01L29/739 , H01L29/76 , H01L29/74 , H01L29/94 , H01L31/062
CPC分类号： H01L27/0248 , H01L29/7395
摘要： In an IGBT with a current sensing function having a plurality of principal current cells and at least one current sensing cell, a P-type base region of the current sensing cell in a current sensing cell region is formed larger than a P-type base region of the principal current cell in a principal current cell region. The IGBT is so constituted that the influence of temperature characteristic of parasitic resistor between the principal current cells and current sensing cell upon detected current can be eliminated and the same interval between the P-type base regions can be set for all the cells.
摘要翻译： 在具有多个主电流单元和至少一个电流感测单元的具有电流感测功能的IGBT中，电流感测单元区域中的电流感测单元的P型基极区域形成为大于P型基极区域 的主要当前单元格区域。 IGBT被构造成可以消除在检测电流时主电流单元与电流感测单元之间的寄生电阻的温度特性的影响，并且可以为所有单元设置P型基极区之间的相同间隔。
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6.发明授权公开(公告)号：US09153502B2
公开(公告)日：2015-10-06
申请号：US13494553
申请日：2012-06-12
CPC分类号： H01L22/14 , G01R31/2894 , H01L22/20
摘要： A semiconductor chip testing method includes: (a) testing the electrical characteristics of each of semiconductor chips in the form of wafers or in the form of chips formed on a predetermined number of semiconductor wafers having certain relationship, and determining if the semiconductor chip is non-defective or defective; (b) calculating a percentage of semiconductor chips determined to be defective as a fraction defective for each of wafer addresses based on determination results about the semiconductor chips on the predetermined number of semiconductor wafers, the wafer addresses indicating the respective positions of the semiconductor chips on the semiconductor wafers; and (c) changing a determination result about a semiconductor chip determined to be non-defective to defective, the semiconductor chip being at a wafer address determined to have a fraction defective at a threshold or higher than the threshold.
摘要翻译： 半导体芯片测试方法包括：（a）测试晶片形式的半导体芯片或形成在具有一定关系的预定数量的半导体晶片上的芯片形式的每个半导体芯片的电特性，以及确定半导体芯片是否为非 有缺陷或有缺陷的; （b）基于关于预定数量的半导体晶片上的半导体芯片的确定结果，计算确定为有缺陷的半导体芯片的百分比，作为每个晶片地址的分数缺陷，晶片地址指示半导体芯片的相应位置 半导体晶圆; 以及（c）将确定为无缺陷的半导体芯片的确定结果改变为不合格，所述半导体芯片处于被确定为具有阈值以上或阈值以下的部分缺陷的晶片地址。
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7.发明申请公开(公告)号：US20130080088A1
公开(公告)日：2013-03-28
申请号：US13494553
申请日：2012-06-12
CPC分类号： H01L22/14 , G01R31/2894 , H01L22/20
摘要： A semiconductor chip testing method includes: (a) testing the electrical characteristics of each of semiconductor chips in the form of wafers or in the form of chips formed on a predetermined number of semiconductor wafers having certain relationship, and determining if the semiconductor chip is non-defective or defective; (b) calculating a percentage of semiconductor chips determined to be defective as a fraction defective for each of wafer addresses based on determination results about the semiconductor chips on the predetermined number of semiconductor wafers, the wafer addresses indicating the respective positions of the semiconductor chips on the semiconductor wafers; and (c) changing a determination result about a semiconductor chip determined to be non-defective to defective, the semiconductor chip being at a wafer address determined to have a fraction defective at a threshold or higher than the threshold.
摘要翻译： 半导体芯片测试方法包括：（a）测试晶片形式的半导体芯片或形成在具有一定关系的预定数量的半导体晶片上的芯片形式的每个半导体芯片的电特性，以及确定半导体芯片是否为非 有缺陷或有缺陷的; （b）基于关于预定数量的半导体晶片上的半导体芯片的确定结果，计算确定为有缺陷的半导体芯片的百分比，作为每个晶片地址的分数缺陷，晶片地址指示半导体芯片的各个位置 半导体晶圆; 以及（c）将确定为无缺陷的半导体芯片的确定结果改变为不合格，所述半导体芯片处于被确定为具有阈值以上或阈值以下的部分缺陷的晶片地址。
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公开(公告)号：US20110024896A1
公开(公告)日：2011-02-03
申请号：US12934127
申请日：2008-07-07
IPC分类号： H01L23/34
CPC分类号： H01L23/492 , H01L23/3735 , H01L24/29 , H01L24/32 , H01L24/33 , H01L25/072 , H01L25/18 , H01L2224/32057 , H01L2224/83385 , H01L2924/01004 , H01L2924/01005 , H01L2924/01033 , H01L2924/01042 , H01L2924/014 , H01L2924/1305 , H01L2924/13055 , H01L2924/30107 , H01L2924/351 , H01L2924/00
摘要： A power semiconductor device that can reduce the mounting area thereof will be provided. A first metal plate is connected to a first power terminal of a power chip. A second metal plate facing the first metal plate is connected to a second power terminal of the power chip. An insulating cover coats the power chip from outside of the first and second metal plates. An exterior signal terminal connected to the signal terminal of the power chip is derived from an upper surface of the insulating cover. The first and second metal plate respectively includes first and second exterior electric power terminals derived from a lower surface of the insulating cover. The first and second exterior electric power terminals are bent to opposite directions. In a bending direction of the first exterior electric power terminal or the second exterior electric power terminal, the second exterior electric power terminal is not present on opposite side of the first exterior electric power terminal across the insulating cover, and the first exterior electric power terminal is not present on opposite side of the second exterior electric power terminal across the insulating cover.
摘要翻译： 将提供能够减小其安装面积的功率半导体器件。 第一金属板连接到功率芯片的第一电源端子。 面对第一金属板的第二金属板连接到功率芯片的第二电源端子。 绝缘盖从第一和第二金属板的外部涂覆功率芯片。 连接到功率芯片的信号端子的外部信号端子从绝缘盖的上表面导出。 第一和第二金属板分别包括从绝缘盖的下表面衍生的第一和第二外部电功率端子。 第一和第二外部电力端子被弯曲到相反的方向。 在第一外部电力端子或第二外部电力端子的弯曲方向上，第二外部电力端子不存在于穿过绝缘盖的第一外部电力端子的相对侧，并且第一外部电力端子 不在绝缘盖上的第二外部电力端子的相对侧。
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公开(公告)号：USD467869S1
公开(公告)日：2002-12-31
申请号：US29149978
申请日：2001-10-25
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公开(公告)号：US6060772A
公开(公告)日：2000-05-09
申请号：US106351
申请日：1998-06-29
CPC分类号： H01L25/162 , H01L24/73 , H01L2224/05553 , H01L2224/48091 , H01L2224/49113 , H01L2224/49175 , H01L2924/01029 , H01L2924/1305 , H01L2924/13055 , H01L2924/14 , H01L2924/19107 , H01L2924/30107
摘要： On a metal base, an insulated wiring substrate is fixed, and, on a conductive layer on the insulated wiring substrate, semiconductor chips are disposed. Above the semiconductor chips, a controlling substrate is provided, and the signals produced in this controlling substrate are supplied to electrodes on the surfaces of the semiconductor chips via bonding wires passing through openings provided in the controlling substrate.
摘要翻译： 在金属基体上固定绝缘配线基板，在绝缘配线基板的导体层上配置半导体芯片。 在半导体芯片上方，设置控制基板，并且通过经由设置在控制基板中的开口的接合线，将在该控制基板中产生的信号提供给半导体芯片的表面上的电极。
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