公开(公告)号：US20050237848A1

公开(公告)日：2005-10-27

申请号：US10507117

申请日：2004-09-10

Applicant: Hiroyuki Takahashi ,  Takuya Hirota ,  Atsushi Nakagawa

Inventor： Hiroyuki Takahashi ,  Takuya Hirota ,  Atsushi Nakagawa

IPC: H01L21/822 ,  G11C11/407 ,  G11C11/4074 ,  G11C11/4076 ,  H01L27/04 ,  H03K5/14 ,  G11C8/02

CPC classification number: G11C5/145 ,  G11C5/147 ,  G11C11/4074 ,  G11C11/4085 ,  G11C2207/2227 ,  H03K5/133

Abstract: A cell core unit and its peripheral circuit are driven by a relatively low voltage power supply. A constant voltage that does not depend on the power supply voltage is provided as a boosted voltage (VBOOST) to be supplied to a control signal for a word line of the cell core unit. A sense amplifier amplifies a higher voltage level of a bit line to the power supply voltage. Then, a circuit for generating a signal for defining the transition timing and/or the pulse width of a control signal from the peripheral circuit to the cell core unit performs signal delay using a delay circuit having a characteristic in which a delay time thereof decreases with reduction of the provided power supply voltage.

Abstract translation: 电池芯单元及其外围电路由相对低压的电源驱动。 提供不依赖于电源电压的恒定电压作为提供给单元芯单元的字线的控制信号的升压电压（VBOOST）。 读出放大器将位线的较高电压电平放大到电源电压。 然后，用于产生用于定义从外围电路到小区核心单元的控制信号的转变定时和/或脉冲宽度的信号的电路使用具有延迟时间减小的特性的延迟电路来执行信号延迟， 降低所提供的电源电压。

公开(公告)号：US06331959B1

公开(公告)日：2001-12-18

申请号：US09525611

申请日：2000-03-14

Applicant: Takuya Hirota

Inventor： Takuya Hirota

IPC: G11C700

CPC classification number: G11C11/419 ,  G11C7/06

Abstract: A semiconductor storage device is disclosed that can lower sense amplifier input potentials to about a half supply potential (VCC/2) to speed up sense amplifier operations. According to one embodiment, a semiconductor storage device (100) may include a pair of digit lines (104 and 106), a memory cell (108) that can place stored data on digit lines (104 and 106), a sense amplifier (112) that may read memory cell data on digit lines (104 and 106), and switching devices (120-a and 120-b) connected between sense amplifier inputs (112-a and 112-b) and digit lines (104 and 106). Digit lines (104 and 106) may be precharged to a high potential. Memory cell data may then be placed on the digit lines (104 and 106). Prior to the activation of the sense amplifier (112) switching devices (120-a and 120-b) may lower the digit line potentials to a level more conducive to sensing by the sense amplifier (112). In this way, a read operation by the sense amplifier (112) may be faster than conventional approaches.

Abstract translation: 公开了一种半导体存储装置，其可将感测放大器输入电位降低到大约一半的电源电位（VCC / 2），以加速感测放大器的操作。 根据一个实施例，半导体存储设备（100）可以包括一对数字线（104和106），可将存储的数据放置在数字线（104和106）上的存储单元（108），读出放大器（112） ），其可读取数字线（104和106）上的存储单元数据以及连接在感测放大器输入（112-a和112-b）与数字线（104和106）之间的开关装置（120-a和120-b） 。 数字线（104和106）可以被预充电到高电位。 然后可将存储单元数据放置在数字线（104和106）上。 在激活读出放大器（112）之前，开关器件（120-a和120-b）可以将数字线电位降低到更有利于读出放大器（112）感测的电平。 以这种方式，读出放大器（112）的读取操作可能比传统的方法更快。

公开(公告)号：US6101122A

公开(公告)日：2000-08-08

申请号：US273488

申请日：1999-03-22

Applicant: Takuya Hirota

Inventor： Takuya Hirota

IPC: G11C11/417 ,  G11C11/409 ,  G11C16/06 ,  H03K3/037 ,  G11C7/00

CPC classification number: H03K3/0375

Abstract: A data latch circuit includes a differential amplifier for detecting a potential difference between a pair of signal transmission lines for transmitting a pair of complementary signals, a latch timing signal generator for generating a latch timing signal based on the detection by the differential amplifier, and a latch section for responding to the latch timing signal to latch the complementary signals transferred thereto. A reliable and high-speed signal transmission can be achieved even in a semiconductor device having a large chip size.

Abstract translation: 数据锁存电路包括：差分放大器，用于检测用于发送一对互补信号的一对信号传输线之间的电位差;基于差分放大器的检测产生锁存定时信号的锁存定时信号发生器;以及 锁存部分，用于响应锁存定时信号以锁存传送到其上的互补信号。 即使在具有大芯片尺寸的半导体器件中也可以实现可靠且高速的信号传输。

公开(公告)号：US07006401B2

公开(公告)日：2006-02-28

申请号：US10500400

申请日：2002-12-25

Applicant: Hiroyuki Takahashi ,  Takuya Hirota ,  Noriaki Komatsu ,  Atsushi Nakagawa ,  Susumu Takano ,  Masahiro Yoshida ,  Yuuji Torige ,  Hideo Inaba

Inventor： Hiroyuki Takahashi ,  Takuya Hirota ,  Noriaki Komatsu ,  Atsushi Nakagawa ,  Susumu Takano ,  Masahiro Yoshida ,  Yuuji Torige ,  Hideo Inaba

IPC: G11C7/00

CPC classification number: G11C11/40603 ,  G11C11/406

Abstract: Refresh of memory cells is performed periodically by a refresh timer, and collision between memory access and memory refresh is avoided. When memory access occurs, an F/F 163 is set by a one shot pulse from an OS circuit 161, a memory access request is inputted to a memory accessing pulse generator circuit 171 through a NOR gate 167, and a latch control signal LC and an enable signal REN are outputted. When a refresh request from the refresh timer is inputted to an AND gate 168 during the memory access, the output of the NOR gate 167 is at the “L” level, and the refresh request is blocked by the AND gate 168. Thereafter, at the time when the latch control signal LC is turned into the “L” level, F/Fs 163, 164 and 165 are reset, the output of the NOR gate 167 is turned into the “H” level, the refresh request is inputted to a refreshing pulse generator circuit 170, and a refresh enable signal RERF is outputted.

Abstract translation: 通过刷新定时器周期性地执行存储器单元的刷新，并避免存储器访问和存储器刷新之间的冲突。 当存储器访问发生时，通过来自OS电路161的单触发脉冲设置F / F 163，通过NOR门167将存储器访问请求输入到存储器访问脉冲发生器电路171，以及锁存控制信号LC和 输出使能信号REN。 当在存储器访问期间来自刷新定时器的刷新请求被输入到与门168时，或非门167的输出处于“L”电平，刷新请求由与门168阻止。 此后，当锁存控制信号LC变为“L”电平时，F / F 163,164和165被复位，或非门167的输出变为“H”电平，刷新请求 被输入到刷新脉冲发生器电路170，并且输出刷新使能信号RERF。

公开(公告)号：US20050041520A1

公开(公告)日：2005-02-24

申请号：US10920249

申请日：2004-08-18

Applicant: Hiroyuki Takahashi ,  Takuya Hirota

Inventor： Hiroyuki Takahashi ,  Takuya Hirota

IPC: G11C8/18 ,  G11C11/403 ,  G11C11/406 ,  G11C11/407 ,  G11C7/00 ,  G11C8/00

CPC classification number: G11C11/40603 ,  G11C8/18 ,  G11C11/406

Abstract: A semiconductor memory device adapted for avoiding collision between the selection period of a word line for a refresh and the selection period of a word line for a read/write, comprises a cell array including a plurality of memory cells that require refreshing for retention of storage data and means for exercising control so that when a read/write request is input in a clock cycle following a clock cycle for performing a refresh operation, a read/write operation in the cell array is delayed by at least one clock cycle, and the read/write operation is started after completion of the refresh.

Abstract translation: 适于避免用于刷新的字线的选择周期与用于读/写的字线的选择周期之间的冲突的半导体存储器件包括包括需要刷新以保持存储的多个存储器单元的单元阵列 用于执行控制的数据和装置，使得当在执行刷新操作的时钟周期之后的时钟周期中输入读/写请求时，单元阵列中的读/写操作被延迟至少一个时钟周期，并且 读/写操作在完成刷新后开始。

公开(公告)号：US07684270B2

公开(公告)日：2010-03-23

申请号：US11892488

申请日：2007-08-23

Applicant: Takuya Hirota ,  Takao Yanagida ,  Hiroyuki Takahashi

Inventor： Takuya Hirota ,  Takao Yanagida ,  Hiroyuki Takahashi

IPC: G11C7/02

CPC classification number: G11C11/4094 ,  G11C7/065 ,  G11C7/08 ,  G11C7/12 ,  G11C7/22 ,  G11C11/4074 ,  G11C11/4076 ,  G11C2207/2281

Abstract: In a conventional equalizer circuit, in an equalizing operation for setting voltages of a wiring pair having a predetermined voltage difference therebetween to be the same, it takes a long time to make the voltages of the wirings in a pair converge to a voltage having an offset with respect to a midpoint voltage of the voltages of the wiring pair after the equalizing operation. According to an equalizer circuit of the present invention, provided is an equalizer circuit (50) which sets the voltages of a first wiring (SAP) and a second wiring (SAN) to be substantially the same and which has a first transistor (N1) connected between the first wiring (SAP) and a first power supply circuit (for example, HVDD−Va) and a second transistor (N2) connected between the first wiring SAP and the second wiring (SAN). The equalizer circuit 50 makes the first transistor (N1) conductive, and then makes the second transistor (N2) conductive.

Abstract translation: 在传统的均衡器电路中，在将具有预定电压差的布线对的电压设定为相同的均衡操作中，使配线的电压成对地收敛到具有偏移的电压需要很长时间 相对于均衡动作后的配线对的电压的中点电压。 根据本发明的均衡器电路，提供了将第一布线（SAP）和第二布线（SAN）的电压设置为基本相同的并具有第一晶体管（N1）的均衡器电路（50） 连接在第一布线（SAP）和连接在第一布线SAP和第二布线（SAN）之间的第一电源电路（例如，HVDD-Va）和第二晶体管（N2）之间。 均衡器电路50使第一晶体管（N1）导通，然后使第二晶体管（N2）导通。

公开(公告)号：US07663945B2

公开(公告)日：2010-02-16

申请号：US11907442

申请日：2007-10-12

Applicant: Hiroyuki Takahashi ,  Takuya Hirota ,  Atsushi Nakagawa

Inventor： Hiroyuki Takahashi ,  Takuya Hirota ,  Atsushi Nakagawa

IPC: G11C7/22 ,  G11C8/18

CPC classification number: G11C5/145 ,  G11C5/147 ,  G11C11/4074 ,  G11C11/4085 ,  G11C2207/2227 ,  H03K5/133

Abstract: A cell core unit and its peripheral circuit are driven by a relatively low voltage power supply. A constant voltage that does not depend on the power supply voltage is provided as a boosted voltage (VBOOST) to be supplied to a control signal for a word line of the cell core unit. A sense amplifier amplifies a higher voltage level of a bit line to the power supply voltage. Then, a circuit for generating a signal for defining the transition timing and/or the pulse width of a control signal from the peripheral circuit to the cell core unit performs signal delay using a delay circuit having a characteristic in which a delay time thereof decreases with reduction of the provided power supply voltage.

Abstract translation: 电池芯单元及其外围电路由相对低压的电源驱动。 提供不依赖于电源电压的恒定电压作为提供给单元芯单元的字线的控制信号的升压电压（VBOOST）。 读出放大器将位线的较高电压电平放大到电源电压。 然后，用于产生用于定义从外围电路到小区核心单元的控制信号的转变定时和/或脉冲宽度的信号的电路使用具有延迟时间减小的特性的延迟电路来执行信号延迟， 降低所提供的电源电压。

公开(公告)号：US07489576B2

公开(公告)日：2009-02-10

申请号：US11723830

申请日：2007-03-22

Applicant: Takuya Hirota ,  Takao Yanagida

Inventor： Takuya Hirota ,  Takao Yanagida

IPC: G11C7/02

CPC classification number: G11C7/12 ,  G11C7/02 ,  G11C7/08 ,  G11C11/4091 ,  G11C11/4094 ,  G11C2207/005 ,  G11C2207/065

Abstract: A semiconductor storage device has first and second cell arrays including a plurality of memory cells to store data, a sense amplifier selectively connected with either one of the first and second cell arrays, a first precharge circuit to set a pair of bit lines in the first cell array to a predetermined voltage, a second precharge circuit to set a pair of bit lines in the second cell array to a predetermined voltage, a first switch circuit to connect the sense amplifier with the first cell array, a second switch circuit to connect the sense amplifier with the second cell array, and a switch controller to control conductive state of the first and second switch circuits. In non-selection state where the sense amplifier does not access any of the cell arrays, the switch controller controls one of the switch circuits into conducting state.

Abstract translation: 一种半导体存储装置具有包括存储数据的多个存储单元的第一和第二单元阵列，选择性地与第一和第二单元阵列中的任一个连接的读出放大器，第一预充电电路，用于在第一和第二单元阵列中设置一对位线 单元阵列到预定电压，第二预充电电路，用于将第二单元阵列中的一对位线设置为预定电压;第一开关电路，用于将读出放大器与第一单元阵列连接;第二开关电路， 具有第二单元阵列的读出放大器和用于控制第一和第二开关电路的导通状态的开关控制器。 在非选择状态，其中读出放大器不访问任何单元阵列，开关控制器将开关电路之一控制为导通状态。

公开(公告)号：US07301830B2

公开(公告)日：2007-11-27

申请号：US10507117

申请日：2004-09-10

Applicant: Hiroyuki Takahashi ,  Takuya Hirota ,  Atsushi Nakagawa

Inventor： Hiroyuki Takahashi ,  Takuya Hirota ,  Atsushi Nakagawa

IPC: G11C11/4074 ,  G11C11/4076 ,  G11C11/4063 ,  G11C7/22 ,  G11C8/18 ,  G11C8/08 ,  G11C7/12

CPC classification number: G11C5/145 ,  G11C5/147 ,  G11C11/4074 ,  G11C11/4085 ,  G11C2207/2227 ,  H03K5/133

Abstract: A cell core unit and its peripheral circuit are driven by a relatively low voltage power supply. A constant voltage that does not depend on the power supply voltage is provided as a boosted voltage (VBOOST) to be supplied to a control signal for a word line of the cell core unit. A sense amplifier amplifies a higher voltage level of a bit line to the power supply voltage. Then, a circuit for generating a signal for defining the transition timing and/or the pulse width of a control signal from the peripheral circuit to the cell core unit performs signal delay using a delay circuit having a characteristic in which a delay time thereof decreases with reduction of the provided power supply voltage.

Abstract translation: 电池芯单元及其外围电路由相对低压的电源驱动。 提供不依赖于电源电压的恒定电压作为提供给单元芯单元的字线的控制信号的升压电压（VBOOST）。 读出放大器将位线的较高电压电平放大到电源电压。 然后，用于产生用于定义从外围电路到小区核心单元的控制信号的转变定时和/或脉冲宽度的信号的电路使用具有延迟时间减小的特性的延迟电路来执行信号延迟， 降低所提供的电源电压。

公开(公告)号：US07277344B2

公开(公告)日：2007-10-02

申请号：US11360593

申请日：2006-02-24

Applicant: Hiroyuki Takahashi ,  Takuya Hirota

Inventor： Hiroyuki Takahashi ,  Takuya Hirota

IPC: G11C7/00

CPC classification number: G11C11/40615 ,  G11C11/406 ,  G11C2211/4061 ,  G11C2211/4067

Abstract: A semiconductor storage device according to an embodiment of the present invention includes: a plurality of word lines; a plurality of memory cells corresponding to the plurality of word lines; and a refresh circuit for sequentially driving the plurality of word lines to refresh each of the plurality of memory cells based on a timer period, which sets the timer period in accordance with a disturb amount in an active mode upon shift from the active mode to the standby mode.

Abstract translation: 根据本发明实施例的半导体存储装置包括：多个字线; 与所述多个字线对应的多个存储单元; 以及刷新电路，用于根据定时器周期顺序驱动多个字线以刷新每个多个存储单元，该定时器周期根据从活动模式转换到活动模式时的活动模式中的干扰量来设置定时器周期 待机模式。