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    Deposition film orientation and reflectivity improvement using a self-aligning ultra-thin layer
    1.
    发明授权
    Deposition film orientation and reflectivity improvement using a self-aligning ultra-thin layer 失效
    使用自对准超薄层的沉积膜取向和反射率提高

    公开(公告)号：US6120844A

    公开(公告)日：2000-09-19

    申请号：US622941

    申请日：1996-03-27

    申请人： Liang Chen ,  Ted Guo ,  Fusen Chen ,  Roderick C. Mosely

    发明人： Liang Chen ,  Ted Guo ,  Fusen Chen ,  Roderick C. Mosely

    IPC分类号： H01L21/28 ,  C23C14/56 ,  C23C16/54 ,  H01L21/02 ,  H01L21/203 ,  H01L21/285 ,  H01L21/3205 ,  H01L21/677 ,  H01L21/768 ,  C23C14/34 ,  C23C16/06 ,  C23C16/22

    CPC分类号： H01L21/76876 ,  C23C14/568 ,  C23C16/54 ,  H01L21/32051 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/76879

    摘要： The present invention relates generally to an improved apparatus and process to provide a thin self-aligning layer prior to forming a conducting film layer thereover to improve the film characteristics and deposition coverage. In one aspect of the invention, a dielectric layer is formed over a conducting or semiconducting layer and etched to form an aperture exposing the underlying conducting or semiconducting layer on the aperture floor. An ultra-thin nucleation layer is then deposited by either vapor deposition or chemical vapor deposition onto the field of the dielectric layer. A CVD metal layer is then deposited onto the structure to achieve selective deposition on the floor of the aperture, while preferably also forming a highly oriented blanket layer on the field. In another aspect of the invention, a thin, self-aligning layer is formed over a barrier layer prior to deposition of a conducting film thereover. It is believed that the self-aligning layer enhances the reflectivity of the films by improving the crystal structure in the resulting film and provides improved electromigration performance by providing crystal orientation. The process is preferably carried out in an integrated processing system that includes both a PVD and CVD processing chamber so that once the substrate is introduced into a vacuum environment, the process occurs without the formation of oxides between the layers.

    摘要翻译： 本发明一般涉及在形成导电膜层之前提供薄的自对准层以改善膜特性和沉积覆盖的改进的装置和工艺。 在本发明的一个方面，电介质层形成在导电或半导体层之上，并被蚀刻以形成露出孔底板上下面的导电或半导体层的孔。 然后通过气相沉积或化学气相沉积将超薄成核层沉积到电介质层的场上。 然后将CVD金属层沉积到结构上以实现孔的地板上的选择性沉积，同时优选地还在场上形成高度取向的覆盖层。 在本发明的另一方面，在其上沉积导电膜之前，在阻挡层上方形成薄的自对准层。 据认为，通过改善所得膜中的晶体结构，自对准层增强了膜的反射率，并通过提供<111>晶体取向来提供改善的电迁移性能。 该方法优选在包括PVD和CVD处理室的集成处理系统中进行，使得一旦将基底引入真空环境中，则该过程发生而不在层之间形成氧化物。

    Blanket-selective chemical vapor deposition using an ultra-thin nucleation layer
    2.
    发明授权
    Blanket-selective chemical vapor deposition using an ultra-thin nucleation layer 失效
    使用超薄成核层的毯选择性化学气相沉积

    公开(公告)号：US6066358A

    公开(公告)日：2000-05-23

    申请号：US611108

    申请日：1996-03-05

    申请人： Ted Guo ,  Liang Chen ,  Fusen Chen ,  Roderick C. Mosely

    发明人： Ted Guo ,  Liang Chen ,  Fusen Chen ,  Roderick C. Mosely

    IPC分类号： H01L21/285 ,  C23C14/56 ,  C23C16/54 ,  H01L21/28 ,  H01L21/3205 ,  H01L21/677 ,  H01L21/768 ,  B05D5/12 ,  C23C14/04 ,  C23C16/04 ,  C23C16/06

    CPC分类号： H01L21/76876 ,  C23C14/568 ,  C23C16/54 ,  H01L21/32051 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/76879

    摘要： The present invention relates generally to an improved apparatus and process for providing uniform step coverage on a substrate and planarization of conducting layers to form continuous, void-free interconnects in sub-half micron, high aspect ratio aperture width applications and highly oriented conducting layers. In one aspect of the invention, a dielectric layer is formed over a conducting or semiconducting layer and etched to form an aperture exposing the underlying conducting or semiconducting layer on the aperture floor. An ultra-thin nucleation layer is then deposited by physical vapor deposition onto the field of the dielectric layer. A CVD metal layer is then deposited onto the structure to achieve selective deposition on the floor of the aperture, while preferably also forming a highly oriented blanket layer on the field. The present apparatus and process reduce the number of steps necessary to fabricate CVD metal interconnects and layers that are substantially void-free and planarized. The metallization process is preferably carried out in an integrated processing system that includes both a PVD and CVD processing chamber so that once the substrate is introduced into a vacuum environment, the metallization of the apertures to form vias and contacts occurs without the formation of oxides between the layers.

    摘要翻译： 本发明一般涉及一种改进的装置和方法，用于在衬底上提供均匀的台阶覆盖和导电层的平坦化，以形成半微米，高纵横比孔径宽度应用和高度取向导电层的连续的无空隙互连。 在本发明的一个方面，电介质层形成在导电或半导体层之上，并被蚀刻以形成露出孔底板上下面的导电或半导体层的孔。 然后通过物理气相沉积将超薄成核层沉积到介电层的场上。 然后将CVD金属层沉积到结构上以实现孔的地板上的选择性沉积，同时优选地还在场上形成高度取向的覆盖层。 本装置和工艺减少了制造基本上无空隙和平坦化的CVD金属互连和层所需的步骤数量。 金属化处理优选在包括PVD和CVD处理室的一体化处理系统中进行，使得一旦将衬底引入真空环境中，孔的金属化形成通孔和接触，而不会在两者之间形成氧化物之间 层。

    Low temperature integrated metallization process and apparatus
    6.
    发明授权
    Low temperature integrated metallization process and apparatus 有权
    低温一体化金属化工艺及装置

    公开(公告)号：US06726776B1

    公开(公告)日：2004-04-27

    申请号：US09370599

    申请日：1999-08-09

    申请人： Roderick Craig Mosely ,  Hong Zhang ,  Fusen Chen ,  Ted Guo

    发明人： Roderick Craig Mosely ,  Hong Zhang ,  Fusen Chen ,  Ted Guo

    IPC分类号： C23C1600

    CPC分类号： H01L21/76843 ,  H01L21/76876 ,  H01L21/76877 ,  Y10S414/139

    摘要： The present invention relates generally to an improved process for providing uniform step coverage on a substrate and planarization of metal layers to form continuous, void-free contacts or vias in sub-half micron applications. In one aspect of the invention, a refractory layer is deposited onto a substrate having high aspect ratio contacts or vias formed thereon. A CVD metal layer is then deposited onto the refractory layer at low temperatures to provide a conformal wetting layer for a PVD metal. Next, a PVD metal is deposited onto the previously formed CVD metal layer at a temperature below that of the melting point temperature of the metal. The resulting CVD/PVD metal layer is substantially void-free. The metallization process is preferably carried out in an integrated processing system that includes both a PVD and CVD processing chamber so that once the substrate is introduced into a vacuum environment, the metallization of the vias and contacts occurs without the formation of an oxide layer over the CVD Al layer.

    摘要翻译： 本发明一般涉及在衬底上提供均匀的台阶覆盖和金属层的平坦化以在半微米应用中形成连续的无空隙接触或通孔的改进方法。 在本发明的一个方面中，将耐火层沉积在具有高比例接触或在其上形成的通孔的基底上。 然后在低温下将CVD金属层沉积到耐火层上，以提供用于PVD金属的保形润湿层。 接下来，在低于金属的熔点温度的温度下，将PVD金属沉积在预先形成的CVD金属层上。 所得到的CVD / PVD金属层基本上无空隙。 金属化处理优选在包括PVD和CVD处理室的一体化处理系统中进行，使得一旦将衬底引入真空环境中，就会发生通孔和触点的金属化，而不会在其上形成氧化物层 CVD Al层。

    Fully planarized dual damascene metallization using copper line interconnect and selective CVD aluminum plug
    7.
    发明授权
    Fully planarized dual damascene metallization using copper line interconnect and selective CVD aluminum plug 失效
    使用铜线互连和选择性CVD铝插头的全平面化双镶嵌金属化

    公开(公告)号：US06537905B1

    公开(公告)日：2003-03-25

    申请号：US08778205

    申请日：1996-12-30

    申请人： Liang-Yuh Chen ,  Ted Guo ,  Roderick Craig Mosley ,  Fusen Chen

    发明人： Liang-Yuh Chen ,  Ted Guo ,  Roderick Craig Mosley ,  Fusen Chen

    IPC分类号： H01L214763

    CPC分类号： H01L21/28562 ,  H01L21/76879

    摘要： The present invention generally provides a metallization process for forming a highly integrated interconnect. More particularly, the present invention provides a dual damascene interconnect module that incorporates selective chemical vapor deposition aluminum (CVD Al) via fill with a metal wire, preferably copper, formed within a barrier layer. The invention provides the advantages of having copper wires with lower resistivity (greater conductivity) and greater electromigration resistance than aluminum, a barrier layer between the copper wire and the surrounding dielectric material, void-free, sub-half micron selective CVD Al via plugs, and a reduced number of process steps to achieve such integration.

    摘要翻译： 本发明通常提供用于形成高度集成的互连件的金属化工艺。 更具体地，本发明提供了一种双镶嵌互连模块，其通过填充形成在阻挡层内的金属线，优选铜，并入选择性化学气相沉积铝（CVD Al）。 本发明提供了具有比铝更低的电阻率（更大的导电性）和更大的电迁移电阻的铜线，铜线和周围介电材料之间的阻挡层，无空隙的半微米选择性CVD Al通过插塞的优点， 并减少了实现这种集成的流程步骤。

    Low temperature integrated via and trench fill process and apparatus
    8.
    发明授权
    Low temperature integrated via and trench fill process and apparatus 失效
    低温集成通孔和沟槽填充工艺和设备

    公开(公告)号：US6139697A

    公开(公告)日：2000-10-31

    申请号：US792292

    申请日：1997-01-31

    申请人： Liang-Yuh Chen ,  Roderick Craig Mosely ,  Fusen Chen ,  Rong Tao ,  Ted Guo

    发明人： Liang-Yuh Chen ,  Roderick Craig Mosely ,  Fusen Chen ,  Rong Tao ,  Ted Guo

    IPC分类号： H01L21/285 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/52 ,  C23C14/34

    CPC分类号： H01L21/76877

    摘要： The present invention relates generally to an improved process for providing complete via fill on a substrate and planarization of metal layers to form continuous, void-free contacts or vias in sub-half micron applications. In one aspect of the invention, a refractory layer is deposited onto a substrate having high aspect ratio contacts or vias formed thereon. A CVD metal layer, such as CVD Al or CVD Cu, is then deposited onto the refractory layer at low temperatures to provide a conformal wetting layer for a PVD Cu. Next, a PVD Cu is deposited onto the previously formed CVD Cu layer at a temperature below that of the melting point temperature of the metal. The resulting CVD/PVD Cu layer is substantially void-free. The metallization process is preferably carried out in an integrated processing system that includes both a PVD and CVD processing chamber so that once the substrate is introduced into a vacuum environment, the metallization of the vias and contacts occurs without the formation of an oxide layer over the CVD Cu layer. The via fill process of the present invention is also successful with air-exposure between the CVD Cu and PVD Cu steps.

    摘要翻译： 本发明一般涉及在衬底上提供完整的通孔填充物和金属层的平坦化以在半微米应用中形成连续的无空隙触点或通孔的改进方法。 在本发明的一个方面中，将耐火层沉积在具有高比例接触或在其上形成的通孔的基底上。 然后将CVD金属层（例如CVD Al或CVD Cu）在低温下沉积到耐火层上，以提供用于PVD Cu的保形润湿层。 接下来，在低于金属的熔点温度的温度下，将PVD Cu沉积在先前形成的CVD Cu层上。 所得到的CVD / PVD ​​Cu层基本上无空隙。 金属化处理优选在包括PVD和CVD处理室的一体化处理系统中进行，使得一旦将衬底引入真空环境中，就会发生通孔和触点的金属化，而不会在其上形成氧化物层 CVD Cu层。 本发明的通孔填充方法也可以在CVD Cu和PVD Cu步骤之间的空气曝光成功。

    Low temperature integrated metallization process and apparatus
    9.
    发明授权
    Low temperature integrated metallization process and apparatus 失效

    公开(公告)号：US06743714B2

    公开(公告)日：2004-06-01

    申请号：US10074938

    申请日：2002-02-11

    申请人： Roderick Craig Mosely ,  Hong Zhang ,  Fusen Chen ,  Ted Guo ,  Liang-Yuh Chen

    发明人： Roderick Craig Mosely ,  Hong Zhang ,  Fusen Chen ,  Ted Guo ,  Liang-Yuh Chen

    IPC分类号： H01L2144

    CPC分类号： H01L21/76876 ,  C23C14/568 ,  C23C16/54 ,  H01L21/32051 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/76879

    摘要： The present invention relates generally to an improved process for providing uniform step coverage on a substrate and planarization of metal layers to form continuous, void-free contacts or vias in sub-half micron applications. In one aspect of the invention, a refractory layer is deposited onto a substrate having high aspect ratio contacts or vias formed thereon. A CVD metal layer is then deposited onto the refractory layer at low temperatures to provide a conformal wetting layer for a PVD metal. Next, a PVD metal is deposited onto the previously formed CVD metal layer at a temperature below that of the melting point temperature of the metal. The resulting CVD/PVD metal layer is substantially void-free. The metallization process is preferably carried out in an integrated processing system that includes both a PVD and CVD processing chamber so that once the substrate is introduced into a vacuum environment, the metallization of the vias and contacts occurs without the formation of an oxide layer over the CVD Al layer.