公开(公告)号：US08924175B2

公开(公告)日：2014-12-30

申请号：US13862035

申请日：2013-04-12

Applicant: Tektronix, Inc.

Inventor： Patrick A. Smith ,  David L. Kelly ,  Que T. Tran ,  Shane A. Hazzard

IPC: G01R13/02 ,  G01R31/02 ,  G06F19/00

CPC classification number: G06F19/00 ,  G01R13/02 ,  G01R13/0254 ,  G01R31/02

Abstract: A test and measurement apparatus, system, and method for synchronizing an acquisition or triggering system to a specific burst of interest. The subject apparatus and method triggers on varying energy content of a signal qualified by time in the presence of high-frequency input signal bursts, by using an adjustable pulse width envelope detector, disposed in the signal path of the trigger circuitry, as a digital rectifier or to otherwise process and extract an envelope signal. An RF envelope probe having an analog envelope detector among other suitable components is disclosed. A method is implemented for isolating an interval of interest in a signal under test. An envelope detector circuit produces an envelope signal from the signal. Trigger circuitry receives the envelope signal from the envelope detector, and isolates the interval of interesting in the signal under test using the envelope signal.

Abstract translation: 一种用于将采集或触发系统同步到感兴趣的特定突发的测试和测量装置，系统和方法。 主题装置和方法通过使用设置在触发电路的信号路径中的可调脉冲宽度包络检测器作为数字整流器来触发在存在高频输入信号脉冲串的情况下由时间限定的信号的变化的能量含量 或以其他方式处理和提取包络信号。 公开了一种具有模拟包络检测器的RF包络探测器以及其它合适的部件。 实施用于隔离被测信号中的感兴趣间隔的方法。 包络检测器电路从信号产生包络信号。 触发电路从包络检测器接收包络信号，并使用包络信号隔离被测信号中有趣的间隔。

公开(公告)号：US20200249275A1

公开(公告)日：2020-08-06

申请号：US16778262

申请日：2020-01-31

Applicant: Tektronix, Inc.

Inventor： Daniel S. Froelich ,  Shane A. Hazzard ,  Sarah R. Boen ,  Jed H. Andrews

IPC: G01R31/317 ,  G06F13/40

Abstract: Systems, devices and methods for high-speed I/O margin testing can screen high volumes of pre-production and production parts and identify cases where the electrical characteristics have changed enough to impact operation. The margin tester disclosed is lower cost, easier to use and faster than traditional BERT and scopes and can operate on the full multi-lane I/O links in their standard operating states with full loading and cross-talk. The margin tester assesses the electrical receiver margin of an operation multi-lane high speed I/O link of a device under test simultaneously in either or both directions. In a technology-specific form, an embodiment of the margin tester can be implemented as an add-in card margin tester to test motherboard slots of a mother board under test, or as a as a motherboard with slots to test add-in cards.

公开(公告)号：US09934355B2

公开(公告)日：2018-04-03

申请号：US13861998

申请日：2013-04-12

Applicant: Tektronix, Inc.

Inventor： Patrick A. Smith ,  David L. Kelly ,  Que T. Tran ,  Shane A. Hazzard

IPC: G01R13/02 ,  G06F19/00 ,  G01R31/02

CPC classification number: G06F19/00 ,  G01R13/02 ,  G01R13/0254 ,  G01R31/02

Abstract: A test and measurement apparatus, system, and method for synchronizing an acquisition or triggering system to a specific burst of interest. The subject apparatus and method triggers on varying energy content of a signal qualified by time in the presence of high-frequency input signal bursts, by using an adjustable pulse width envelope detector, disposed in the signal path of the trigger circuitry, as a digital rectifier or to otherwise process and extract an envelope signal. An RF envelope probe having an analog envelope detector among other suitable components is disclosed. A method is implemented for isolating an interval of interest in a signal under test. An envelope detector circuit produces an envelope signal from the signal. Trigger circuitry receives the envelope signal from the envelope detector, and isolates the interval of interesting in the signal under test using the envelope signal.

公开(公告)号：US20240159797A1

公开(公告)日：2024-05-16

申请号：US18511977

申请日：2023-11-16

Applicant: Tektronix, Inc.

Inventor： Daniel G. Knierim ,  Shane A. Hazzard ,  Scott T. Harrison ,  Timothy E. Bieber

IPC: G01R1/20

CPC classification number: G01R1/20 ,  G02B6/12

Abstract: A test and measurement system includes one or more remote heads, each of the one or more remote heads configured to be coupled to a respective device under test (DUT) to receive an electrical test signal from the DUT and each of the one or more remote heads including an electrical-to-optical (EOM) configured to convert the received electrical test signal into an optical test signal. Optical interconnection circuitry receives the optical test signal from the EOM of the one or more remote heads and, in response to control signals, selects one of the optical test signals to be provided to a test and measurement system. The optical interconnection circuitry further converts the selected optical test signal into an electrical test signal to be supplied to a test port of the test and measurement instrument. Methods are also described.

公开(公告)号：US20220390513A1

公开(公告)日：2022-12-08

申请号：US17832535

申请日：2022-06-03

Applicant: Tektronix, Inc.

Inventor： Shane A. Hazzard ,  Ajaiey Kumar Sharma ,  Timothy E. Bieber ,  John Marrinan ,  Andrew McCann ,  Pieter Christiaan Seidel ,  Josiah A. Bartlett

IPC: G01R31/317

Abstract: An input selector for electrically connecting one of a plurality of test signals from a device under test to a test and measurement instrument includes a multiplexer having multiple inputs, each of the multiple inputs coupled to a different one of the plurality of test signals from the device under test, and having an output of a selected one of the multiple inputs, and an amplifier coupled to the output of the multiplexer for amplifying the selected test signal of the device under test before being sent as an output of the input selector to the test and measurement instrument. In alternative architectures, two or more amplifiers are coupled to the plurality of test signals, and the multiplexer selects an output of one of the two amplifiers to pass to a measurement instrument for testing.

公开(公告)号：US20200250368A1

公开(公告)日：2020-08-06

申请号：US16778249

申请日：2020-01-31

Applicant: Tektronix, Inc.

Inventor： Daniel S. Froelich ,  Shane A. Hazzard ,  Sarah R. Boen ,  Jed H. Andrews

IPC: G06F30/398 ,  G06F13/42 ,  G06F13/20 ,  G06F115/12

Abstract: Systems, devices and methods for high-speed I/O margin testing can screen high volumes of pre-production and production parts and identify cases where the electrical characteristics have changed enough to impact operation. The margin tester disclosed is lower cost, easier to use and faster than traditional BERT and scopes and can operate on the full multi-lane I/O links in their standard operating states with full loading and cross-talk. The margin tester assesses the electrical receiver margin of an operation multi-lane high speed I/O link of a device under test simultaneously in either or both directions. In a technology-specific form, an embodiment of the margin tester can be implemented as an add-in card margin tester to test motherboard slots of a mother board under test, or as a as a motherboard with slots to test add-in cards.

公开(公告)号：US20130231883A1

公开(公告)日：2013-09-05

申请号：US13861998

申请日：2013-04-12

Applicant: TEKTRONIX, INC.

Inventor： Patrick A. Smith ,  David L. Kelly ,  Que T. Tran ,  Shane A. Hazzard

IPC: G06F19/00 ,  G01R13/02

CPC classification number: G06F19/00 ,  G01R13/02 ,  G01R13/0254 ,  G01R31/02

Abstract: A test and measurement apparatus, system, and method for synchronizing an acquisition or triggering system to a specific burst of interest. The subject apparatus and method triggers on varying energy content of a signal qualified by time in the presence of high-frequency input signal bursts, by using an adjustable pulse width envelope detector, disposed in the signal path of the trigger circuitry, as a digital rectifier or to otherwise process and extract an envelope signal. An RF envelope probe having an analog envelope detector among other suitable components is disclosed. A method is implemented for isolating an interval of interest in a signal under test. An envelope detector circuit produces an envelope signal from the signal. Trigger circuitry receives the envelope signal from the envelope detector, and isolates the interval of interesting in the signal under test using the envelope signal.

Abstract translation: 一种用于将采集或触发系统同步到感兴趣的特定突发的测试和测量装置，系统和方法。 主题装置和方法通过使用设置在触发电路的信号路径中的可调脉冲宽度包络检测器作为数字整流器来触发在存在高频输入信号脉冲串的情况下由时间限定的信号的变化的能量含量 或以其他方式处理和提取包络信号。 公开了一种具有模拟包络检测器的RF包络探测器以及其它合适的部件。 实施用于隔离被测信号中的感兴趣间隔的方法。 包络检测器电路从信号产生包络信号。 触发电路从包络检测器接收包络信号，并使用包络信号隔离被测信号中有趣的间隔。

公开(公告)号：US12117486B2

公开(公告)日：2024-10-15

申请号：US16778262

申请日：2020-01-31

Applicant: Tektronix, Inc.

Inventor： Daniel S. Froelich ,  Shane A. Hazzard ,  Sarah R. Boen ,  Jed H. Andrews

IPC: G01R31/317 ,  G06F13/20 ,  G06F13/40 ,  G06F13/42 ,  G06F30/398 ,  G06F115/12

CPC classification number: G01R31/31715 ,  G06F13/20 ,  G06F13/4068 ,  G06F13/4282 ,  G06F30/398 ,  G06F2115/12 ,  G06F2213/0026

Abstract: Systems, devices and methods for high-speed I/O margin testing can screen high volumes of pre-production and production parts and identify cases where the electrical characteristics have changed enough to impact operation. The margin tester disclosed is lower cost, easier to use and faster than traditional BERT and scopes and can operate on the full multi-lane I/O links in their standard operating states with full loading and cross-talk. The margin tester assesses the electrical receiver margin of an operation multi-lane high speed I/O link of a device under test simultaneously in either or both directions. In a technology-specific form, an embodiment of the margin tester can be implemented as an add-in card margin tester to test motherboard slots of a mother board under test, or as a as a motherboard with slots to test add-in cards.

公开(公告)号：US11946970B2

公开(公告)日：2024-04-02

申请号：US16778249

申请日：2020-01-31

Applicant: Tektronix, Inc.

Inventor： Daniel S. Froelich ,  Shane A. Hazzard ,  Sarah R. Boen ,  Jed H. Andrews

IPC: G01R31/317 ,  G06F11/273 ,  G06F13/20 ,  G06F13/40 ,  G06F13/42 ,  G06F30/398 ,  H04L43/50 ,  G06F115/12

CPC classification number: G01R31/31715 ,  G06F13/20 ,  G06F13/4068 ,  G06F13/4282 ,  G06F30/398 ,  G06F2115/12 ,  G06F2213/0026

Abstract: Systems, devices and methods for high-speed I/O margin testing can screen high volumes of pre-production and production parts and identify cases where the electrical characteristics have changed enough to impact operation. The margin tester disclosed is lower cost, easier to use and faster than traditional BERT and scopes and can operate on the full multi-lane I/O links in their standard operating states with full loading and cross-talk. The margin tester assesses the electrical receiver margin of an operation multi-lane high speed I/O link of a device under test simultaneously in either or both directions. In a technology-specific form, an embodiment of the margin tester can be implemented as an add-in card margin tester to test motherboard slots of a mother board under test, or as a as a motherboard with slots to test add-in cards.

公开(公告)号：US20220034967A1

公开(公告)日：2022-02-03

申请号：US17375451

申请日：2021-07-14

Applicant: Tektronix, Inc.

Inventor： Sam J. Strickling ,  Daniel S. Froelich ,  Michelle L. Baldwin ,  Jonathan San ,  Lin-Yung Chen ,  Shane A. Hazzard

IPC: G01R31/319 ,  G01R31/3185

Abstract: A calibrated test and measurement cable for connecting one or more devices under test and a test and measurement instrument, including a first port structured to electrically connect to a first signal lane, a second port structured to electrically connect to a second signal lane, a third port structured to electrically connect to a test and measurement instrument, and a multiplexer configured to switch between electrically connecting the first port to the third port and connected the second port to the third port. The first and second signal lanes can be included on the same device under test or different devices under test. An input can receive instructions to operate the multiplexer.