公开(公告)号：US08536646B2

公开(公告)日：2013-09-17

申请号：US13237940

申请日：2011-09-21

申请人： Teng-Hao Yeh ,  Shian-Hau Liao ,  Chia-Hui Chen ,  Sung-Shan Tai

发明人： Teng-Hao Yeh ,  Shian-Hau Liao ,  Chia-Hui Chen ,  Sung-Shan Tai

IPC分类号： H01L29/66

CPC分类号： H01L29/7813 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7811

摘要： The present invention provides a trench type power transistor device including a semiconductor substrate, at least one transistor cell, a gate metal layer, a source metal layer, and a second gate conductive layer. The semiconductor substrate has at least one trench. The transistor cell includes a first gate conductive layer disposed in the trench. The gate metal layer and the source metal layer are disposed on the semiconductor substrate. The second gate conductive layer is disposed between the first gate conductive layer and the source metal layer. The second gate conductive layer electrically connects the first gate conductive layer to the gate metal layer, and the second gate conductive layer is electrically insulated from the source metal layer and the semiconductor substrate.

摘要翻译： 本发明提供了包括半导体衬底，至少一个晶体管单元，栅极金属层，源极金属层和第二栅极导电层的沟槽型功率晶体管器件。 半导体衬底具有至少一个沟槽。 晶体管单元包括设置在沟槽中的第一栅极导电层。 栅极金属层和源极金属层设置在半导体衬底上。 第二栅极导电层设置在第一栅极导电层和源极金属层之间。 第二栅极导电层将第一栅极导电层电连接到栅极金属层，并且第二栅极导电层与源极金属层和半导体衬底电绝缘。

公开(公告)号：US20130069143A1

公开(公告)日：2013-03-21

申请号：US13237940

申请日：2011-09-21

申请人： Teng-Hao Yeh ,  Shian-Hau Liao ,  Chia-Hui Chen ,  SUNG-SHAN TAI

发明人： Teng-Hao Yeh ,  Shian-Hau Liao ,  Chia-Hui Chen ,  SUNG-SHAN TAI

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7813 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7811

摘要： The present invention provides a trench type power transistor device including a semiconductor substrate, at least one transistor cell, a gate metal layer, a source metal layer, and a second gate conductive layer. The semiconductor substrate has at least one trench. The transistor cell includes a first gate conductive layer disposed in the trench. The gate metal layer and the source metal layer are disposed on the semiconductor substrate. The second gate conductive layer is disposed between the first gate conductive layer and the source metal layer. The second gate conductive layer electrically connects the first gate conductive layer to the gate metal layer, and the second gate conductive layer is electrically insulated from the source metal layer and the semiconductor substrate.

摘要翻译： 本发明提供了包括半导体衬底，至少一个晶体管单元，栅极金属层，源极金属层和第二栅极导电层的沟槽型功率晶体管器件。 半导体衬底具有至少一个沟槽。 晶体管单元包括设置在沟槽中的第一栅极导电层。 栅极金属层和源极金属层设置在半导体衬底上。 第二栅极导电层设置在第一栅极导电层和源极金属层之间。 第二栅极导电层将第一栅极导电层电连接到栅极金属层，并且第二栅极导电层与源极金属层和半导体衬底电绝缘。

公开(公告)号：US09196315B2

公开(公告)日：2015-11-24

申请号：US13681133

申请日：2012-11-19

申请人： Teng-Hao Yeh ,  Yen-Hao Shih ,  Yan-Ru Chen

发明人： Teng-Hao Yeh ,  Yen-Hao Shih ,  Yan-Ru Chen

IPC分类号： G11C11/34 ,  G11C5/06 ,  H01L21/28 ,  H01L29/792 ,  H01L27/115 ,  G11C16/04

CPC分类号： G11C5/06 ,  G11C5/063 ,  G11C16/0483 ,  G11C2213/71 ,  H01L21/28282 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/7926

摘要： A device on an integrated circuit includes a stack of alternating semiconductor lines and insulating lines, and a gate structure over the stack of semiconductor lines. The gate structure includes a vertical portion adjacent the stack on the at least one side, and horizontal extension portions between the semiconductor lines. Sides of the insulating lines can be recessed relative to sides of the semiconductor lines, so at least one side of the stack includes recesses between semiconductor lines. The horizontal extension portions can be in the recesses. The horizontal extension portions have inside surfaces adjacent the sides of the insulating lines, and outside surfaces that can be flush with the sides of the semiconductor lines. The device may include a second gate structure spaced away from the first mentioned gate structure, and an insulating element between horizontal extension portions of the second gate structure and the first mentioned gate structure.

摘要翻译： 集成电路中的器件包括交替的半导体线路和绝缘线路的堆叠以及在半导体线路堆叠上的栅极结构。 栅极结构包括在至少一个侧面上与堆叠相邻的垂直部分和半导体线之间的水平延伸部分。 绝缘线的边可以相对于半导体线的侧面凹陷，因此堆叠的至少一侧包括半导体线之间的凹槽。 水平延伸部分可以在凹槽中。 水平延伸部具有与绝缘线的侧面相邻的内表面以及可与半导体线的侧面齐平的外表面。 器件可以包括与第一提到的栅极结构间隔开的第二栅极结构，以及在第二栅极结构的水平延伸部分和第一个提到的栅极结构之间的绝缘元件。

公开(公告)号：US20140021628A1

公开(公告)日：2014-01-23

申请号：US13607555

申请日：2012-09-07

申请人： Yen-Hao Shih ,  Shih-Hung Chen ,  Teng-Hao Yeh ,  Chih-Wei Hu ,  Feng-Nien Tsai ,  Lo-Yueh Lin

发明人： Yen-Hao Shih ,  Shih-Hung Chen ,  Teng-Hao Yeh ,  Chih-Wei Hu ,  Feng-Nien Tsai ,  Lo-Yueh Lin

IPC分类号： H01L21/768 ,  H01L23/48

CPC分类号： H01L23/5226 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/32137 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76831 ,  H01L23/53271 ,  H01L23/5329 ,  H01L27/11526 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method is used with an IC device including a stack of dielectric/conductive layers to form interlayer connectors extending from a surface of the device to the conductive layers. Contact openings are created through a dielectric layer to a first conductive layer. N etch masks, with 2N−1 being less than W, 2N being greater than or equal to W, have spaced apart open etch regions and mask regions elsewhere. The stack of layers are etched only through W−1 contact openings to create extended contact openings extending to W−1 conductive layers; 2n−1 conductive layers are etched for up to half of the contact openings for each etch mask n=1, 2 . . . N. The contact openings are etched with different combinations of the etch masks' open etch regions. Interlayer connectors are formed in the contact openings.

摘要翻译： 一种使用IC器件的方法包括一叠介电/导电层，以形成从器件表面延伸到导电层的层间连接器。 通过电介质层产生接触开口到第一导电层。 N型蚀刻掩模，其中2N-1小于W，2N大于或等于W，其间具有间隔开的开放蚀刻区域和掩模区域。 层叠层仅通过W-1接触开口蚀刻以产生延伸到W-1导电层的延伸的接触开口; 对于每个蚀刻掩模n = 1,2，2n-1个导电层被蚀刻用于多达一半的接触开口。 。 。 用蚀刻掩模的开放蚀刻区域的不同组合蚀刻接触开口。 中间层连接器形成在接触开口中。

公开(公告)号：US08633099B1

公开(公告)日：2014-01-21

申请号：US13607555

申请日：2012-09-07

申请人： Yen-Hao Shih ,  Shih-Hung Chen ,  Teng-Hao Yeh ,  Chih-Wei Hu ,  Feng-Nien Tsai ,  Lo-Yueh Lin

发明人： Yen-Hao Shih ,  Shih-Hung Chen ,  Teng-Hao Yeh ,  Chih-Wei Hu ,  Feng-Nien Tsai ,  Lo-Yueh Lin

IPC分类号： H01L21/44 ,  H01L21/4763 ,  H01L23/48 ,  H01L29/40

CPC分类号： H01L23/5226 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/32137 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76831 ,  H01L23/53271 ,  H01L23/5329 ,  H01L27/11526 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method is used with an IC device including a stack of dielectric/conductive layers to form interlayer connectors extending from a surface of the device to the conductive layers. Contact openings are created through a dielectric layer to a first conductive layer. N etch masks, with 2N−1 being less than W, 2N being greater than or equal to W, have spaced apart open etch regions and mask regions elsewhere. The stack of layers are etched only through W−1 contact openings to create extended contact openings extending to W−1 conductive layers; 2n−1 conductive layers are etched for up to half of the contact openings for each etch mask n=1, 2 . . . N. The contact openings are etched with different combinations of the etch masks' open etch regions. Interlayer connectors are formed in the contact openings.

摘要翻译： 一种使用IC器件的方法包括一叠介电/导电层，以形成从器件表面延伸到导电层的层间连接。 通过电介质层产生接触开口到第一导电层。 N型蚀刻掩模，其中2N-1小于W，2N大于或等于W，其间具有间隔开的开放蚀刻区域和掩模区域。 层叠层仅通过W-1接触开口蚀刻以产生延伸到W-1导电层的延伸的接触开口; 对于每个蚀刻掩模n = 1,2，2n-1个导电层被蚀刻用于多达一半的接触开口。 。 。 用蚀刻掩模的开放蚀刻区域的不同组合蚀刻接触开口。 中间层连接器形成在接触开口中。

公开(公告)号：US20110255350A1

公开(公告)日：2011-10-20

申请号：US12835075

申请日：2010-07-13

申请人： Yu-Fon Huang ,  Teng-Hao Yeh ,  Miao-Chih Hsu ,  Tzung-Ting Han

发明人： Yu-Fon Huang ,  Teng-Hao Yeh ,  Miao-Chih Hsu ,  Tzung-Ting Han

IPC分类号： G11C16/04

CPC分类号： H01L29/7923 ,  G11C11/5621 ,  G11C16/0458 ,  H01L29/66833

摘要： A method of operating a memory cell is provided. The memory cell has first, second, third and fourth storage regions in a charge-storage layer between a substrate and a word line. The first and second storage regions are respectively adjacent to lower and upper portions at one side of the protruding part of the substrate, and the third and fourth storage regions are respectively adjacent to lower and upper portions at the other side of the same. The second and third storage regions are regarded as a top storage region. When the top storage region is programmed, a first positive voltage is applied to the word line, a second positive voltage is applied to a top bit line in a top portion of the protruding part, and a bottom voltage is applied to first and second bottom bit lines in the substrate beside the protruding part respectively.

摘要翻译： 提供了一种操作存储单元的方法。 存储单元在基板和字线之间的电荷存储层中具有第一，第二，第三和第四存储区域。 第一和第二存储区分别与衬底的突出部分的一侧的下部和上部相邻，并且第三和第四存储区分别在其另一侧的下部和上部相邻。 第二和第三存储区域被认为是顶部存储区域。 当顶部存储区域被编程时，第一正电压被施加到字线，第二正电压被施加到突出部分的顶部中的顶位线，并且底电压被施加到第一和第二底部 位于突出部分旁边的基板中的位线。

公开(公告)号：US20140140131A1

公开(公告)日：2014-05-22

申请号：US13681133

申请日：2012-11-19

申请人： Teng-Hao Yeh ,  Yen-Hao Shih ,  Yan-Ru Chen

发明人： Teng-Hao Yeh ,  Yen-Hao Shih ,  Yan-Ru Chen

IPC分类号： H01L29/788 ,  G11C5/06 ,  G11C16/04 ,  H01L21/28

CPC分类号： G11C5/06 ,  G11C5/063 ,  G11C16/0483 ,  G11C2213/71 ,  H01L21/28282 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/7926

摘要： A device on an integrated circuit includes a stack of alternating semiconductor lines and insulating lines, and a gate structure over the stack of semiconductor lines. The gate structure includes a vertical portion adjacent the stack on the at least one side, and horizontal extension portions between the semiconductor lines. Sides of the insulating lines can be recessed relative to sides of the semiconductor lines, so at least one side of the stack includes recesses between semiconductor lines. The horizontal extension portions can be in the recesses. The horizontal extension portions have inside surfaces adjacent the sides of the insulating lines, and outside surfaces that can be flush with the sides of the semiconductor lines. The device may include a second gate structure spaced away from the first mentioned gate structure, and an insulating element between horizontal extension portions of the second gate structure and the first mentioned gate structure.

摘要翻译： 集成电路中的器件包括交替的半导体线路和绝缘线路的堆叠以及在半导体线路堆叠上的栅极结构。 栅极结构包括在至少一个侧面上与堆叠相邻的垂直部分和半导体线之间的水平延伸部分。 绝缘线的边可以相对于半导体线的侧面凹陷，因此堆叠的至少一侧包括半导体线之间的凹槽。 水平延伸部分可以在凹槽中。 水平延伸部具有与绝缘线的侧面相邻的内表面以及可与半导体线的侧面齐平的外表面。 器件可以包括与第一提到的栅极结构间隔开的第二栅极结构，以及在第二栅极结构的水平延伸部分和第一个提到的栅极结构之间的绝缘元件。

公开(公告)号：US08391063B2

公开(公告)日：2013-03-05

申请号：US12835075

申请日：2010-07-13

申请人： Yu-Fong Huang ,  Teng-Hao Yeh ,  Miao-Chih Hsu ,  Tzung-Ting Han

发明人： Yu-Fong Huang ,  Teng-Hao Yeh ,  Miao-Chih Hsu ,  Tzung-Ting Han

IPC分类号： G11C11/34

CPC分类号： H01L29/7923 ,  G11C11/5621 ,  G11C16/0458 ,  H01L29/66833

摘要： A method of operating a memory cell is provided. The memory cell has first, second, third and fourth storage regions in a charge-storage layer between a substrate and a word line. The first and second storage regions are respectively adjacent to lower and upper portions at one side of the protruding part of the substrate, and the third and fourth storage regions are respectively adjacent to lower and upper portions at the other side of the same. The second and third storage regions are regarded as a top storage region. When the top storage region is programmed, a first positive voltage is applied to the word line, a second positive voltage is applied to a top bit line in a top portion of the protruding part, and a bottom voltage is applied to first and second bottom bit lines in the substrate beside the protruding part respectively.

摘要翻译： 提供了一种操作存储单元的方法。 存储单元在基板和字线之间的电荷存储层中具有第一，第二，第三和第四存储区域。 第一和第二存储区分别与衬底的突出部分的一侧的下部和上部相邻，并且第三和第四存储区分别在其另一侧的下部和上部相邻。 第二和第三存储区域被认为是顶部存储区域。 当顶部存储区域被编程时，第一正电压被施加到字线，第二正电压被施加到突出部分的顶部中的顶位线，并且底电压被施加到第一和第二底部 位于突出部分旁边的基板中的位线。

公开(公告)号：US09082657B2

公开(公告)日：2015-07-14

申请号：US13676672

申请日：2012-11-14

申请人： Chih-Wei Hu ,  Teng-Hao Yeh ,  Yen-Hao Shih

发明人： Chih-Wei Hu ,  Teng-Hao Yeh ,  Yen-Hao Shih

IPC分类号： H01L21/3205 ,  H01L27/115

CPC分类号： H01L27/11578 ,  H01L21/28575 ,  H01L27/11565 ,  H01L29/0891 ,  H01L29/2003 ,  H01L29/42316 ,  H01L29/42376 ,  H01L29/452 ,  H01L29/66462 ,  H01L29/7787

摘要： A semiconductor structure and a method for manufacturing the same are provided. The method comprises following steps. Semiconductor units are arranged on a substrate. A material layer is formed on the semiconductor units. A first patterned mask layer is formed on the semiconductor units. The first patterned mask layer has a mask opening corresponding to a portion of the semiconductor units and exposing the material layer. A portion of the material layer exposed by the mask opening is removed to remain a portion of the material layer on a sidewall of each of the semiconductor units exposed by the mask opening to form spacer structures.

摘要翻译： 提供半导体结构及其制造方法。 该方法包括以下步骤。 半导体单元布置在基板上。 在半导体单元上形成材料层。 在半导体单元上形成第一图案化掩模层。 第一图案化掩模层具有对应于半导体单元的一部分并且暴露材料层的掩模开口。 去除由掩模开口暴露的材料层的一部分，以保留由掩模开口暴露的每个半导体单元的侧壁上的材料层的一部分，以形成间隔结构。