公开(公告)号：US20050285106A1

公开(公告)日：2005-12-29

申请号：US11205522

申请日：2005-08-17

申请人： Terence Kane ,  Chung-Ping Eng ,  Brett Engel ,  Barry Ginsberg ,  Dermott MacPherson ,  John Petrus

发明人： Terence Kane ,  Chung-Ping Eng ,  Brett Engel ,  Barry Ginsberg ,  Dermott MacPherson ,  John Petrus

IPC分类号： G01N21/68 ,  H01L21/00 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/302 ,  H01L21/461 ,  H01L21/4763 ,  H01L23/58 ,  H01L29/10

CPC分类号： H01L21/67253 ,  G01N21/68 ,  H01J37/32009 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31127 ,  H01L21/31138 ,  H01L21/32131 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods of etching a semiconductor structure using ion milling with a variable-position endpoint detector to unlayer multiple interconnect layers, including low-k dielectric films. The ion milling process is controlled for each material type to maintain a planar surface with minimal damage to the exposed materials. In so doing, an ion beam mills a first layer and detects an endpoint thereof using an optical detector positioned within the ion beam adjacent the first layer to expose a second layer of low-k dielectric film. Once the low-k dielectric film is exposed, a portion of the low-k dielectric film may be removed to provide spaces therein, which are backfilled with a material and polished to remove the backfill material and a layer of the multiple interconnect metal layers. Still further, the exposed low-k dielectric film may then be removed, and the exposed metal vias polished.

摘要翻译： 使用可变位置端点检测器使用离子铣削蚀刻半导体结构以使多层互连层（包括低k介电膜）层叠的方法。 对于每种材料类型来控制离子研磨工艺以保持平坦表面，同时对暴露的材料具有最小的损伤。 这样做，离子束研磨第一层并使用位于邻近第一层的离子束内的光学检测器来检测其端点，以暴露第二层低k电介质膜。 一旦露出低k电介质膜，可以去除低k电介质膜的一部分以在其中提供空间，其中填充有材料并被抛光以去除回填材料和多个互连金属层的层。 此外，然后可以去除暴露的低k电介质膜，并且暴露的金属通孔被抛光。

公开(公告)号：US20060030160A1

公开(公告)日：2006-02-09

申请号：US11242719

申请日：2005-10-03

申请人： Terence Kane ,  Darrell Miles ,  John Sylvestri ,  Michael Tenney

发明人： Terence Kane ,  Darrell Miles ,  John Sylvestri ,  Michael Tenney

IPC分类号： A61N5/00 ,  H01L21/302

CPC分类号： H01J37/32366 ,  G01N1/32 ,  G01R31/2898 ,  H01J2237/3114

摘要： A method and system for backside unlayering a semiconductor device to expose FEOL semiconductor features of the device for subsequent electrical and/or physical probing. A window is formed within a backside substrate layer of the semiconductor. A collimated ion plasma is generated and directed so as to contact the semiconductor only within the backside window via an opening in a focusing shield. This focused collimated ion plasma contacts the semiconductor, only within the window, while the semiconductor is simultaneously being rotated and tilted by a temperature controlled stage, for uniform removal of semiconductor layering such that the semiconductor features, in a location on the semiconductor corresponding to the backside window, are exposed. Backside unlayering of the invention may be enhanced by CAIBE processing.

摘要翻译： 一种用于背面非层叠半导体器件以暴露设备的FEOL半导体特征以用于随后的电和/或物理探测的方法和系统。 在半导体的背面基板层内形成窗口。 产生并引导准直离子等离子体，以便仅通过聚焦屏蔽件中的开口在后侧窗口内接触半导体。 这种聚焦的准直离子等离子体仅在窗口内接触半导体，同时半导体同时被温度控制的阶段旋转和倾斜，以均匀地去除半导体层，使得半导体特征在半导体上对应于 后视窗，曝光。 通过CAIBE处理可以增强本发明的背面未铺层。

公开(公告)号：US06887783B2

公开(公告)日：2005-05-03

申请号：US10650890

申请日：2003-08-28

申请人： Tze-Chiang Chen ,  Brett H. Engel ,  John A. Fitzsimmons ,  Terence Kane ,  Naftall E. Lustig ,  Ann McDonald ,  Vincent McGahay ,  Soon-Cheon Seo ,  Anthony K. Stamper ,  Yun Yu Wang ,  Erdem Kaltalioglu

发明人： Tze-Chiang Chen ,  Brett H. Engel ,  John A. Fitzsimmons ,  Terence Kane ,  Naftall E. Lustig ,  Ann McDonald ,  Vincent McGahay ,  Soon-Cheon Seo ,  Anthony K. Stamper ,  Yun Yu Wang ,  Erdem Kaltalioglu

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/44 ,  H01L21/4763

CPC分类号： H01L21/76834 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76832 ,  H01L23/5226 ,  H01L23/53228 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： An advanced back-end-of-line (BEOL) metallization structure is disclosed. The structure includes a bilayer diffusion barrier or cap, where the first cap layer is formed of a dielectric material preferably deposited by a high density plasma chemical vapor deposition (HDP CVD) process, and the second cap layer is formed of a dielectric material preferably deposited by a plasma-enhanced chemical vapor deposition (PE CVD) process. A method for forming the BEOL metallization structure is also disclosed. The invention is particularly useful in interconnect structures comprising low-k dielectric material for the inter-layer dielectric (ILD) and copper for the conductors.

摘要翻译： 公开了一种先进的后端（BEOL）金属化结构。 该结构包括双层扩散阻挡层或盖，其中第一覆盖层由优选通过高密度等离子体化学气相沉积（HDP CVD）工艺沉积的电介质材料形成，并且第二覆盖层由介电材料形成，优选沉积 通过等离子体增强化学气相沉积（PE CVD）工艺。 还公开了一种用于形成BEOL金属化结构的方法。 本发明在包括用于层间电介质（ILD）的低k电介质材料和用于导体的铜的互连结构中是特别有用的。

公开(公告)号：US06858530B2

公开(公告)日：2005-02-22

申请号：US10609789

申请日：2003-06-30

申请人： Terence Kane ,  Lawrence S. Fischer ,  Steven B. Herschbein ,  Ying Hong ,  Michael P. Tenney

发明人： Terence Kane ,  Lawrence S. Fischer ,  Steven B. Herschbein ,  Ying Hong ,  Michael P. Tenney

IPC分类号： G01R31/28 ,  H01L23/544 ,  H01L21/4763

CPC分类号： H01L22/34 ,  G01R31/2886 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method and structure for the electrical characterization of a semiconductor device comprising, first, forming a hole having a diameter less than 0.15 μm, wherein the hole is created using focused ion beam (FIB) etching, and through at least a protective cap layer formed over the device. The FIB etching occurs in an electron mode using a beam current less than 35 ρA with an aperture size less than 50 μm, and at an acceleration voltage of about 50 kV. Second, the surface of the hole is coated with a metal, preferably using chemical vapor deposition (CVD) and preferably using a FIB device. Third, a metal pad is deposited, preferably by FIB CVD, over the hole. Fourth, the pad is probed to determine characteristics and/or detect defects of the electrical device. The present invention allows for electrical characterization without causing damage to the device or its features.

摘要翻译： 一种用于半导体器件的电学表征的方法和结构，包括：首先形成直径小于0.15μm的孔，其中使用聚焦离子束（FIB）蚀刻产生孔，并且至少形成保护盖层 在设备上。 FIB蚀刻使用小于35rhoA的光束电流，孔径尺寸小于50um，并且在约50kV的加速电压下以电子模式发生。 第二，孔的表面涂覆金属，优选使用化学气相沉积（CVD），优选使用FIB器件。 第三，优选通过FIB CVD沉积金属焊盘。 第四，探测垫以确定电气设备的特性和/或检测缺陷。 本发明允许电特性而不会对设备或其特征造成损害。

公开(公告)号：US06914320B2

公开(公告)日：2005-07-05

申请号：US10807029

申请日：2004-03-23

申请人： Tze-Chiang Chen ,  Brett H. Engel ,  John A. Fitzsimmons ,  Terence Kane ,  Naftall E. Lustig ,  Ann McDonald ,  Vincent McGahay ,  Soon-Cheon Seo ,  Anthony K. Stamper ,  Yun Yu Wang ,  Erdem Kaltalioglu

发明人： Tze-Chiang Chen ,  Brett H. Engel ,  John A. Fitzsimmons ,  Terence Kane ,  Naftall E. Lustig ,  Ann McDonald ,  Vincent McGahay ,  Soon-Cheon Seo ,  Anthony K. Stamper ,  Yun Yu Wang ,  Erdem Kaltalioglu

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L23/58

CPC分类号： H01L21/76834 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76832 ,  H01L23/5226 ,  H01L23/53228 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： An advanced back-end-of-line (BEOL) metallization structure is disclosed. The structure includes a bilayer diffusion barrier or cap, where the first cap layer is formed of a dielectric material preferably deposited by a high density plasma chemical vapor deposition (HDP CVD) process, and the second cap layer is formed of a dielectric material preferably deposited by a plasma-enhanced chemical vapor deposition (PE CVD) process. A method for forming the BEOL metallization structure is also disclosed. The invention is particularly useful in interconnect structure comprising low-k dielectric material for the inter-layer dielectric (ILD) and copper for the conductors.

摘要翻译： 公开了一种先进的后端（BEOL）金属化结构。 该结构包括双层扩散阻挡层或盖，其中第一覆盖层由优选通过高密度等离子体化学气相沉积（HDP CVD）工艺沉积的电介质材料形成，并且第二覆盖层由介电材料形成，优选沉积 通过等离子体增强化学气相沉积（PE CVD）工艺。 还公开了一种用于形成BEOL金属化结构的方法。 本发明在包括用于层间电介质（ILD）的低k电介质材料和用于导体的铜的互连结构中是特别有用的。

公开(公告)号：US06894522B2

公开(公告)日：2005-05-17

申请号：US10605530

申请日：2003-10-06

申请人： Barbara A. Averill ,  Terence Kane ,  Darrell L. Miles ,  Richard W. Oldrey ,  John D. Sylvestri

发明人： Barbara A. Averill ,  Terence Kane ,  Darrell L. Miles ,  Richard W. Oldrey ,  John D. Sylvestri

IPC分类号： G01N1/32 ,  G01R31/28 ,  G01R31/26

CPC分类号： G01R31/2886 ,  G01N1/32 ,  G01R31/2898

摘要： A method for implementing backside probing of a semiconductor device includes isolating an identified defect area on a backside of the semiconductor device, and milling the identified defect area to an initial depth. Edges of the identified defect area are masked, wherein unmasked semiconductor material, beginning at the initial depth, is etched for a plurality of timed intervals until one or more active devices are reached. The one or more active devices are electrically probed.

摘要翻译： 用于实现半导体器件的背面探测的方法包括隔离半导体器件的背面上的识别的缺陷区域，以及将所识别的缺陷区域研磨到初始深度。 所识别的缺陷区域的边缘被掩蔽，其中从初始深度开始的未屏蔽半导体材料被蚀刻多个定时间隔，直到达到一个或多个有源器件。 一个或多个有源器件被电探测。

公开(公告)号：US20050073333A1

公开(公告)日：2005-04-07

申请号：US10605530

申请日：2003-10-06

申请人： Barbara Averill ,  Terence Kane ,  Darrell Miles ,  Richard Oldrey ,  John Sylvestri

发明人： Barbara Averill ,  Terence Kane ,  Darrell Miles ,  Richard Oldrey ,  John Sylvestri

IPC分类号： G01N1/32 ,  G01R31/28 ,  G01R31/26

CPC分类号： G01R31/2886 ,  G01N1/32 ,  G01R31/2898

摘要： A method for implementing backside probing of a semiconductor device includes isolating an identified defect area on a backside of the semiconductor device, and milling the identified defect area to an initial depth. Edges of the identified defect area are masked, wherein unmasked semiconductor material, beginning at the initial depth, is etched for a plurality of timed intervals until one or more active devices are reached. The one or more active devices are electrically probed.

摘要翻译： 用于实现半导体器件的背面探测的方法包括隔离半导体器件的背面上的识别的缺陷区域，以及将所识别的缺陷区域研磨到初始深度。 所识别的缺陷区域的边缘被掩蔽，其中从初始深度开始的未屏蔽半导体材料被蚀刻多个定时间隔，直到达到一个或多个有源器件。 一个或多个有源器件被电探测。

公开(公告)号：US06884641B2

公开(公告)日：2005-04-26

申请号：US10605258

申请日：2003-09-18

申请人： John Bruley ,  Terence Kane ,  Michael P. Tenney ,  Yun Yu Wang

发明人： John Bruley ,  Terence Kane ,  Michael P. Tenney ,  Yun Yu Wang

IPC分类号： G01R31/307 ,  H01L21/66 ,  H01L31/26

CPC分类号： H01L22/24 ,  G01R31/307 ,  H01L2924/0002 ,  Y10S438/902 ,  H01L2924/00

摘要： This invention relates to a method for electrically localizing site-specific defective sub 130 nm node MOSFET devices with shallow (less than 80 nm deep) source/drain junctions utilizing bulk silicon, or Silicon on Insulator (SOI), or strained silicon (SE), followed by optimized sample preparation steps that permits imaging, preferably high resolution electron holographic imaging, in an electron microscope to detect blocked implants, asymmetric doping, or channel length variations affecting MOSFET device performance. Detection of such defects in such shallow junctions enables further refinements in process simulation models and permits optimization of MOSFET device designs.

摘要翻译： 本发明涉及一种利用体硅或绝缘体上硅（SOI）或应变硅（SE）的具有浅（小于80nm深）源极/漏极结的电位定位缺陷子130nm节点MOSFET器件的方法， ，然后进行优化的样品制备步骤，其允许在电子显微镜中成像，优选高分辨率电子全息成像，以检测影响MOSFET器件性能的封闭植入物，不对称掺杂或沟道长度变化。 在这种浅结中的这种缺陷的检测使得能够进一步改进工艺仿真模型并允许优化MOSFET器件设计。

公开(公告)号：US06790125B2

公开(公告)日：2004-09-14

申请号：US09734225

申请日：2000-12-11

申请人： Terence Kane ,  Darrell L. Miles

发明人： Terence Kane ,  Darrell L. Miles

IPC分类号： B24B100

CPC分类号： B24B37/04 ,  B24B49/16

摘要： A method for preparing a semiconductor die for analysis comprises providing a semiconductor die having a connector on one side and an opposite, backside surface to be analyzed, providing a polishing pad for polishing the backside surface of a semiconductor die, providing a rotatable spindle for securing the polishing pad, and providing a constant force actuator on the spindle, the constant force actuator being adapted to provide constant force between the polishing pad and the backside surface of the die. The method then includes contacting the backside die surface with the polishing pad, rotating the spindle and polishing pad, and polishing the backside surface of the die while maintaining the substantially constant force of the polishing pad on the die backside surface with the constant force actuator.

摘要翻译： 制备用于分析的半导体管芯的方法包括：提供一半导体管芯，该半导体管芯具有在一侧的连接器和相对的待分析背面，提供用于抛光半导体管芯的背面的抛光垫，提供用于固定的可旋转主轴 抛光垫，并且在主轴上提供恒定的力致动器，恒力致动器适于在抛光垫和模具的后侧表面之间提供恒定的力。 该方法然后包括使背面模具表面与抛光垫接触，旋转主轴和抛光垫，并且用恒定力致动器保持抛光垫在模具背面上的基本上恒定的力，抛光模具的背面。

公开(公告)号：US06670717B2

公开(公告)日：2003-12-30

申请号：US09977807

申请日：2001-10-15

申请人： Terence Kane ,  Lawrence S. Fischer ,  Steven B. Herschbein ,  Ying Hong ,  Michael P. Tenney

发明人： Terence Kane ,  Lawrence S. Fischer ,  Steven B. Herschbein ,  Ying Hong ,  Michael P. Tenney

IPC分类号： H01L2348

CPC分类号： H01L22/34 ,  G01R31/2886 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method and structure for the electrical characterization of a semiconductor device comprising, first, forming a hole having a diameter less than 0.15 &mgr;m, wherein the hole is created using focused ion beam (FIB) etching, and through at least a protective cap layer formed over the device. The FIB etching occurs in an electron mode using a beam current less than 35 &rgr;A with an aperture size less than 50 &mgr;m, and at an acceleration voltage of about 50 kV. Second, the surface of the hole is coated with a metal, preferably using chemical vapor deposition (CVD) and preferably using a FIB device. Third, a metal pad is deposited, preferably by FIB CVD, over the hole. Fourth, the pad is probed to determine characteristics and/or detect defects of the electrical device. The present invention allows for electrical characterization without causing damage to the device or its features.