公开(公告)号：US06780779B2

公开(公告)日：2004-08-24

申请号：US10222855

申请日：2002-08-19

申请人： Tetsuya Ueda ,  Eiji Tamaoka ,  Nobuo Aoi

发明人： Tetsuya Ueda ,  Eiji Tamaoka ,  Nobuo Aoi

IPC分类号： H01L21302

CPC分类号： H01L21/76897 ,  H01L21/31144 ,  H01L21/76801 ,  H01L21/76811 ,  H01L21/76837 ,  H01L21/76885 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

摘要： After successively depositing a first metal film and a first silicon oxide film on an insulating film formed on a semiconductor substrate, etching is carried out by using a first resist pattern as a mask, so as to form a first interlayer insulating film having openings from the first silicon oxide film and first metal interconnects from the first metal film. A third interlayer insulating film of an organic film is filled in the openings of the first interlayer insulating film, and the first interlayer insulating film is etched by using a hard mask. A second metal film is then filled in a space in the second interlayer insulating film, so as to form second metal interconnects.

摘要翻译： 在形成在半导体衬底上的绝缘膜上依次沉积第一金属膜和第一氧化硅膜之后，通过使用第一抗蚀剂图案作为掩模进行蚀刻，从而形成具有开口的第一层间绝缘膜 第一氧化硅膜和第一金属互连从第一金属膜。 在第一层间绝缘膜的开口部填充有机膜的第三层间绝缘膜，使用硬掩模对第一层间绝缘膜进行蚀刻。 然后将第二金属膜填充在第二层间绝缘膜的空间中，以形成第二金属互连。

公开(公告)号：US06545361B2

公开(公告)日：2003-04-08

申请号：US09835169

申请日：2001-04-16

申请人： Tetsuya Ueda ,  Eiji Tamaoka ,  Nobuo Aoi

发明人： Tetsuya Ueda ,  Eiji Tamaoka ,  Nobuo Aoi

IPC分类号： H01L2348

CPC分类号： H01L21/76897 ,  H01L21/76801 ,  H01L21/7682 ,  H01L21/76838 ,  H01L21/76885 ,  H01L23/5222 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for fabricating a semiconductor device having a multilevel interconnection structure according to the present invention includes the steps of: covering a surface of a substrate with an insulating film; depositing a conductive film on the insulating film; forming a first interlevel dielectric film on the conductive film; forming an interlevel contact hole in the first interlevel dielectric film so as to reach the conductive film; filling in the interlevel contact hole with an interconnecting metal; forming a masking layer, defining a pattern of a first interconnect layer, on the first interlevel dielectric film so as to cover at least part of the interconnecting metal; forming the first interconnect layer out of the conductive film by etching the first interlevel dielectric film using the masking layer as a mask and by etching the conductive film using the masking layer and the interconnecting metal as a mask; removing the masking layer; depositing a second interlevel dielectric film over the substrate so as to cover the interconnecting metal and the first interconnect layer; planarizing the second interlevel dielectric film, thereby exposing at least part of the interconnecting metal; and forming a second interconnect layer to be electrically connected to an upper part of the interconnecting metal.

摘要翻译： 根据本发明的制造具有多层互连结构的半导体器件的方法包括以下步骤：用绝缘膜覆盖衬底的表面; 在绝缘膜上沉积导电膜; 在导电膜上形成第一层间电介质膜; 在所述第一层间绝缘膜中形成层间接触孔，以到达所述导电膜; 用互连金属填充层间接触孔; 在所述第一层间绝缘膜上形成限定第一互连层图案的掩模层，以便覆盖所述互连金属的至少一部分; 通过使用掩模层作为掩模蚀刻第一层间电介质膜，并且使用掩模层和互连金属作为掩模蚀刻导电膜，从导电膜形成第一互连层; 去除掩蔽层; 在所述衬底上沉积第二层间电介质膜以便覆盖所述互连金属和所述第一互连层; 平面化第二层间电介质膜，从而暴露至少部分互连金属; 以及形成与所述互连金属的上部电连接的第二互连层。

公开(公告)号：US06242336B1

公开(公告)日：2001-06-05

申请号：US09186067

申请日：1998-11-05

申请人： Tetsuya Ueda ,  Eiji Tamaoka ,  Nobuo Aoi

发明人： Tetsuya Ueda ,  Eiji Tamaoka ,  Nobuo Aoi

IPC分类号： H01L214763

CPC分类号： H01L21/76897 ,  H01L21/76801 ,  H01L21/7682 ,  H01L21/76838 ,  H01L21/76885 ,  H01L23/5222 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for fabricating a semiconductor device having a multilevel interconnection structure according to the present invention includes the steps of: covering a surface of a substrate with an insulating film; depositing a conductive film on the insulating film; forming a first interlevel dielectric film on the conductive film; forming an interlevel contact hole in the first interlevel dielectric film so as to reach the conductive film; filling in the interlevel contact hole with an interconnecting metal; forming a masking layer, defining a pattern of a first interconnect layer, on the first interlevel dielectric film so as to cover at least part of the interconnecting metal; forming the first interconnect layer out of the conductive film by etching the first interlevel dielectric film using the masking layer as a mask and by etching the conductive film using the masking layer and the interconnecting metal as a mask; removing the masking layer; depositing a second interlevel dielectric film over the substrate so as to cover the interconnecting metal and the first interconnect layer; planarizing the second interlevel dielectric film, thereby exposing at least part of the interconnecting metal; and forming a second interconnect layer to be electrically connected to an upper part of the interconnecting metal.

公开(公告)号：US06455436B1

公开(公告)日：2002-09-24

申请号：US09479243

申请日：2000-01-07

申请人： Tetsuya Ueda ,  Eiji Tamaoka ,  Nobuo Aoi

发明人： Tetsuya Ueda ,  Eiji Tamaoka ,  Nobuo Aoi

IPC分类号： H01L21302

CPC分类号： H01L21/76897 ,  H01L21/31144 ,  H01L21/76801 ,  H01L21/76811 ,  H01L21/76837 ,  H01L21/76885 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

摘要： After successively depositing a first metal film and a first silicon oxide film on an insulating film formed on a semiconductor substrate, etching is carried out by using a first resist pattern as a mask, so as to form a first interlayer insulating film having openings from the first silicon oxide film and first metal interconnects from the first metal film. A third interlayer insulating film of an organic film is filled in the openings of the first interlayer insulating film, and the first interlayer insulating film is etched by using a hard mask. A second metal film is then filled in a space in the second interlayer insulating film, so as to form second metal interconnects.

摘要翻译： 在形成在半导体衬底上的绝缘膜上依次沉积第一金属膜和第一氧化硅膜之后，通过使用第一抗蚀剂图案作为掩模进行蚀刻，从而形成具有开口的第一层间绝缘膜 第一氧化硅膜和第一金属互连从第一金属膜。 在第一层间绝缘膜的开口部填充有机膜的第三层间绝缘膜，使用硬掩模对第一层间绝缘膜进行蚀刻。 然后将第二金属膜填充在第二层间绝缘膜的空间中，以形成第二金属互连。

公开(公告)号：US06232237B1

公开(公告)日：2001-05-15

申请号：US09206982

申请日：1998-12-08

申请人： Eiji Tamaoka ,  Nobuo Aoi ,  Tetsuya Ueda

发明人： Eiji Tamaoka ,  Nobuo Aoi ,  Tetsuya Ueda

IPC分类号： H01L214763

CPC分类号： H01L21/02063 ,  G03F7/427 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/76802 ,  H01L21/76814

摘要： A method for fabricating a semiconductor device according to the present invention includes the steps of: a) forming an insulator film having Si—H bonds; b) forming a resist mask over a selected region of the insulator film; c) etching part of the insulator film that is not covered with the resist mask, thereby forming a recess in the insulator film; and d) removing the resist mask. The step d) includes the step of e) ashing the resist mask by using plasma produced from a gas comprising water vapor as a main component.

摘要翻译： 根据本发明的制造半导体器件的方法包括以下步骤：a）形成具有Si-H键的绝缘膜; b）在所述绝缘膜的选定区域上形成抗蚀剂掩模; c）蚀刻未被抗蚀剂掩模覆盖的绝缘体膜的一部分，从而在绝缘膜中形成凹部; 和d）去除抗蚀剂掩模。 步骤d）包括以下步骤：e）通过使用由包含水蒸汽作为主要成分的气体产生的等离子体来蚀刻抗蚀剂掩模。

公开(公告)号：US06300242B1

公开(公告)日：2001-10-09

申请号：US09560299

申请日：2000-04-27

申请人： Tetsuya Ueda ,  Eiji Tamaoka ,  Nobou Aoi ,  Hideo Nakagawa

发明人： Tetsuya Ueda ,  Eiji Tamaoka ,  Nobou Aoi ,  Hideo Nakagawa

IPC分类号： H01L214763

CPC分类号： H01L21/76897 ,  H01L21/7682 ,  H01L21/76838 ,  H01L21/76879 ,  H01L21/76885 ,  H01L21/76886

摘要： After a first metal film and a first interlayer insulating film are deposited successively on an insulating film on a semiconductor substrate, a via hole is formed in the first interlayer insulating film. A second metal film is grown in the via hole to form a via contact composed of the second metal film, while a recessed portion is formed over the via contact in the via hole. A cap layer composed of a material different from the material of the first metal film is formed in the recessed portion. Then, the first metal film is patterned by using a mask pattern for forming a lower interconnect and a cap layer as a mask, whereby a lower interconnect is formed.

摘要翻译： 在第一金属膜和第一层间绝缘膜依次沉积在半导体衬底上的绝缘膜上之后，在第一层间绝缘膜中形成通孔。 在通孔中生长第二金属膜以形成由第二金属膜构成的通孔接触，同时在通孔中的通孔接触件上方形成凹部。 在凹部中形成由与第一金属膜的材料不同的材料构成的盖层。 然后，通过使用用于形成下部布线的掩模图案和作为掩模的盖层来对第一金属膜进行图案化，从而形成下部互连。

公开(公告)号：US07144761B2

公开(公告)日：2006-12-05

申请号：US10958282

申请日：2004-10-06

申请人： Hideo Nakagwa ,  Eiji Tamaoka ,  Masafumi Kubota ,  Tetsuya Ueda

发明人： Hideo Nakagwa ,  Eiji Tamaoka ,  Masafumi Kubota ,  Tetsuya Ueda

IPC分类号： H01L21/48

CPC分类号： H01L21/7682 ,  H01L21/288 ,  H01L21/2885 ,  H01L21/32051 ,  H01L21/76879 ,  H01L21/76885 ,  H01L21/76897 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/5228 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes metal interconnects made from a multi-layer film composed of a first metal film formed on a semiconductor substrate with an insulating film sandwiched therebetween and a second metal film deposited on the first metal film. An interlayer insulating film having a via hole is formed on the metal interconnects. A third metal film is selectively grown on the second metal film within the via hole, so that a plug can be formed from the third metal film.

公开(公告)号：US20050059231A1

公开(公告)日：2005-03-17

申请号：US10958282

申请日：2004-10-06

申请人： Hideo Nakagawa ,  Eiji Tamaoka ,  Masafumi Kubota ,  Tetsuya Ueda

发明人： Hideo Nakagawa ,  Eiji Tamaoka ,  Masafumi Kubota ,  Tetsuya Ueda

IPC分类号： H01L21/288 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/48 ,  H01L29/40

CPC分类号： H01L21/7682 ,  H01L21/288 ,  H01L21/2885 ,  H01L21/32051 ,  H01L21/76879 ,  H01L21/76885 ,  H01L21/76897 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/5228 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes metal interconnects made from a multi-layer film composed of a first metal film formed on a semiconductor substrate with an insulating film sandwiched therebetween and a second metal film deposited on the first metal film. An interlayer insulating film having a via hole is formed on the metal interconnects. A third metal film is selectively grown on the second metal film within the via hole, so that a plug can be formed from the third metal film.

摘要翻译： 半导体器件包括由半导体衬底上形成的第一金属膜和夹在其间的绝缘膜构成的多层膜和沉积在第一金属膜上的第二金属膜制成的金属互连。 在金属互连件上形成具有通孔的层间绝缘膜。 选择性地在通孔内的第二金属膜上生长第三金属膜，从而能够从第三金属膜形成插塞。

公开(公告)号：US08669833B2

公开(公告)日：2014-03-11

申请号：US13375945

申请日：2010-06-03

申请人： Tetsuya Ueda

发明人： Tetsuya Ueda

IPC分类号： H01P1/205 ,  H01P7/10

CPC分类号： H01P7/10 ,  G02B1/002 ,  G02B5/3058 ,  H01P1/20 ,  H01P1/2084

摘要： In a metamaterial, a dielectric layer includes a host medium and dielectric bodies disposed in rows with predetermined intervals therebetween is sandwiched between a pair of conductive mesh plates each having holes, thereby forming a functional layer including dielectric resonators corresponding to the dielectric bodies. The metamaterial is configured by laminating the functional layers. The holes and the dielectric resonators are positioned coaxially and an electromagnetic wave is propagated in each of the functional layers in a propagation direction perpendicular to a multi-layered laminate surface such that the metamaterial function as a left-handed metamaterial in relation to the propagation direction perpendicular to the multi-layered surface.

摘要翻译： 在超材料中，电介质层包括主介体，并且以一定间隔设置成行的电介质体夹在一对具有孔的导电网板之间，从而形成包括对应于介电体的介电谐振器的功能层。 超材料通过层压功能层而构成。 孔和介质谐振器同轴地定位，并且电磁波在垂直于多层叠层表面的传播方向上在每个功能层中传播，使得超材料相对于传播方向作为左旋超材料 垂直于多层表面。

公开(公告)号：US08294538B2

公开(公告)日：2012-10-23

申请号：US12530102

申请日：2008-03-05

申请人： Tetsuya Ueda

发明人： Tetsuya Ueda

IPC分类号： H01P3/08

CPC分类号： H01Q1/38 ,  H01P1/203 ,  H01P1/207 ,  H01P1/32 ,  H01Q13/206

摘要： A transmission line microwave apparatus includes at least one nonreciprocal transmission line part, which includes a series branch circuit equivalently including a capacitive element and a shunt branch circuit equivalently including an inductive element. The nonreciprocal transmission line part has gyrotropic characteristic by being magnetized in a magnetization direction different from the propagation direction of a microwave, and has an asymmetric structure to a plane formed by the propagation direction and the magnetization direction. The nonreciprocal transmission line part has a propagation constant and an operating frequency set in a dispersion curve that represents a relation between the propagation constant and the operating frequency so that the propagation constant in the forward direction and the propagation constant in the backward direction have nonreciprocal phase characteristics different from each other. A microwave transmission line is constituted by cascade-connecting at least one non-reciprocal transmission line part between first and second ports.

摘要翻译： 传输线微波装置包括至少一个不可逆传输线部分，其包括等效地包括电容元件的串联分支电路和等效地包括电感元件的分流分支电路。 不可逆传输线部分通过在与微波的传播方向不同的磁化方向上磁化而具有陀螺特性，并且具有与由传播方向和磁化方向形成的平面不对称的结构。 不可逆传输线部分具有传播常数和在表示传播常数与工作频率之间的关系的色散曲线中设定的工作频率，使得正向传播常数和反向传播常数具有非相互相位 特征彼此不同。 微波传输线通过级联连接第一和第二端口之间的至少一个不可逆传输线部分而构成。