公开(公告)号：US07144761B2

公开(公告)日：2006-12-05

申请号：US10958282

申请日：2004-10-06

申请人： Hideo Nakagwa ,  Eiji Tamaoka ,  Masafumi Kubota ,  Tetsuya Ueda

发明人： Hideo Nakagwa ,  Eiji Tamaoka ,  Masafumi Kubota ,  Tetsuya Ueda

IPC分类号： H01L21/48

CPC分类号： H01L21/7682 ,  H01L21/288 ,  H01L21/2885 ,  H01L21/32051 ,  H01L21/76879 ,  H01L21/76885 ,  H01L21/76897 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/5228 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes metal interconnects made from a multi-layer film composed of a first metal film formed on a semiconductor substrate with an insulating film sandwiched therebetween and a second metal film deposited on the first metal film. An interlayer insulating film having a via hole is formed on the metal interconnects. A third metal film is selectively grown on the second metal film within the via hole, so that a plug can be formed from the third metal film.

公开(公告)号：US20050059231A1

公开(公告)日：2005-03-17

申请号：US10958282

申请日：2004-10-06

申请人： Hideo Nakagawa ,  Eiji Tamaoka ,  Masafumi Kubota ,  Tetsuya Ueda

发明人： Hideo Nakagawa ,  Eiji Tamaoka ,  Masafumi Kubota ,  Tetsuya Ueda

IPC分类号： H01L21/288 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/48 ,  H01L29/40

CPC分类号： H01L21/7682 ,  H01L21/288 ,  H01L21/2885 ,  H01L21/32051 ,  H01L21/76879 ,  H01L21/76885 ,  H01L21/76897 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/5228 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes metal interconnects made from a multi-layer film composed of a first metal film formed on a semiconductor substrate with an insulating film sandwiched therebetween and a second metal film deposited on the first metal film. An interlayer insulating film having a via hole is formed on the metal interconnects. A third metal film is selectively grown on the second metal film within the via hole, so that a plug can be formed from the third metal film.

摘要翻译： 半导体器件包括由半导体衬底上形成的第一金属膜和夹在其间的绝缘膜构成的多层膜和沉积在第一金属膜上的第二金属膜制成的金属互连。 在金属互连件上形成具有通孔的层间绝缘膜。 选择性地在通孔内的第二金属膜上生长第三金属膜，从而能够从第三金属膜形成插塞。

公开(公告)号：US06242336B1

公开(公告)日：2001-06-05

申请号：US09186067

申请日：1998-11-05

申请人： Tetsuya Ueda ,  Eiji Tamaoka ,  Nobuo Aoi

发明人： Tetsuya Ueda ,  Eiji Tamaoka ,  Nobuo Aoi

IPC分类号： H01L214763

CPC分类号： H01L21/76897 ,  H01L21/76801 ,  H01L21/7682 ,  H01L21/76838 ,  H01L21/76885 ,  H01L23/5222 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for fabricating a semiconductor device having a multilevel interconnection structure according to the present invention includes the steps of: covering a surface of a substrate with an insulating film; depositing a conductive film on the insulating film; forming a first interlevel dielectric film on the conductive film; forming an interlevel contact hole in the first interlevel dielectric film so as to reach the conductive film; filling in the interlevel contact hole with an interconnecting metal; forming a masking layer, defining a pattern of a first interconnect layer, on the first interlevel dielectric film so as to cover at least part of the interconnecting metal; forming the first interconnect layer out of the conductive film by etching the first interlevel dielectric film using the masking layer as a mask and by etching the conductive film using the masking layer and the interconnecting metal as a mask; removing the masking layer; depositing a second interlevel dielectric film over the substrate so as to cover the interconnecting metal and the first interconnect layer; planarizing the second interlevel dielectric film, thereby exposing at least part of the interconnecting metal; and forming a second interconnect layer to be electrically connected to an upper part of the interconnecting metal.

公开(公告)号：US20050161824A1

公开(公告)日：2005-07-28

申请号：US11082853

申请日：2005-03-18

申请人： Eiji Tamaoka ,  Hideo Nakagawa

发明人： Eiji Tamaoka ,  Hideo Nakagawa

IPC分类号： H01L23/52 ,  H01L21/3105 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/822 ,  H01L23/522 ,  H01L27/04 ,  H01L23/48

CPC分类号： H01L21/76897 ,  H01L21/31053 ,  H01L21/76819 ,  H01L21/7682 ,  H01L23/522 ,  H01L23/5222 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device of this invention includes a first interconnect pattern formed on a semiconductor substrate and a second interconnect pattern formed above the first interconnect pattern with an interlayer insulating film sandwiched therebetween. The first interconnect pattern includes a dummy pattern insulated from the first interconnect pattern, and the dummy pattern includes a plurality of fine patterns adjacent to each other and air gaps formed between the adjacent fine patterns.

摘要翻译： 本发明的半导体器件包括形成在半导体衬底上的第一互连图案和形成在第一布线图案之上的第二布线图案，夹在其间的层间绝缘膜。 第一互连图案包括与第一互连图案绝缘的虚设图案，并且虚设图案包括彼此相邻的多个精细图案以及形成在相邻精细图案之间的气隙。

公开(公告)号：US06780778B2

公开(公告)日：2004-08-24

申请号：US10206053

申请日：2002-07-29

申请人： Hideo Nakagawa ,  Eiji Tamaoka

发明人： Hideo Nakagawa ,  Eiji Tamaoka

IPC分类号： H01L21302

CPC分类号： H01L21/0273 ,  H01L21/31058 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76808 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76835 ,  H01L2221/1031

摘要： After an organic insulating film has been deposited over a semiconductor substrate, a silylated layer is formed selectively on the organic insulating film. Then, the organic insulating film is etched using the silylated layer as a mask, thereby forming an opening, which will be a via hole or interconnection groove, in the organic insulating film.

摘要翻译： 在半导体衬底上沉积有机绝缘膜之后，在有机绝缘膜上选择性地形成甲硅烷基化层。 然后，使用甲硅烷基化层作为掩模蚀刻有机绝缘膜，从而在有机绝缘膜中形成作为通孔或互连槽的开口。

公开(公告)号：US06762120B2

公开(公告)日：2004-07-13

申请号：US10251975

申请日：2002-09-23

申请人： Hideo Nakagawa ,  Eiji Tamaoka

发明人： Hideo Nakagawa ,  Eiji Tamaoka

IPC分类号： H01L214763

CPC分类号： H01L21/7682 ,  H01L23/5222 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： A plurality of metal interconnects are formed on a lower interlayer insulating film provided on a semiconductor substrate. An upper interlayer insulating film is formed so as to cover the plural metal interconnects. The upper interlayer insulating film has an air gap between the plural metal interconnects, and a top portion of the air gap is positioned at a level higher than the plural metal interconnects.

摘要翻译： 在设置在半导体衬底上的下层间绝缘膜上形成多个金属互连。 形成上层间绝缘膜以覆盖多个金属互连。 上层间绝缘膜在多个金属互连之间具有空气间隙，气隙的顶部位于比多个金属互连件高的位置。

公开(公告)号：US06562710B2

公开(公告)日：2003-05-13

申请号：US09971734

申请日：2001-10-09

申请人： Hideo Nakagawa ,  Reiko Hinogami ,  Eiji Tamaoka

发明人： Hideo Nakagawa ,  Reiko Hinogami ,  Eiji Tamaoka

IPC分类号： H01L214763

CPC分类号： H01L21/76897 ,  H01L21/7682 ,  H01L21/76877 ,  H01L21/76885 ,  H01L23/5222 ,  H01L23/544 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

摘要： After depositing a metal film on an insulating film on a semiconductor substrate, a first interlayer insulating film is formed on the metal film. After forming first plug openings in the first interlayer insulating film by etching the first interlayer insulating film with a first mask pattern used as a mask, first connection plugs are formed by filling a first conducting film in the first plug openings. A second interlayer insulating film is formed on the first interlayer insulating film. After forming second plug openings respectively on the first connection plugs in the second interlayer insulating film by etching the second interlayer insulating film with a second mask pattern used as a mask, second connection plugs are formed by filling a second conducting film in the second plug openings. The metal film is etched by using at least the first connection plugs and the second connection plugs as a mask so as to form metal interconnects, and then, a third interlayer insulating film is formed on the metal interconnects so as to form an air gap between the metal interconnects.

公开(公告)号：US06300242B1

公开(公告)日：2001-10-09

申请号：US09560299

申请日：2000-04-27

申请人： Tetsuya Ueda ,  Eiji Tamaoka ,  Nobou Aoi ,  Hideo Nakagawa

发明人： Tetsuya Ueda ,  Eiji Tamaoka ,  Nobou Aoi ,  Hideo Nakagawa

IPC分类号： H01L214763

CPC分类号： H01L21/76897 ,  H01L21/7682 ,  H01L21/76838 ,  H01L21/76879 ,  H01L21/76885 ,  H01L21/76886

摘要： After a first metal film and a first interlayer insulating film are deposited successively on an insulating film on a semiconductor substrate, a via hole is formed in the first interlayer insulating film. A second metal film is grown in the via hole to form a via contact composed of the second metal film, while a recessed portion is formed over the via contact in the via hole. A cap layer composed of a material different from the material of the first metal film is formed in the recessed portion. Then, the first metal film is patterned by using a mask pattern for forming a lower interconnect and a cap layer as a mask, whereby a lower interconnect is formed.

摘要翻译： 在第一金属膜和第一层间绝缘膜依次沉积在半导体衬底上的绝缘膜上之后，在第一层间绝缘膜中形成通孔。 在通孔中生长第二金属膜以形成由第二金属膜构成的通孔接触，同时在通孔中的通孔接触件上方形成凹部。 在凹部中形成由与第一金属膜的材料不同的材料构成的盖层。 然后，通过使用用于形成下部布线的掩模图案和作为掩模的盖层来对第一金属膜进行图案化，从而形成下部互连。

公开(公告)号：US06890830B2

公开(公告)日：2005-05-10

申请号：US10383772

申请日：2003-03-10

申请人： Eiji Tamaoka ,  Hideo Nakagawa

发明人： Eiji Tamaoka ,  Hideo Nakagawa

IPC分类号： H01L23/52 ,  H01L21/3105 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/822 ,  H01L23/522 ,  H01L27/04 ,  H01L21/76 ,  H01L21/4763

CPC分类号： H01L21/76897 ,  H01L21/31053 ,  H01L21/76819 ,  H01L21/7682 ,  H01L23/522 ,  H01L23/5222 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device of this invention includes a first interconnect pattern formed on a semiconductor substrate and a second interconnect pattern formed above the first interconnect pattern with an interlayer insulating film sandwiched therebetween. The first interconnect pattern includes a dummy pattern insulated from the first interconnect pattern, and the dummy pattern includes a plurality of fine patterns adjacent to each other and air gaps formed between the adjacent fine patterns.

公开(公告)号：US06780779B2

公开(公告)日：2004-08-24

申请号：US10222855

申请日：2002-08-19

申请人： Tetsuya Ueda ,  Eiji Tamaoka ,  Nobuo Aoi

发明人： Tetsuya Ueda ,  Eiji Tamaoka ,  Nobuo Aoi

IPC分类号： H01L21302

CPC分类号： H01L21/76897 ,  H01L21/31144 ,  H01L21/76801 ,  H01L21/76811 ,  H01L21/76837 ,  H01L21/76885 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

摘要： After successively depositing a first metal film and a first silicon oxide film on an insulating film formed on a semiconductor substrate, etching is carried out by using a first resist pattern as a mask, so as to form a first interlayer insulating film having openings from the first silicon oxide film and first metal interconnects from the first metal film. A third interlayer insulating film of an organic film is filled in the openings of the first interlayer insulating film, and the first interlayer insulating film is etched by using a hard mask. A second metal film is then filled in a space in the second interlayer insulating film, so as to form second metal interconnects.

摘要翻译： 在形成在半导体衬底上的绝缘膜上依次沉积第一金属膜和第一氧化硅膜之后，通过使用第一抗蚀剂图案作为掩模进行蚀刻，从而形成具有开口的第一层间绝缘膜 第一氧化硅膜和第一金属互连从第一金属膜。 在第一层间绝缘膜的开口部填充有机膜的第三层间绝缘膜，使用硬掩模对第一层间绝缘膜进行蚀刻。 然后将第二金属膜填充在第二层间绝缘膜的空间中，以形成第二金属互连。