公开(公告)号：US20180076277A1

公开(公告)日：2018-03-15

申请号：US15264147

申请日：2016-09-13

Applicant: Texas Instruments Incorporated

Inventor： Binghua Hu ,  Hideaki Kawahara ,  Sameer P. Pendharkar

IPC: H01L49/02 ,  H01L21/3205 ,  H01L21/762 ,  H01L21/02 ,  H01L21/265 ,  H01L29/08 ,  H01L21/306 ,  H01L29/06 ,  H01L27/06

CPC classification number: H01L28/40 ,  H01L21/0223 ,  H01L21/26513 ,  H01L21/30625 ,  H01L21/32055 ,  H01L21/76224 ,  H01L27/0629 ,  H01L29/0649 ,  H01L29/0847

Abstract: A deep trench capacitor and a method for providing the same in a semiconductor process are disclosed. The method includes forming a plurality of deep trenches in a first region of a semiconductor wafer, the first region having well doping of a first type. A dielectric layer is formed on a surface of the plurality of deep trenches and a doped polysilicon layer is deposited to fill the plurality of deep trenches, with the doped polysilicon being doped with a dopant of a second type. Shallow trench isolation is formed overlying the dielectric layer at an intersection of the dielectric layer with the surface of the semiconductor wafer.

公开(公告)号：US09806074B2

公开(公告)日：2017-10-31

申请号：US14965182

申请日：2015-12-10

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Yongxi Zhang ,  Sameer P. Pendharkar

IPC: H01L29/78 ,  H01L29/66 ,  H01L27/092 ,  H01L27/088 ,  H01L21/8238 ,  H01L21/265 ,  H01L21/324 ,  H01L21/762 ,  H01L29/06 ,  H01L29/10 ,  H01L29/167 ,  H01L21/225 ,  H01L21/266 ,  H01L29/08

CPC classification number: H01L27/088 ,  H01L21/2253 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/324 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/092 ,  H01L27/0922 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/1037 ,  H01L29/1045 ,  H01L29/1079 ,  H01L29/1095 ,  H01L29/167 ,  H01L29/66681 ,  H01L29/66689 ,  H01L29/66712 ,  H01L29/7802 ,  H01L29/7809 ,  H01L29/7816 ,  H01L29/7817 ,  H01L29/7831

Abstract: An integrated circuit and method having an LDMOS transistor with multiple current channels. A first current channel is above a buried p-type diffusion and a second one current channel is below the buried p-type diffusion.

公开(公告)号：US20170084738A1

公开(公告)日：2017-03-23

申请号：US15364971

申请日：2016-11-30

Applicant: Texas Instruments Incorporated

Inventor： Yongxi Zhang ,  Sameer P. Pendharkar ,  Henry Litzmann Edwards

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/423 ,  H01L29/06

CPC classification number: H01L29/7816 ,  H01L27/092 ,  H01L29/063 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/42356 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7817 ,  H01L29/7824 ,  H01L29/7831 ,  H01L29/7835

Abstract: RESURF-based dual-gate p-n bimodal conduction laterally diffused metal oxide semiconductors (LDMOS). In an illustrative embodiment, a p-type source is electrically coupled to an n-type drain. A p-type drain is electrically coupled to an n-type source. An n-type layer serves as an n-type conduction channel between the n-type drain and the n-type source. A p-type top layer is disposed at the surface of the substrate of said semiconductor device and is disposed above and adjacent to the n-type layer. The p-type top layer serves as a p-type conduction channel between the p-type source and the p-type drain. An n-gate controls current flow in the n-type conduction channel, and a p-gate controls current flow in the p-type conduction channel.

公开(公告)号：US09543299B1

公开(公告)日：2017-01-10

申请号：US14861912

申请日：2015-09-22

Applicant: Texas Instruments Incorporated

Inventor： Yongxi Zhang ,  Sameer P. Pendharkar ,  Henry Litzmann Edwards

IPC: H01L27/092 ,  H01L29/08 ,  H01L29/78

CPC classification number: H01L29/7816 ,  H01L27/092 ,  H01L29/063 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/42356 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7817 ,  H01L29/7824 ,  H01L29/7831 ,  H01L29/7835

Abstract: RESURF-based dual-gate p-n bimodal conduction laterally diffused metal oxide semiconductors (LDMOS). In an illustrative embodiment, a p-type source is electrically coupled to an n-type drain. A p-type drain is electrically coupled to an n-type source. An n-type layer serves as an n-type conduction channel between the n-type drain and the n-type source. A p-type top layer is disposed at the surface of the substrate of said semiconductor device and is disposed above and adjacent to the n-type layer. The p-type top layer serves as a p-type conduction channel between the p-type source and the p-type drain. An n-gate controls current flow in the n-type conduction channel, and a p-gate controls current flow in the p-type conduction channel.

Abstract translation: 基于RESURF的双栅p-n双峰传导横向扩散金属氧化物半导体（LDMOS）。 在说明性实施例中，p型源电耦合到n型漏极。 p型漏极电耦合到n型源极。 n型层用作n型漏极和n型源极之间的n型导电沟道。 p型顶层设置在所述半导体器件的衬底的表面上，并且设置在n型层的上方并与其相邻。 p型顶层用作p型源极和p型漏极之间的p型导电沟道。 n栅极控制n型导电沟道中的电流，p栅极控制p型导电沟道中的电流。

公开(公告)号：US20160308007A1

公开(公告)日：2016-10-20

申请号：US15191656

申请日：2016-06-24

Applicant: Texas Instruments Incorporated

Inventor： Binghua Hu ,  Sameer P. Pendharkar ,  Jarvis Benjamin Jacobs

IPC: H01L29/40

CPC classification number: H01L29/41 ,  H01L21/02164 ,  H01L21/02255 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/2253 ,  H01L21/26513 ,  H01L21/32155 ,  H01L21/324 ,  H01L21/743 ,  H01L21/763 ,  H01L28/20 ,  H01L28/40 ,  H01L29/407 ,  H01L29/45 ,  H01L29/945

Abstract: A semiconductor device is formed by forming a deep trench in a substrate and a dielectric liner on sidewalls of the deep trench. A first undoped polysilicon layer is formed on the semiconductor device, extending into the deep trench on the dielectric liner, but not filling the deep trench. Dopants are implanted into the first polysilicon layer. A second layer of polysilicon is formed on the first layer of polysilicon. A thermal drive anneal activates and diffuses the dopants. In one version, the dielectric liner is removed at the bottom of the deep trench before the first polysilicon layer is formed, so that the polysilicon in the deep trench provides a contact to the substrate. In another version, the polysilicon in the deep trench is isolated from the substrate by the dielectric liner.

Abstract translation: 半导体器件通过在衬底中形成深沟槽和在深沟槽的侧壁上形成介电衬垫来形成。 第一未掺杂多晶硅层形成在半导体器件上，延伸到电介质衬垫上的深沟槽中，但不填充深沟槽。 将掺杂剂注入到第一多晶硅层中。 在第一多晶硅层上形成第二层多晶硅。 热驱动退火激活并扩散掺杂剂。 在一个版本中，在形成第一多晶硅层之前，在深沟槽的底部去除电介质衬垫，使得深沟槽中的多晶硅提供与衬底的接触。 在另一种形式中，深沟槽中的多晶硅通过电介质衬垫从衬底隔离。

公开(公告)号：US20160149011A1

公开(公告)日：2016-05-26

申请号：US14555300

申请日：2014-11-26

Applicant: Texas Instruments Incorporated

Inventor： Binghua Hu ,  Sameer P. Pendharkar ,  Jarvis Benjamin Jacobs

IPC: H01L29/45 ,  H01L29/41 ,  H01L21/225 ,  H01L21/265 ,  H01L21/3215 ,  H01L21/324 ,  H01L49/02 ,  H01L21/02

CPC classification number: H01L29/41 ,  H01L21/02164 ,  H01L21/02255 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/2253 ,  H01L21/26513 ,  H01L21/32155 ,  H01L21/324 ,  H01L21/743 ,  H01L21/763 ,  H01L28/20 ,  H01L28/40 ,  H01L29/407 ,  H01L29/45 ,  H01L29/945

Abstract: A semiconductor device is formed by forming a deep trench in a substrate and a dielectric liner on sidewalls of the deep trench. A first undoped polysilicon layer is formed on the semiconductor device, extending into the deep trench on the dielectric liner, but not filling the deep trench. Dopants are implanted into the first polysilicon layer. A second layer of polysilicon is formed on the first layer of polysilicon. A thermal drive anneal activates and diffuses the dopants. In one version, the dielectric liner is removed at the bottom of the deep trench before the first polysilicon layer is formed, so that the polysilicon in the deep trench provides a contact to the substrate. In another version, the polysilicon in the deep trench is isolated from the substrate by the dielectric liner.

公开(公告)号：US10903306B2

公开(公告)日：2021-01-26

申请号：US16163606

申请日：2018-10-18

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Binghua Hu ,  Hideaki Kawahara ,  Sameer P. Pendharkar

IPC: H01L49/02 ,  H01L21/02 ,  H01L21/265 ,  H01L21/306 ,  H01L21/3205 ,  H01L21/762 ,  H01L27/06 ,  H01L29/06 ,  H01L29/08

Abstract: Embodiments of a deep trench capacitor are disclosed. In one example a plurality of deep trenches is located in a first region of a semiconductor wafer, the first region having a first conductivity type. A corresponding dielectric layer is located on a surface of each of the plurality of deep trenches, and a corresponding doped polysilicon filler is located within each of the dielectric layers. Dielectric-filled trenches are located between each of the dielectric layers and the surface of the semiconductor wafer.

公开(公告)号：US10121891B2

公开(公告)日：2018-11-06

申请号：US15364971

申请日：2016-11-30

Applicant: Texas Instruments Incorporated

Inventor： Yongxi Zhang ,  Sameer P. Pendharkar ,  Henry Litzmann Edwards

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/10 ,  H01L29/66 ,  H01L27/092

Abstract: RESURF-based dual-gate p-n bimodal conduction laterally diffused metal oxide semiconductors (LDMOS). In an illustrative embodiment, a p-type source is electrically coupled to an n-type drain. A p-type drain is electrically coupled to an n-type source. An n-type layer serves as an n-type conduction channel between the n-type drain and the n-type source. A p-type top layer is disposed at the surface of the substrate of said semiconductor device and is disposed above and adjacent to the n-type layer. The p-type top layer serves as a p-type conduction channel between the p-type source and the p-type drain. An n-gate controls current flow in the n-type conduction channel, and a p-gate controls current flow in the p-type conduction channel.

公开(公告)号：US09985028B2

公开(公告)日：2018-05-29

申请号：US15491179

申请日：2017-04-19

Applicant: Texas Instruments Incorporated

Inventor： Yongxi Zhang ,  Sameer P. Pendharkar ,  Scott G. Balster

IPC: H01L21/761 ,  H01L27/092 ,  H01L29/66 ,  H01L21/266 ,  H01L21/762 ,  H01L29/06 ,  H01L29/10 ,  H01L29/78

CPC classification number: H01L27/0922 ,  H01L21/266 ,  H01L21/76224 ,  H01L27/092 ,  H01L29/0623 ,  H01L29/063 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/1095 ,  H01L29/66681 ,  H01L29/7816

Abstract: A multi-finger lateral high voltage transistors (MFLHVT) includes a substrate doped a first dopant type, a well doped a second dopant type, and a buried drift layer (BDL) doped first type having a diluted BDL portion (DBDL) including dilution stripes. A semiconductor surface doped the second type is on the BDL. Dielectric isolation regions have gaps defining a first active area in a first gap region (first MOAT) and a second active area in a second gap region (second MOAT). A drain includes drain fingers in the second MOAT interdigitated with source fingers in the first MOAT each doped second type. The DBDL is within a fingertip drift region associated drain fingertips and/or source fingertips between the first and second MOAT. A gate stack is on the semiconductor surface between source and drain. The dilution stripes have stripe widths that increase monotonically with a drift length at their respective positions.

公开(公告)号：US20170264289A1

公开(公告)日：2017-09-14

申请号：US15067928

申请日：2016-03-11

Applicant: Texas Instruments Incorporated

Inventor： Yongxi Zhang ,  Sameer P. Pendharkar ,  Philip L. Hower ,  Salvatore Giombanco ,  Filippo Marino ,  Seetharaman Sridhar

IPC: H03K17/687 ,  H01L29/06 ,  H03K19/0185 ,  H01L27/092

CPC classification number: H03K19/018521 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/1033 ,  H01L29/7816 ,  H01L29/7831 ,  H03K17/122

Abstract: An integrated circuit chip includes a bimodal power N-P-Laterally Diffused Metal Oxide Semiconductor (LDMOS) device having an N-gate coupled to receive an input signal and a level shifter coupled to receive the input signal and to provide a control signal to a P-gate driver of the N-P-LDMOS device. A method of operating an N-P-LDMOS power device is also disclosed.