公开(公告)号：US08910369B2

公开(公告)日：2014-12-16

申请号：US14275009

申请日：2014-05-12

Applicant: Texas Instruments Incorporated

Inventor： Juan A Herbsommer ,  Osvaldo J Lopez ,  Jonathan A Noquil ,  David Jauregui ,  Lucian Hriscu

IPC: H05K7/20 ,  H02M3/00 ,  H01R43/26 ,  H02B1/48

CPC classification number: H02M3/00 ,  H01R43/26 ,  H02B1/48 ,  H05K7/2039 ,  H05K7/2089 ,  H05K7/209 ,  Y10T29/49002 ,  Y10T29/49073 ,  Y10T29/49117

Abstract: A method for fabricating a power supply converter comprises a load inductor wrapped by a metal sleeve structured to transform the inductor into a heat sink positioned to deposit layers of solder paste on a sleeve surface and on the inductor leads. A metal carrier having a portion of a first thickness and portions of a greater second thickness is placed on the solder layers of the inductor. The carrier portion of first thickness is aligned with the inductor sleeve. The carrier portions of second thickness are aligned with the inductor leads. A sync and a control FET are placed side-by-side on solder layers deposited on the carrier portion of first thickness opposite the inductor sleeve. Reflowing is preformed and the solder layers are solidified. The FETs, the carrier and the inductor become integrated and the un-soldered surfaces of the FETs and the carrier portions of second thickness become coplanar.

Abstract translation: 一种用于制造电源转换器的方法包括由金属套管包围的负载感应器，所述金属套管构造成将电感器转换成散热器，该散热器定位成在套筒表面上和电感器引线上沉积焊膏层。 具有第一厚度的一部分和更大的第二厚度的部分的金属载体被放置在电感器的焊料层上。 第一厚度的载体部分与电感器套筒对准。 第二厚度的载体部分与电感器引线对准。 同步和控制FET并排放置在沉积在与电感器套筒相对的第一厚度的载体部分上的焊料层上。 进行回流，并使焊料层固化。 FET，载体和电感器变得集成，并且FET的未焊接表面和第二厚度的载体部分变得共面。

公开(公告)号：US09779967B2

公开(公告)日：2017-10-03

申请号：US14854140

申请日：2015-09-15

Applicant: Texas Instruments Incorporated

Inventor： Juan A Herbsommer ,  Osvaldo J Lopez ,  Jonathan A Noquil

IPC: H01L21/48 ,  H01L23/495 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L21/4825 ,  H01L21/563 ,  H01L23/3107 ,  H01L23/49537 ,  H01L23/49548 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/19 ,  H01L24/20 ,  H01L24/27 ,  H01L24/29 ,  H01L24/30 ,  H01L24/32 ,  H01L24/33 ,  H01L24/83 ,  H01L2224/2101 ,  H01L2224/211 ,  H01L2224/215 ,  H01L2224/2732 ,  H01L2224/291 ,  H01L2224/29193 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32104 ,  H01L2224/32227 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/83192 ,  H01L2224/838 ,  H01L2224/83815 ,  H01L2224/83851 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2924/01028 ,  H01L2924/00

Abstract: A power field-effect transistor package is fabricated. A leadframe including a flat plate and a coplanar flat strip spaced from the plate is provided. The plate has a first thickness and the strip has a second thickness smaller than the first thickness. A field-effect power transistor chip having a third thickness is provided. A first and second contact pad on one chip side and a third contact pad on the opposite chip side are created. The first pad is attached to the plate and the second pad to the strip. Terminals are concurrently attached to the plate and the strip so that the terminals are coplanar with the third contact pad. The thickness difference between plate and strip and spaces between chip and terminals is filled with an encapsulation compound having a surface coplanar with the plate and the opposite surface coplanar with the third pad and terminals. The chip, leadframe and terminals are integrated into a package having a thickness equal to the sum of the first and third thicknesses.