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15 条记录 (耗时 0.028 秒)

    Method for etching a substrate and a device formed using the method
    6.
    发明申请
    Method for etching a substrate and a device formed using the method 有权
    用于蚀刻基板的方法和使用该方法形成的器件

    公开(公告)号：US20050112898A1

    公开(公告)日：2005-05-26

    申请号：US10721932

    申请日：2003-11-25

    申请人： K.R. Udayakumar ,  Ted Moise ,  Scott Summerfelt ,  Martin Albrecht ,  William Dostalik ,  Francis Celii

    发明人： K.R. Udayakumar ,  Ted Moise ,  Scott Summerfelt ,  Martin Albrecht ,  William Dostalik ,  Francis Celii

    IPC分类号： H01L21/02 ,  H01L21/311 ,  H01L21/316 ,  H01L21/768 ,  H01L21/302 ,  H01L21/461

    CPC分类号： H01L21/31116 ,  H01L21/31616 ,  H01L21/76895 ,  H01L28/55

    摘要： The present invention provides a method for etching a substrate, a method for forming an integrated circuit, an integrated circuit formed using the method, and an integrated circuit. The method for etching a substrate includes, among other steps, providing a substrate 140 having an aluminum oxide etch stop layer 130 located thereunder, and then etching an opening 150, 155, in the substrate 140 using an etchant comprising carbon oxide, a fluorocarbon, an etch rate modulator, and an inert carrier gas, wherein a flow rate of the carbon oxide is greater than about 80 sccm and the etchant is selective to the aluminum oxide etch stop layer 130. The aluminum oxide etch stop layer may also be used in the back-end of advanced CMOS processes as a via etch stop layer.

    摘要翻译： 本发明提供了蚀刻基板的方法，集成电路的形成方法，使用该方法形成的集成电路和集成电路。 除了其他步骤之外，用于蚀刻衬底的方法包括提供具有位于其下方的氧化铝蚀刻停止层130的衬底140，然后使用包含碳氧化物，碳氟化合物的蚀刻剂在衬底140中蚀刻开口150,155， 蚀刻速率调制器和惰性载气，其中碳氧化物的流速大于约80sccm，并且蚀刻剂对氧化铝蚀刻停止层130是选择性的。 氧化铝蚀刻停止层也可用作先进CMOS工艺的后端作为通孔蚀刻停止层。

    Method for Forming Ferroelectric Memory Capacitor
    7.
    发明申请
    Method for Forming Ferroelectric Memory Capacitor 审中-公开
    形成铁电存储电容器的方法

    公开(公告)号：US20070221974A1

    公开(公告)日：2007-09-27

    申请号：US11756372

    申请日：2007-05-31

    申请人： Francis Celii ,  Mahesh Thakre ,  Scott Summerfelt

    发明人： Francis Celii ,  Mahesh Thakre ,  Scott Summerfelt

    IPC分类号： H01L29/94

    CPC分类号： H01L28/55 ,  H01L21/31122 ,  H01L21/32136 ,  H01L28/75

    摘要： A ferroelectric memory capacitor is formed by forming a barrier layer, a first metal layer, a ferroelectric layer, a second metal layer, and a hard mask layer, on dielectric layer (70). Using the patterned hard mask layer (255), the layers are etched to form an etched barrier layer (205), and etched first metal layer (215), and etched ferroelectric layer (225), and etched second metal layers (235, 245). The etched layers form a ferroelectric memory capacitor (270) with sidewalls that form an angle with the plane of the upper surface of the dielectric layer (70) between 78° and 88°. The processes used to etch the layers are plasma processes performed at temperatures between 200° C. and 500° C.

    摘要翻译： 在电介质层（70）上形成阻挡层，第一金属层，铁电体层，第二金属层和硬掩模层，形成铁电存储电容器。 使用图案化的硬掩模层（255），蚀刻这些层以形成蚀刻的阻挡层（205），蚀刻第一金属层（215）和蚀刻铁电层（225），并蚀刻第二金属层 ）。 蚀刻层形成具有与电介质层（70）的上表面的平面形成角度为78°至88°的侧壁的铁电存储电容器（270）。 用于蚀刻层的工艺是在200℃和500℃之间的温度下进行的等离子体处理。

    FeRAM capacitor stack etch
    8.
    发明申请
    FeRAM capacitor stack etch 有权
    FeRAM电容堆栈蚀刻

    公开(公告)号：US20050054122A1

    公开(公告)日：2005-03-10

    申请号：US10968721

    申请日：2004-10-19

    申请人： Francis Celii ,  Scott Summerfelt ,  Mahesh Thakre

    发明人： Francis Celii ,  Scott Summerfelt ,  Mahesh Thakre

    IPC分类号： H01L21/3065 ,  H01L21/02 ,  H01L21/311 ,  H01L21/316 ,  H01L21/3213 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/115 ,  H01L21/00

    CPC分类号： H01L27/11502 ,  H01L21/31122 ,  H01L21/31691 ,  H01L21/32139 ,  H01L27/11507 ,  H01L28/55

    摘要： The present invention is directed to a method of forming an FeRAM integrated circuit, which includes performing a capacitor stack etch to define the FeRAM capacitor. The method comprises etching a PZT ferroelectric layer with a high temperature BCl3 etch which provides substantial selectivity with respect to the hard mask. Alternatively, the PZT ferroelectric layer is etch using a low temperature fluorine component etch chemistry such as CHF3 to provide a non-vertical PZT sidewall profile. Such a profile prevents conductive material associated with a subsequent bottom electrode layer etch from depositing on the PZT sidewall, thereby preventing leakage or a “shorting out” of the resulting FeRAM capacitor.

    摘要翻译： 本发明涉及形成FeRAM集成电路的方法，其包括执行电容器堆叠蚀刻以限定FeRAM电容器。 该方法包括用提供相对于硬掩模的实质选择性的高温BCl3蚀刻来蚀刻PZT铁电层。 或者，PZT铁电层是使用诸如CHF 3的低温氟成分蚀刻化学品进行蚀刻，以提供非垂直PZT侧壁轮廓。 这种轮廓防止与随后的底部电极层蚀刻相关联的导电材料沉积在PZT侧壁上，从而防止所得FeRAM电容器的泄漏或“短路”。

    GAS SWITCHING DURING AN ETCH PROCESS TO MODULATE THE CHARACTERISTICS OF THE ETCH
    9.
    发明申请
    GAS SWITCHING DURING AN ETCH PROCESS TO MODULATE THE CHARACTERISTICS OF THE ETCH 有权
    在ETCH过程中的气体开关调节ETCH的特性

    公开(公告)号：US20070275561A1

    公开(公告)日：2007-11-29

    申请号：US11420405

    申请日：2006-05-25

    申请人： Ping Jiang ,  Francis Celii

    发明人： Ping Jiang ,  Francis Celii

    IPC分类号： H01L21/311 ,  H01L21/302

    CPC分类号： H01L21/31144 ,  H01L21/30655 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/76808

    摘要： Gas switching is used during an etch process to modulate the characteristics of the etch. The etch process comprises a sequence of at least three steps, wherein the sequence is repeated at least once. For example, the first step may result in a high etch rate of oxide (108) while the second step is a polymer coating steps and the third step results in a low etch rate of oxide and high etch rate of another material (114) and/or sputtering.

    摘要翻译： 在蚀刻过程中使用气体切换来调制蚀刻的特性。 蚀刻过程包括至少三个步骤的序列，其中该序列重复至少一次。 例如，第一步可能导致氧化物（108）的高蚀刻速率，而第二步骤是聚合物涂覆步骤，第三步骤导致氧化物的低蚀刻速率和另一种材料（114）的高蚀刻速率， /或溅射。

    Gas switching during an etch process to modulate the characteristics of the etch
    10.
    发明申请
    Gas switching during an etch process to modulate the characteristics of the etch 有权
    在蚀刻工艺期间的气体切换以调制蚀刻的特性

    公开(公告)号：US20080090423A1

    公开(公告)日：2008-04-17

    申请号：US11923852

    申请日：2007-10-25

    申请人： Ping Jiang ,  Francis Celii

    发明人： Ping Jiang ,  Francis Celii

    IPC分类号： H01L21/31

    CPC分类号： H01L21/31144 ,  H01L21/30655 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/76808

    摘要： Gas switching is used during an etch process to modulate the characteristics of the etch. The etch process comprises a sequence of at least three steps, wherein the sequence is repeated at least once. For example, the first step may result in a high etch rate of oxide (108) while the second step is a polymer coating steps and the third step results in a low etch rate of oxide and high etch rate of another material (114) and/or sputtering.

    摘要翻译： 在蚀刻过程中使用气体切换来调制蚀刻的特性。 蚀刻过程包括至少三个步骤的序列，其中该序列重复至少一次。 例如，第一步可能导致氧化物（108）的高蚀刻速率，而第二步骤是聚合物涂覆步骤，第三步骤导致氧化物的低蚀刻速率和另一种材料（114）的高蚀刻速率， /或溅射。