公开(公告)号：US5782503A

公开(公告)日：1998-07-21

申请号：US636932

申请日：1996-04-24

申请人： Thierry Noel ,  Akira Narita

发明人： Thierry Noel ,  Akira Narita

IPC分类号： F16L9/02 ,  E21B17/042 ,  F16L15/04 ,  F16L15/06 ,  F16L7/00

CPC分类号： E21B17/042 ,  F16L15/001

摘要： The threaded joint for tubes according to the invention concerns sealed end to end connections of metal tubes useable in particular in the petroleum industry. This joint comprises a sleeve provided with two housings with tapered threads into which are screwed the male extremities of two metal tubes provided with corresponding threads having non-threaded extremity zones the front walls of which abut one against the other, a clearance existing between the lateral walls of these zones and the annular wall of he sleeve opposite. Two pairs of male/female shoulder stops prevent over-screwing. The heights of the teeth of the male and female threads are identical.

摘要翻译： 根据本发明的用于管的螺纹接头涉及可以特别在石油工业中使用的金属管的密封端对端连接。 该接头包括设置有两个具有锥形螺纹的壳体的套筒，螺栓将两个金属管的公端螺纹拧入两个金属管的两个金属管中，该两个金属管设置有具有非螺纹末端区的螺纹末端区，其前壁相对于另一个突出， 这些区域的墙壁和他的套筒的环形壁相对。 两对男/女肩膀防止过度拧紧。 公螺纹和母螺纹的齿的高度是相同的。

公开(公告)号：US5066219A

公开(公告)日：1991-11-19

申请号：US500782

申请日：1990-03-28

申请人： Norio Anzawa ,  Koji Adachi ,  Tetsuo Futakawa ,  Hironari Sato ,  Akira Narita

发明人： Norio Anzawa ,  Koji Adachi ,  Tetsuo Futakawa ,  Hironari Sato ,  Akira Narita

IPC分类号： F23D5/00 ,  F23D5/14

CPC分类号： F23D5/00 ,  F23D5/14

摘要： A method and apparatus for burning a liquid fuel by introducing gas into the liquid fuel through capillaries, a porous plate, cloth, a particle layer or the like to bubble the liquid fuel to control the fuel level and simultaneously by supplying combustion air separately to accomplish complete combustion.

公开(公告)号：US4692834A

公开(公告)日：1987-09-08

申请号：US761707

申请日：1985-08-02

申请人： Hiroshi Iwahashi ,  Masamichi Asano ,  Akira Narita

发明人： Hiroshi Iwahashi ,  Masamichi Asano ,  Akira Narita

IPC分类号： H01L27/06 ,  H02H9/04 ,  H02H3/20

CPC分类号： H02H9/046

摘要： An electrostatic discharge protection circuit is provided with a variable threshold for limiting the potential of an input signal having a given high or low voltage, and is adapted to an EPROM containing an input MOS transistor which is responsive to the input signal. The protection circuit is associated with an input terminal for receiving the input signal. The input terminal is coupled to the gate of the input MOS transistor. The protection circuit also includes a circuit element for limiting or suppressing the input signal potential at the variable threshold. The gate of the input MOS transistor receives the potential limited signal from the circuit element. The circuit element is responsive to a given threshold control potential. The variable threshold is enhanced by the given threshold control potential when a high-voltage input signal is applied to the input terminal.

摘要翻译： 静电放电保护电路具有用于限制具有给定高或低电压的输入信号的电位的可变阈值，并且适用于包含响应于输入信号的输入MOS晶体管的EPROM。 保护电路与用于接收输入信号的输入端相关联。 输入端耦合到输入MOS晶体管的栅极。 保护电路还包括用于限制或抑制在可变阈值处的输入信号电位的电路元件。 输入MOS晶体管的栅极接收来自电路元件的电位限制信号。 电路元件响应给定的阈值控制电位。 当将高电压输入信号施加到输入端时，通过给定的阈值控制电位增强可变阈值。

公开(公告)号：US5829797A

公开(公告)日：1998-11-03

申请号：US561587

申请日：1995-11-21

申请人： Miyuki Yamamoto ,  Akira Narita ,  Jun Maeda

发明人： Miyuki Yamamoto ,  Akira Narita ,  Jun Maeda

IPC分类号： E21B17/042 ,  F16L15/06 ,  F16L15/00

CPC分类号： F16L15/001 ,  E21B17/042

摘要： A threaded joint for an oil well pipe having (1) a tapered threaded having roughly the shape of a buttress thread, (2) a pin having a male thread and a box having a female thread, (3) a seal and a torque shoulder, characterized in that (i) the load flank angle of the threads is -20.degree. or greater and less than 0.degree., the stab flank angle is greater than 30.degree. and at most 60.degree. (ii) there is a positive amount of interference between the male threads and the female threads, and (iii) during and at the completion of make-up, the load flanks and the stab flanks are contacting each other, and there is a gap between the crests and the roots.

摘要翻译： 一种用于油井管的螺纹接头，其具有（1）具有大致为支撑螺纹形状的锥形螺纹，（2）具有外螺纹的销和具有内螺纹的箱，（3）密封件和扭矩肩 其特征在于，（i）螺纹的负载侧面角度为-20°以上且小于0°，刀尖侧角大于30°，至多60°（ii）存在正的干涉量 在外螺纹和内螺纹之间，以及（iii）在补充和补充完成期间，负载侧面和刺侧面彼此接触，并且在顶部和根部之间存在间隙。

公开(公告)号：US4697101A

公开(公告)日：1987-09-29

申请号：US645392

申请日：1984-08-29

申请人： Hiroshi Iwahashi ,  Masamichi Asano ,  Masaki Momodomi ,  Hidenobu Minagawa ,  Kazuto Suzuki ,  Akira Narita

发明人： Hiroshi Iwahashi ,  Masamichi Asano ,  Masaki Momodomi ,  Hidenobu Minagawa ,  Kazuto Suzuki ,  Akira Narita

IPC分类号： G11C16/12 ,  G11C16/30 ,  H03K19/096 ,  G06F7/38 ,  H03K17/16

CPC分类号： G11C16/30 ,  G11C16/12

摘要： A semiconductor integrated circuit which has a CMOS inverter formed of p- and n-channel MOSFETs, and a D-type n-channel MOSFET coupled at the gate to the output terminal of the CMOS inverter, having one end coupled to a high voltage terminal and the other end coupled to the drain of the p-channel MOSFET.

摘要翻译： 一种半导体集成电路，其具有由p-沟道MOSFET和n沟道MOSFET形成的CMOS反相器，以及在栅极处连接到CMOS反相器的输出端的D型n沟道MOSFET，其一端耦合到高电压端子 另一端耦合到p沟道MOSFET的漏极。

公开(公告)号：US5649725A

公开(公告)日：1997-07-22

申请号：US544137

申请日：1995-10-17

申请人： Shigeo Nagasaku ,  Kenichi Ohyabu ,  Jun Maeda ,  Akira Narita

发明人： Shigeo Nagasaku ,  Kenichi Ohyabu ,  Jun Maeda ,  Akira Narita

IPC分类号： E21B17/042 ,  F16L15/00 ,  F16L15/04 ,  F16L25/00

CPC分类号： E21B17/042 ,  F16L15/004

摘要： A thread joint for a tube which suppresses galling without deteriorating its sealing performance since a sliding distance L.sub.S which expresses a quantity of spiral sliding of sealing portions relative to each other during a tightening period from the start of a contact between the sealing portions until shoulder portions abut each other satisfies the following relationship:Sliding Distance L.sub.S .ltoreq.-0.0093.times. (Tube Outer Diameter).sup.2 +4.73.times. (Tube Outer Diameter).To shorten the sliding distance L.sub.S, the sealing portion of a box portion is formed shorter than the sealing portion of a pin portion. In this case, a circumferential groove may be formed to discharge a dope. Conversely, the sealing portion of the pin portion is formed shorter than the sealing portion of the box portion. In this case, a precedent-stage unthread portion whose inclination is smaller than that of the sealing portion of the pin portion is formed between a male thread and the sealing portion of the pin portion. In addition, tapers of the sealing portions of the pin portion and the box portion are set at 1/6 or larger, and/or, a distance where the sealing portion of the box portion (pin portion) is formed so as to contact a curve which is tangent to the sealing portion of the pin portion (box portion) is 1.45 mm or larger.

摘要翻译： 一种用于管的螺纹接头，其在从密封部分之间的接触开始直到肩部部分的紧固期间的紧固期间，表现出密封部分相对于彼此的螺旋滑动量的滑动距离LS，从而抑制磨损，而不会降低其密封性能 彼此相邻满足以下关系：滑动距离LS <= - 0.0093x（管外直径）2 + 4.73x（管外直径）。 为了缩短滑动距离LS，盒部的密封部形成为比销部的密封部短。 在这种情况下，可以形成周向槽以排出涂料。 相反，销部分的密封部分形成得比盒部分的密封部分短。 在这种情况下，在外螺纹和销部的密封部之间形成有倾斜小于销部的密封部的倾斜度的前级无螺纹部。 此外，销部分和箱部分的密封部分的锥度设定为+ E，fra 1/6 + EE或更大，和/或设置在盒部分（销部分）的密封部分 形成为与销部（盒部）的密封部相切的曲线接触的距离为1.45mm以上。

公开(公告)号：US5336952A

公开(公告)日：1994-08-09

申请号：US67102

申请日：1993-05-26

申请人： Hiroshi Iwahashi ,  Toshiyuki Fujimoto ,  Akira Narita

发明人： Hiroshi Iwahashi ,  Toshiyuki Fujimoto ,  Akira Narita

IPC分类号： G11C17/00 ,  G11C5/14 ,  G11C8/08 ,  G11C16/06 ,  G11C16/12 ,  H03K17/10 ,  H03K17/687

CPC分类号： G11C5/145 ,  G11C16/12 ,  G11C8/08 ,  H03K17/102

摘要： A semiconductor integrated circuit which is protected from element breakdown includes a memory cell, series-connected first and second program load transistors arranged between the memory cell and the program power source, a boosting circuit for outputting a board voltage higher than the voltage of a program power source, and a controller. The controller applies the boosted voltage to the gates of the first and second program load transistors when program data is set at a first logic level. The controller applies a voltage of about 0 V to the gate of the first program load transistor and an intermediate voltage lower than the voltage of the program power source and higher than 0 V to the gate of the second load transistor when the program data is set at a second logic level.

摘要翻译： 防止元件击穿的半导体集成电路包括布置在存储单元和编程电源之间的存储单元，串联连接的第一和第二程序负载晶体管，用于输出高于程序电压的电路板电压的升压电路 电源和控制器。 当程序数据被设置在第一逻辑电平时，控制器将升压电压施加到第一和第二编程负载晶体管的栅极。 当程序数据被设置时，控制器向第一编程负载晶体管的栅极施加大约0V的电压和低于编程电源电压的中间电压并且高于0V到第二负载晶体管的栅极 在第二逻辑级别。

公开(公告)号：US4905314A

公开(公告)日：1990-02-27

申请号：US184580

申请日：1988-04-21

申请人： Hideo Kato ,  Hiroshi Iwahashi ,  Masamichi Asano ,  Akira Narita ,  Shinichi Kikuchi

发明人： Hideo Kato ,  Hiroshi Iwahashi ,  Masamichi Asano ,  Akira Narita ,  Shinichi Kikuchi

IPC分类号： G11C17/00 ,  G11C5/14 ,  G11C16/06 ,  G11C16/30 ,  H01L21/822 ,  H01L21/8234 ,  H01L21/8247 ,  H01L27/04 ,  H01L27/088 ,  H01L27/10 ,  H01L29/788 ,  H01L29/792 ,  H02M3/07 ,  H03K3/356 ,  H03K17/06

CPC分类号： G11C5/145 ,  G11C16/30 ,  H03K17/06 ,  H03K3/356008

摘要： A sub-booster circuit for further stepping up an output voltage of a main booster circuit includes a first MOS transistor having a drain connected to the output terminal of the main booster circuit, and a gate connected to an input terminal of an object circuit, a second MOS transistor having a drain and a gate connected to the source of the first MOS transistor and a source connected to the input terminal of the object circuit, and a MOS capacitor having a first electrode connected to a connection node between the first and second MOS transistors and a second electrode connected to receive a clock pulse signal. A threshold voltage of the second MOS transistor is set to be larger in its absolute value than a threshold voltage of the first MOS transistor and the MOS capacitor has substantially the same threshold voltage as that of the second MOS transistor.

公开(公告)号：US4804929A

公开(公告)日：1989-02-14

申请号：US101667

申请日：1987-09-28

申请人： Hideo Kato ,  Hiroshi Iwahashi ,  Masamichi Asano ,  Akira Narita ,  Shinichi Kikuchi

发明人： Hideo Kato ,  Hiroshi Iwahashi ,  Masamichi Asano ,  Akira Narita ,  Shinichi Kikuchi

IPC分类号： H03K3/037 ,  H03K17/22 ,  H03L1/00 ,  H03B1/00

CPC分类号： H03K17/223

摘要： A control pulse generator according to the present invention includes a voltage generator for generating an output voltage proportional to a power supply voltage, an inverter for generating an inversion signal whose signal level is inverted when the output voltage from the voltage generator reaches a predetermined value, and a pulse signal generator for delaying a level inversion timing of the inversion signal by a predetermined delay time, and generating a control pulse having a width corresponding to the delay time. According to the control pulse generator with the above arrangement, the width of the control pulse can be determined on the basis of the delay time of the pulse signal generator, regardless of rise states of the power supply voltage. In addition, the height of the control pulse can be set at a desired value according to a supply voltage to the pulse signal generator, regardless of rise states of the supply voltage.

摘要翻译： 根据本发明的控制脉冲发生器包括用于产生与电源电压成比例的输出电压的电压发生器，用于产生当来自电压发生器的输出电压达到预定值时信号电平反转的反相信号的反相器， 以及脉冲信号发生器，用于将反转信号的电平反转定时延迟预定的延迟时间，并产生具有对应于延迟时间的宽度的控制脉冲。 根据具有上述配置的控制脉冲发生器，无论电源电压的上升状态如何，可以基于脉冲信号发生器的延迟时间来确定控制脉冲的宽度。 此外，无论电源电压的上升状态如何，控制脉冲的高度可以根据与脉冲信号发生器的电源电压设定在期望值。

公开(公告)号：US4794562A

公开(公告)日：1988-12-27

申请号：US94458

申请日：1987-09-09

申请人： Hideo Kato ,  Hiroshi Iwahashi ,  Masamichi Asano ,  Akira Narita ,  Shinichi Kikuchi

发明人： Hideo Kato ,  Hiroshi Iwahashi ,  Masamichi Asano ,  Akira Narita ,  Shinichi Kikuchi

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  G11C11/40

CPC分类号： H01L29/7883 ,  H01L27/115

摘要： In an electrically-erasable/programmable nonvolatile semiconductor memory device according to the invention, a one-bit memory cell is constituted by a series circuit of a selecting MOS transistor and a data storage MOS transistor. A floating gate electrode and a control gate electrode are formed in the data storage MOS transistor, One portion of the floating gate electrode is formed on a channel region of the data storage MOS transistor through a gate insulating film. The other portion of the floating gate electrode is formed on a drain region of the data storage MOS transistor through a gate insulating film, a portion of which is sufficiently thinner than the gate insulating film. One and the other portions of the floating gate electrode are structurally separated from each other but are electrically connected with each other on a field region. A control gate electrode having substantially the same shape as that of the floating gate electrode is formed thereon through a gate insulating film.

摘要翻译： 在根据本发明的电可擦除/可编程非易失性半导体存储器件中，一位存储单元由选择MOS晶体管和数据存储MOS晶体管的串联电路构成。 在数据存储MOS晶体管中形成浮栅电极和控制栅极，通过栅极绝缘膜在浮动栅极的一部分形成在数据存储MOS晶体管的沟道区上。 浮置栅电极的另一部分通过栅极绝缘膜形成在数据存储MOS晶体管的漏极区上，栅极绝缘膜的一部分比栅极绝缘膜充分薄。 浮栅电极的一个和另外部分在结构上彼此分离，但是在场区域上彼此电连接。 通过栅极绝缘膜在其上形成具有与浮栅电极基本相同形状的控制栅电极。