公开(公告)号：US5037777A

公开(公告)日：1991-08-06

申请号：US546801

申请日：1990-07-02

申请人： Thomas C. Mele ,  Wayne M. Paulson ,  Frank K. Baker ,  Michael P. Woo

发明人： Thomas C. Mele ,  Wayne M. Paulson ,  Frank K. Baker ,  Michael P. Woo

IPC分类号： H01L21/3105 ,  H01L21/768

CPC分类号： H01L21/76802 ,  H01L21/3105 ,  Y10S148/133 ,  Y10S148/161 ,  Y10S438/978

摘要： The disclosed invention is a method for fabricating a multi-layer semiconductor device using selective planarization. In accordance with one embodiment of the invention, conductive members are formed on a substrate and a first insulating layer is deposited onto the substrate and the conductive members. A second insulating layer, which has a lower flow temperature than the flow temperature of the first layer, is deposited onto the first layer. A photoresist mask is patterned and developed to form a window which exposes an area between the conductive members. The device is preferentially etched such that only the exposed areas of the second insulating layer are removed, leaving the first insulating layer intact. An anisotropic etch is used to remove portions of the first insulating layer, leaving spacers along the edges of the conductive members. The photoresist mask is removed and a heating step is performed which flows the remaining portions of the second insulating layer, but not the first layer. Since the second insulating material remains in only selective areas, the process is termed selective planarization. The method provides the benefit that areas which are to be etched to form contact hole or vias are not planarized, unlike existing blanket planarization methods, and a self-aligned contact is formed between the conductive members to the substrate.

摘要翻译： 所公开的发明是使用选择性平坦化制造多层半导体器件的方法。 根据本发明的一个实施例，导电构件形成在衬底上，并且第一绝缘层沉积到衬底和导电构件上。 具有比第一层的流动温度低的流动温度的第二绝缘层沉积到第一层上。 对光致抗蚀剂掩模进行图案化和显影以形成露出导电构件之间的区域的窗口。 优先蚀刻器件，使得只有第二绝缘层的暴露区域被去除，留下第一绝缘层完好无损。 使用各向异性蚀刻去除第一绝缘层的部分，沿着导电构件的边缘留下间隔物。 去除光致抗蚀剂掩模，并且执行流过第二绝缘层的剩余部分而不是第一层的加热步骤。 由于第二绝缘材料仅保留在选择性区域中，所以该过程称为选择性平面化。 该方法提供了与现有的覆盖平面化方法不同的是要被蚀刻以形成接触孔或通孔的区域不平坦化的优点，并且在导电构件与基底之间形成自对准接触。

公开(公告)号：US4997790A

公开(公告)日：1991-03-05

申请号：US566185

申请日：1990-08-13

申请人： Michael P. Woo ,  Thomas C. Mele ,  Wayne J. Ray ,  Wayne M. Paulson

发明人： Michael P. Woo ,  Thomas C. Mele ,  Wayne J. Ray ,  Wayne M. Paulson

IPC分类号： H01L21/28 ,  H01L21/3205 ,  H01L21/60 ,  H01L21/768

CPC分类号： H01L21/76897 ,  H01L21/76885 ,  H01L24/11 ,  Y10S148/105 ,  Y10S148/161

摘要： A self-aligned contact is formed in a multi-layer semiconductor device. In one form, conductive members are formed overlying a substrate material and a first insulating layer is deposited overlying the substrate material and the conductive members. A film of material is deposited on the first insulating layer and the film of material is patterned to form a sacrificial plug in an area where a contact is to be made. A second insulating layer is deposited on the device, and the device is made substantially planar. The second insulating layer is etched back to expose the sacrificial plug. The sacrificial plug is removed by selectively etching the device such that the first and second insulating layers are left substantially unaltered. An anisotropic etch of the device is performed to expose an area of the substrate material on which a contact is to be made, and to simultaneously form sidewall spacers along edges of the conductive members. A conductive layer is deposited onto the device and patterned, thereby forming a self-aligned contact.

摘要翻译： 在多层半导体器件中形成自对准接触。 在一种形式中，形成覆盖衬底材料的导电构件，并且沉积覆盖衬底材料和导电构件的第一绝缘层。 将材料膜沉积在第一绝缘层上，并且将材料膜图案化以在要进行接触的区域中形成牺牲插塞。 第二绝缘层沉积在器件上，并且器件基本上是平面的。 将第二绝缘层回蚀刻以暴露牺牲插头。 通过选择性地蚀刻该器件以使得第一绝缘层和第二绝缘层基本上保持不变而去除牺牲插塞。 执行器件的各向异性蚀刻以暴露要在其上形成触点的衬底材料的区域，并且同时沿着导电构件的边缘形成侧壁间隔物。 导电层沉积在器件上并图案化，从而形成自对准接触。

公开(公告)号：US20090242994A1

公开(公告)日：2009-10-01

申请号：US12059006

申请日：2008-03-31

申请人： Giri Nallapati ,  Sushama Davar ,  Robert E. Booth ,  Michael P. Woo ,  Mahbub M. Rashed

发明人： Giri Nallapati ,  Sushama Davar ,  Robert E. Booth ,  Michael P. Woo ,  Mahbub M. Rashed

IPC分类号： H01L21/8234 ,  H01L27/10

CPC分类号： H01L21/823462 ,  H01L21/823418 ,  H01L21/823456

摘要： A method includes forming a first transistor having a first gate dielectric thickness and a first source/drain extension depth, a second transistor having a second gate dielectric thickness and the first source/drain extension depth, and a third transistor having the second gate dielectric thickness and a second source/drain extension depth. The second source/drain extension depth is greater than the first source/drain extension depth. The second gate dielectric thickness is greater than the first gate dielectric thickness. The first transistor is used in a logic circuit. The third transistor is used in an I/O circuit. The second transistor is made without extra processing steps and is better than either the first or third transistor for coupling a power supply terminal to the logic circuit in a power-up mode and decoupling the power supply terminal from the logic circuit in a power-down mode.

摘要翻译： 一种方法包括形成具有第一栅介质厚度和第一源极/漏极延伸深度的第一晶体管，具有第二栅极介电厚度和第一源极/漏极延伸深度的第二晶体管，以及具有第二栅极介电厚度的第三晶体管 和第二源/漏扩展深度。 第二源极/漏极延伸深度大于第一源极/漏极延伸深度。 第二栅极电介质厚度大于第一栅极电介质厚度。 第一个晶体管用于逻辑电路。 第三个晶体管用于I / O电路。 第二晶体管是在没有额外的处理步骤的情况下制造的，并且优于用于在上电模式下将电源端子耦合到逻辑电路的第一或第三晶体管，并且在断电时将电源端子与逻辑电路解耦 模式。

公开(公告)号：US06686633B1

公开(公告)日：2004-02-03

申请号：US09653338

申请日：2000-08-31

申请人： Craig S. Lage ,  Mousumi Bhat ,  Yeong-Jyh Tom Lii ,  Andrew G. Nagy ,  Larry E. Frisa ,  Stanley M. Filipiak ,  David L. O'Meara ,  T. P. Ong ,  Michael P. Woo ,  Terry G. Sparks ,  Carol M. Gelatos

发明人： Craig S. Lage ,  Mousumi Bhat ,  Yeong-Jyh Tom Lii ,  Andrew G. Nagy ,  Larry E. Frisa ,  Stanley M. Filipiak ,  David L. O'Meara ,  T. P. Ong ,  Michael P. Woo ,  Terry G. Sparks ,  Carol M. Gelatos

IPC分类号： H01L2976

CPC分类号： H01L27/11 ,  H01L21/76801 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76895 ,  H01L21/76897 ,  H01L27/1104

摘要： A semiconductor device includes a memory array of static-random-access memory cells. The SRAM cells are formed using a process flow more closely associated with logic-type devices. The SRAM cells are formed using one semiconductor layer compared to at least three typically seen with SRAM cells. The SRAM cells include many features that allow its dimensions to be scaled to very small dimensions (less than 0.25 microns and possible down to 0.1 microns or even smaller). A unique process integration scheme allows formation of local interconnects (522 and 524), wherein each local interconnect (522, 524) cross couples the inverters of the SRAM and is formed within a single opening (70). Also, interconnect portions (104) of word lines are laterally offset from silicon portions (36) of the same word line, so that the interconnect portions do not interfere with bit line connections.

摘要翻译： 半导体器件包括静态随机存取存储器单元的存储器阵列。 使用与逻辑型器件更紧密相关联的工艺流程来形成SRAM单元。 SRAM单元使用一个半导体层形成，与至少三个SRAM单元相似。 SRAM单元包括许多特征，允许其尺寸缩放到非常小的尺寸（小于0.25微米，并且可能低至0.1微米甚至更小）。 独特的过程集成方案允许形成局部互连（522和524），其中每个局部互连（522,524）交叉耦合SRAM的反相器并形成在单个开口（70）内。 此外，字线的互连部分（104）横向偏离同一字线的硅部分（36），使得互连部分不干扰位线连接。

公开(公告)号：US06440805B1

公开(公告)日：2002-08-27

申请号：US09516970

申请日：2000-02-29

申请人： Xiaodong Wang ,  Michael P. Woo ,  Craig S. Lage ,  Hong Tian

发明人： Xiaodong Wang ,  Michael P. Woo ,  Craig S. Lage ,  Hong Tian

IPC分类号： H01L21336

CPC分类号： H01L21/761 ,  H01L21/26533 ,  H01L21/76224

摘要： A semiconductor device and its method of fabrication are disclosed. The method includes forming a first well region in a semiconductor substrate. The semiconductor substrate includes a first doped region below the first well region. The first well region and the first doped region are doped with a first type dopant and the first well region is electrically connected to the first doped region. An isolation region is formed between the first well region and the first doped region. The isolation region is electrically connected to a second well region. The isolation region and the second well region are doped with a second dopant type The second dopant type is opposite the first dopant type. In one embodiment, the first type dopant includes a p-type dopant, and the second type dopant includes an n-type dopant. The method may further include, forming a second doped region within the first well region and below the isolation region. A third doped region with the first type dopant may be formed over the isolation region. The method may further include forming a gate electrode over the semiconductor substrate, forming source/drain regions adjacent the gate electrode and forming a protective charge recombination region below the gate electrode and the source/drain regions.

摘要翻译： 公开了一种半导体器件及其制造方法。 该方法包括在半导体衬底中形成第一阱区。 半导体衬底包括在第一阱区下面的第一掺杂区。 第一阱区域和第一掺杂区域掺杂有第一类型掺杂剂，并且第一阱区域电连接到第一掺杂区域。 在第一阱区和第一掺杂区之间形成隔离区。 隔离区电连接到第二阱区。 隔离区域和第二阱区域掺杂有第二掺杂剂类型。第二掺杂剂类型与第一掺杂剂类型相反。 在一个实施例中，第一类型掺杂剂包括p型掺杂剂，第二类掺杂剂包括n型掺杂剂。 该方法还可以包括：在第一阱区域内和隔离区域下方形成第二掺杂区域。 可以在隔离区域上形成具有第一类型掺杂剂的第三掺杂区域。 该方法还可以包括在半导体衬底上形成栅电极，形成与栅电极相邻的源/漏区，并在栅电极和源极/漏极区之下形成保护电荷复合区。

公开(公告)号：US06184073B2

公开(公告)日：2001-02-06

申请号：US08997714

申请日：1997-12-23

申请人： Craig S. Lage ,  Mousumi Bhat ,  Yeong-Jyh Tom Lii ,  Andrew G. Nagy ,  Larry E. Frisa ,  Stanley M. Filipiak ,  David L. O'Meara ,  T. P. Ong ,  Michael P. Woo ,  Terry G. Sparks ,  Carol M. Gelatos

发明人： Craig S. Lage ,  Mousumi Bhat ,  Yeong-Jyh Tom Lii ,  Andrew G. Nagy ,  Larry E. Frisa ,  Stanley M. Filipiak ,  David L. O'Meara ,  T. P. Ong ,  Michael P. Woo ,  Terry G. Sparks ,  Carol M. Gelatos

IPC分类号： H01L218234

CPC分类号： H01L27/11 ,  H01L21/76801 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76895 ,  H01L21/76897 ,  H01L27/1104

摘要： A semiconductor device includes a memory array of static-random-access memory cells. The SRAM cells are formed using a process flow more closely associated with logic-type devices. The SRAM cells are formed using one semiconductor layer compared to at least three typically seen with SRAM cells. The SRAM cells include many features that allow its dimensions to be scaled to very small dimensions (less than 0.25 microns and possible down to 0.1 microns or even smaller). A unique process integration scheme allows formation of local interconnects (522 and 524), wherein each local interconnect (522, 524) cross couples the inverters of the SRAM and is formed within a single opening (70). Also, interconnect portions (104) of word lines are laterally offset from silicon portions (36) of the same word line, so that the interconnect portions do not interfere with bit line connections.

摘要翻译： 半导体器件包括静态随机存取存储器单元的存储器阵列。 使用与逻辑型器件更紧密相关联的工艺流程来形成SRAM单元。 SRAM单元使用一个半导体层形成，与至少三个SRAM单元相似。 SRAM单元包括许多特征，允许其尺寸缩放到非常小的尺寸（小于0.25微米，并且可能低至0.1微米甚至更小）。 独特的过程集成方案允许形成局部互连（522和524），其中每个局部互连（522,524）交叉耦合SRAM的反相器并形成在单个开口（70）内。 此外，字线的互连部分（104）横向偏离同一字线的硅部分（36），使得互连部分不干扰位线连接。

公开(公告)号：US06037246A

公开(公告)日：2000-03-14

申请号：US715303

申请日：1996-09-17

申请人： Mousumi Bhat ,  Mark D. Hall ,  Arkalgud R. Sitaram ,  Michael P. Woo

发明人： Mousumi Bhat ,  Mark D. Hall ,  Arkalgud R. Sitaram ,  Michael P. Woo

IPC分类号： H01L21/768 ,  H01L21/4763

CPC分类号： H01L21/76805 ,  H01L21/76831 ,  H01L21/76895

摘要： Electrical shorts and leakage paths are virtually eliminated by recessing conductive nodules (52) away from a conductor (72) or not forming the conductive nodules at all. In one embodiment, the refractory metal containing material (52) is recessed from the edge of the opening (32). When forming a nitride layer (54) within the opening (32), conductive nodules (52) are formed from a portion of the refractory metal containing material (20) such that the conductive modules (52) lie within the recession (42). In another embodiment, an oxide layer (82, 102) is formed adjacent to the refractory metal containing material (20) before forming a nitride layer (84, 112).

摘要翻译： 实际上通过使导电结节（52）远离导体（72）凹陷或完全不形成导电结节来消除电短路和漏电路径。 在一个实施例中，含难熔金属材料（52）从开口（32）的边缘凹进。 当在开口（32）内形成氮化物层（54）时，导电结核（52）由含难熔金属材料（20）的一部分形成，使得导电模块（52）位于凹陷（42）内。 在另一个实施例中，在形成氮化物层（84,112）之前，邻近难熔金属材料（20）形成氧化物层（82,102）。

公开(公告)号：US06291888B1

公开(公告)日：2001-09-18

申请号：US09461251

申请日：1999-12-15

申请人： Mousumi Bhat ,  Mark D. Hall ,  Arkalgud R. Sitaram ,  Michael P. Woo

发明人： Mousumi Bhat ,  Mark D. Hall ,  Arkalgud R. Sitaram ,  Michael P. Woo

IPC分类号： H01L214763

CPC分类号： H01L21/76805 ,  H01L21/76831 ,  H01L21/76895

摘要： Electrical shorts and leakage paths are virtually eliminated by recessing conductive nodules (52) away from a conductor (72) or not forming the conductive nodules at all. In one embodiment, the refractory metal containing material (52) is recessed from the edge of the opening (32). When forming a nitride layer (54) within the opening (32), conductive nodules (52) are formed from a portion of the refractory metal containing material (20) such that the conductive nodules (52) lie within the recession (42). In another embodiment, an oxide layer (82, 102) is formed adjacent to the refractory metal containing material (20) before forming a nitride layer (84, 112).

摘要翻译： 实际上通过使导电结节（52）远离导体（72）凹陷或完全不形成导电结节来消除电短路和漏电路径。 在一个实施例中，含难熔金属材料（52）从开口（32）的边缘凹进。 当在开口（32）内形成氮化物层（54）时，导电结核（52）由含难熔金属材料（20）的一部分形成，使得导电结核（52）位于凹陷（42）内。 在另一个实施例中，在形成氮化物层（84,112）之前，邻近难熔金属材料（20）形成氧化物层（82,102）。

公开(公告)号：US5381040A

公开(公告)日：1995-01-10

申请号：US147861

申请日：1993-08-24

申请人： Shih W. Sun ,  Michael P. Woo

发明人： Shih W. Sun ,  Michael P. Woo

IPC分类号： H01L21/768 ,  H01L29/44 ,  H01L23/48 ,  H01L29/46

CPC分类号： H01L21/76802

摘要： A contact between a heavily-doped region in the substrate and metal is made via a hole in a thick oxide layer and a polysilicon layer. The polysilicon layer is first etched to form a hole for establishing a mask for the eventual contact hole. Prior to forming the contact hole, a sidewall spacer of polysilicon is formed in the hole in the polysilicon layer. A thin oxide layer over the polysilicon layer is used for convenient end point detection during the formation of the polysilicon sidewall spacers. The sidewall spacer reduces the bore dimension of the hole in the polysilicon used for the mask for forming the contact hole. A hole is then etched in the thick oxide which is sloped and which has a bore dimension determined by the hole in the polysilicon which is reduced due to the sidewall spacer. The heavily-doped region, the contact hole, and the remaining polysilicon are coated with a barrier. The contact hole is then filled with a conductive material which also coats the barrier. The resulting conductive material, barrier, and polysilicon, are conveniently selectively etched in a single process step. The contact adheres well because polysilicon is in contact with the thick oxide in the locations where there is going to applied any physical stress, such as a bonding pad.

摘要翻译： 衬底中的重掺杂区域和金属之间的接触通过厚氧化物层和多晶硅层中的孔制成。 首先蚀刻多晶硅层以形成用于建立用于最终接触孔的掩模的孔。 在形成接触孔之前，在多晶硅层的孔中形成多晶硅的侧壁间隔物。 在多晶硅层的形成过程中，多晶硅层上的薄氧化层用于方便的端点检测。 侧壁间隔件减小了用于形成接触孔的掩模用的多晶硅中的孔的孔尺寸。 然后在厚的氧化物中蚀刻一个孔，该氧化物是倾斜的，并且具有由多晶硅中的孔确定的孔尺寸，其由于侧壁间隔而减小。 重掺杂区域，接触孔和剩余的多晶硅被涂覆有屏障。 接触孔然后用也涂覆屏障的导电材料填充。 所得到的导电材料，阻挡层和多晶硅在单个工艺步骤中方便地被选择性地蚀刻。 接触良好，因为多晶硅在要施加任何物理应力的位置（如焊盘）与厚氧化物接触。

公开(公告)号：US5158910A

公开(公告)日：1992-10-27

申请号：US618204

申请日：1990-11-26

申请人： Kent J. Cooper ,  Michael P. Woo ,  Wayne J. Ray

发明人： Kent J. Cooper ,  Michael P. Woo ,  Wayne J. Ray

IPC分类号： H01L21/60 ,  H01L21/768

CPC分类号： H01L21/76897 ,  H01L21/76885 ,  Y10S148/106

摘要： Self-aligned and/or isolated contacts are formed in a semiconductor device, while simultaneously providing device planarization. In one form, an imagable material is deposited directly on a substrate material. The imagable material is patterned to form a sacrifical plug on a portion of the substrate material. A substantially planar insulating layer is then deposited overlying the substrate material. The plug formed of the imagable material is then removed, thereby exposing a portion of the substrate material and defining a contact opening. A conductive layer is deposited and patterned to complete formation of a contact.

摘要翻译： 在半导体器件中形成自对准和/或隔离的触点，同时提供器件平面化。 在一种形式中，可成像材料直接沉积在基底材料上。 可成像材料被图案化以在基底材料的一部分上形成牺牲塞。 然后将基本平坦的绝缘层沉积在衬底材料上。 然后移除由可成像材料形成的插头，从而露出基板材料的一部分并限定接触开口。 导电层被沉积并图案化以完成接触的形成。