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公开(公告)号：US4157587A
公开(公告)日：1979-06-05
申请号：US863095
申请日：1977-12-22
申请人： Thomas F. Joyce , Thomas O. Holtey
发明人： Thomas F. Joyce , Thomas O. Holtey
CPC分类号： G06F12/123 , G06F12/0862 , F02B2075/027 , G06F2212/6022
摘要： A data processing system includes a plurality of system units all connected in common to a system bus. The system units include a central processor (CPU), a memory system and a high speed buffer or cache system. The cache system is word oriented and comprises a directory, a data buffer and associated control logic. The CPU requests data words by sending a main memory address of the requested data word to the cache system. If the cache does not have the information, apparatus in the cache requests the information from main memory, and in addition, the apparatus requests additional information from consecutively higher addresses. If main memory is busy, the cache has apparatus to request fewer words.
摘要翻译： 数据处理系统包括多个系统单元，它们都共同连接到系统总线。 系统单元包括中央处理器（CPU），存储器系统和高速缓冲器或缓存系统。 缓存系统是面向字的，包括一个目录，一个数据缓冲器和相关的控制逻辑。 CPU通过将请求的数据字的主存储器地址发送到高速缓存系统来请求数据字。 如果高速缓存不具有信息，则高速缓存中的装置请求来自主存储器的信息，此外，该装置从连续更高的地址请求附加信息。 如果主存储器正忙，则缓存器具有要求较少字的设备。
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2.发明授权
公开(公告)号：US4161024A
公开(公告)日：1979-07-10
申请号：US863097
申请日：1977-12-22
申请人： Thomas F. Joyce , Thomas O. Holtey
发明人： Thomas F. Joyce , Thomas O. Holtey
CPC分类号： G06F12/0884
摘要： A data processing system having a system bus; a plurality of system units including a main memory, a cache memory, a central processing unit (CPU) and a communications controller all connected in parallel to the system bus. The controller operates to supervise interconnection between the units via the system bus to transfer data therebetween, and the CPU includes a memory request device for generating data requests in response to the CPU. The cache memory includes a private interface connecting the CPU to the cache memory for permitting direct transmission of data requests from the CPU to the cache memory and direct transmission of requested data from the cache memory to the CPU; a cache directory and data buffer for evaluating the data requests to determine when the requested data is not present in the cache memory; and a system bus interface connecting the cache memory to the system bus for obtaining CPU requested data not found in the cache memory from the main memory via the system bus in response to the cache directory and data buffer. The cache memory may also include replacement and update apparatus for determining when the system bus is transmitting data to be written into a specific address in main memory and for replacing the data in a corresponding specific address in the cache memory with the data then on the system bus.
摘要翻译： 一种具有系统总线的数据处理系统; 多个系统单元，包括主系统总线并联的主存储器，高速缓存存储器，中央处理单元（CPU）和通信控制器。 控制器通过系统总线来监控单元之间的互连，以在其间传输数据，并且CPU包括用于响应于CPU产生数据请求的存储器请求装置。 高速缓冲存储器包括将CPU连接到高速缓冲存储器的专用接口，用于允许从CPU向高速缓存存储器的数据请求的直接传输，并将所请求的数据从缓存存储器直接发送到CPU; 缓存目录和数据缓冲器，用于评估数据请求以确定所请求的数据何时不存在于高速缓冲存储器中; 以及系统总线接口，其将所述高速缓冲存储器连接到所述系统总线，用于响应于所述高速缓存目录和数据缓冲器，经由所述系统总线从所述主存储器获得在所述高速缓冲存储器中未找到的CPU请求 高速缓冲存储器还可以包括替换和更新装置，用于确定系统总线何时正在发送要写入主存储器中的特定地址的数据，并且用数据然后在系统上替换高速缓冲存储器中相应的特定地址中的数据 总线。
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3.发明授权
公开(公告)号：US4214303A
公开(公告)日：1980-07-22
申请号：US863093
申请日：1977-12-22
CPC分类号： G06F12/0862 , G06F12/123 , F02B2075/027
摘要： A word oriented data processing system includes a plurality of system units all connected in common to a system bus. Included are a central processor unit (CPU), a memory system and a high speed buffer or cache system. The cache system is also coupled to the CPU. The cache includes an address directory and a data store with each address location of directory addressing its respective word in data store. The CPU requests a word of cache by sending a memory request to cache which includes a memory address location. If the requested word is stored in the data store, then it is sent to the CPU. If the word is not stored in cache, the cache requests the word of memory. When the cache receives the word from memory, the word is sent to the CPU and also stored in the data store.
摘要翻译： 面向字的数据处理系统包括多个系统单元，其全部共同连接到系统总线。 包括中央处理器单元（CPU），存储器系统和高速缓冲器或缓存系统。 缓存系统也耦合到CPU。 高速缓存包括地址目录和数据存储，其中目录的每个地址位置在数据存储器中寻址其相应的字。 CPU通过发送包含存储器地址位置的高速缓存的存储器请求来请求高速缓存字。 如果请求的字存储在数据存储中，则发送到CPU。 如果该字未存储在高速缓存中，则缓存请求内存字。 当缓存从存储器接收到该字时，该字被发送到CPU并存储在数据存储器中。
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公开(公告)号：US4167782A
公开(公告)日：1979-09-11
申请号：US863092
申请日：1977-12-22
CPC分类号： G06F12/0862 , G06F12/0802 , G06F12/0831 , G06F12/123 , F02B2075/027
摘要： A data processing system includes a plurality of system units all connected in common to a system bus. Included are a main memory system and a high speed buffer or cache store. System units communicate with each other over the system bus. Apparatus in the cache store monitors each communication between system units to determine if it is a communication from a system unit to main memory which will update a word location in main memory. If that word location is also stored in cache then the word location in cache will be updated in addition to the word location in main memory.
摘要翻译： 数据处理系统包括多个系统单元，它们都共同连接到系统总线。 包括主存储系统和高速缓存或缓存存储。 系统单元通过系统总线相互通信。 高速缓存存储器中的装置监视系统单元之间的每个通信，以确定它是否是从系统单元到主存储器的通信，其将更新主存储器中的字位置。 如果该字位置也存储在高速缓存中，除了主存储器中的单词位置之外，高速缓存中的单词位置将被更新。
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公开(公告)号：US4195342A
公开(公告)日：1980-03-25
申请号：US863098
申请日：1977-12-22
申请人： Thomas F. Joyce , Thomas O. Holtey
发明人： Thomas F. Joyce , Thomas O. Holtey
CPC分类号： G06F12/0886 , G06F2212/601
摘要： In a data processing system which includes a plurality of system units such as a central processing unit (CPU), main memory, and cache memory all connected in common to a system bus and communicating with each other via the system bus, and also having a private CPU-cache memory interface for permitting direct cache memory read access by the CPU, a multi-configurable cache store control unit for permitting cache memory to operate in any of the following word modes:1. Single pull banked;2. Double pull banked;3. Single pull interleaved;4. Double pull interleaved.The number of words read is a function of the main store configuration and the amount of memory interference from I/O controllers and other subsystems. The number ranges from one to four under the various conditions.
摘要翻译： 在包括诸如中央处理单元（CPU），主存储器和高速缓冲存储器的多个系统单元的数据处理系统中，所有这些系统单元共同地连接到系统总线并且经由系统总线彼此通信，并且还具有 专用CPU缓存存储器接口，用于允许CPU直接高速缓存存储器读取访问;多可配置高速缓存存储控制单元，用于允许高速缓冲存储器以任何以下字模式操作：1.单拉行; 双拉银行; 单拉交错; 双拉插拔。 读取的字数是主存储配置和I / O控制器和其他子系统的存储器干扰量的函数。 在各种条件下，数字范围从1到4。
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公开(公告)号：US5442704A
公开(公告)日：1995-08-15
申请号：US181691
申请日：1994-01-14
申请人： Thomas O. Holtey
发明人： Thomas O. Holtey
CPC分类号： G07F7/1008 , G06Q20/341 , G06Q20/3576
摘要： A secure memory card includes a microprocessor on a single semiconductor chip which interconnects through an internal bus to a number of non-volatile addressable memory chips. The microprocessor includes an addressable non-volatile memory for storing information including a number of key values and program instruction information. Each chip's memory is organized into a number of blocks, each block including a number of rows of byte locations. Each row of each block further includes a lock bit location, the total number of which provide storage for a lock value uniquely coded to utilize a predetermined characteristic of the memory to ensure data protection. Each memory chip is constructed to include security control logic circuits which include a security access control unit and a volatile access control memory containing a plurality of access control storage elements. Under the control of a predetermined set of instructions, the security access control unit performs a predetermined key validation operation by comparing key values against the bit contents of lock bit locations read out a bit at a time during an authentication procedure with a host computer. After the successful performance of the key validation procedure, the microprocessor sets one of the storage elements of the volatile access control memory for enabling user access to block data.
摘要翻译： 安全存储卡包括在单个半导体芯片上的微处理器，其通过内部总线与多个非易失性可寻址存储器芯片互连。 微处理器包括可寻址的非易失性存储器，用于存储包括多个键值和程序指令信息的信息。 每个芯片的存储器被组织成多个块，每个块包括多个字节位置行。 每个块的每一行还包括锁定位置，其总数为唯一编码的锁值提供存储以利用存储器的预定特性以确保数据保护。 每个存储器芯片被构造为包括安全控制逻辑电路，其包括安全访问控制单元和包含多个访问控制存储元件的易失性访问控制存储器。 在预定的一组指令的控制下，安全访问控制单元通过将密钥值与在主计算机的认证过程期间一次读出的锁定位位置的位内容进行比较来执行预定的密钥验证操作。 在成功执行密钥验证过程之后，微处理器设置易失性访问控制存储器的存储元件之一，以使用户能够访问块数据。
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公开(公告)号：US4945473A
公开(公告)日：1990-07-31
申请号：US051084
申请日：1987-05-15
摘要： A communications controller interface for emulating the previous system employing a plurality of line units in which data is transmitted and received. The interface includes a microprocessor-controlled interface control unit having an interface memory having a plurality of addressable storage locations. The interface memory is mapped by dividing it into a number of groups of locations corresponding to the number of communication lines with each group of locations being subdivided into further locations including a location for storage of receive data, a location for storage of transmit data, and a control location. There are a number of control elements each for generating a sequence of signals for different tasks to be performed by the interface control unit. These control elements are interconnected to the interface control unit and to the interface memory so that the multi-line communications unit is able to access different ones of the control locations for updating the status of the lines and further enabling the microprocessor-controlled interface control unit to transfer data to and from the transmit data and receive data locations of the lines in the predetermined sequence consistent with the status.
摘要翻译： 一种通信控制器接口，用于仿真先前系统，采用多个发送和接收数据的线路单元。 接口包括微处理器控制的接口控制单元，其具有具有多个可寻址存储位置的接口存储器。 通过将接口存储器划分成与通信线路数量相对应的多个位置组，将每组位置细分为另外的位置，包括用于存储接收数据的位置，用于存储发送数据的位置，以及 控制位置。 存在多个控制元件，用于生成用于由接口控制单元执行的不同任务的信号序列。 这些控制元件互连到接口控制单元和接口存储器，使得多线通信单元能够访问不同的控制位置以更新线路的状态，并且进一步启用微处理器控制的接口控制单元 将数据传输到发送数据和从发送数据传送数据，并以与状态一致的预定顺序接收线路的数据位置。
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公开(公告)号：US4633244A
公开(公告)日：1986-12-30
申请号：US537929
申请日：1983-09-30
CPC分类号： H01J29/48 , G09G1/20 , H01J2229/507
摘要： A high definition page display system for graphics and text utilizing multiple beams in a CRT is disclosed. Information for the several lines which are written simultaneously is made available in parallel. The invention is described in terms of a character set and text generation, but the same principles apply to any other graphic or bit map and to storage in ROMs or loadable RAMs. Each beam of a multiple CRT tube is biased to generate a portion of a character or graphic as it scans across the tube. It takes 12 lines to scan a character with a N-beam tube, 12 over N character scans are therefore required. With the same scanning speed as with a single beam, this factor can be used to increase definition (i.e. number of lines). Also the advantage of multiple beams can be used to reduce scanning speed, if this is useful to improve brightness or spot definition, or to increase the number of dots per line. Reduced scanning speed can also reduce costs, particularly if it brings the scan rate in line with standard components available commerically. Another way to use the advantages would be higher refresh rates.
摘要翻译： 公开了一种用于在CRT中使用多个光束的图形和文本的高清晰度页面显示系统。 同时写入的几条线的信息可以并行提供。 根据字符集和文本生成描述本发明，但是相同的原理适用于任何其他图形或位图，并且存储在ROM或可加载RAM中。 多个CRT管的每个光束被偏压以在其穿过管扫描时产生字符或图形的一部分。 需要12行扫描带有N光束管的字符，因此需要12个N字符扫描。 以与单个波束相同的扫描速度，该因子可用于增加定义（即线数）。 此外，如果这对于提高亮度或光斑定义有用，或者增加每行的点数，则可以使用多个光束的优点来降低扫描速度。 降低扫描速度也可以降低成本，特别是如果扫描速率符合标准组件可商用。 另一种使用优势的方法是更高的刷新率。
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9.发明授权Communications subsystem having a self-latching data monitor and storage device 失效通信子系统具有自锁数据监视器和存储设备
公开(公告)号：US4393461A
公开(公告)日：1983-07-12
申请号：US194311
申请日：1980-10-06
CPC分类号： G06F13/385
摘要： A communications subsystem having a microprocessor coupled to an address bus and a data bus includes a latching register also coupled to the address bus and the data bus. The latching register is responsive to signals from the data bus and address bus for storing bits representative of a direct connect mode, a clear to send mode, and a bit oriented or byte control protocol mode.
摘要翻译： 具有耦合到地址总线和数据总线的微处理器的通信子系统包括还耦合到地址总线和数据总线的锁存寄存器。 锁存寄存器响应来自数据总线和地址总线的信号，用于存储代表直接连接模式，清除发送模式和面向位或字节控制协议模式的位。
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10.发明授权Apparatus for verifying the integrity of information stored in a data processing system memory 失效用于验证存储在数据处理系统存储器中的信息的完整性的装置
公开(公告)号：US4038537A
公开(公告)日：1977-07-26
申请号：US643453
申请日：1975-12-22
CPC分类号： G06F11/1008 , G06F11/1076 , G11C29/52
摘要： A memory having a plurality of word locations, each having a bit location, includes a parity word in one of the word locations. Bit selector means selects a column of bits made up of like positioned bits in each of the word locations. All bits in a column are added together to indicate whether there is a successful parity check. Each such column is successively checked thereby verifying the integrity of the stored information on a column basis.
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