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53 条记录 (耗时 0.018 秒)

    Method of forming a metal silicide gate in a standard MOS process sequence
    2.
    发明授权
    Method of forming a metal silicide gate in a standard MOS process sequence 有权
    在标准MOS工艺序列中形成金属硅化物栅的方法

    公开(公告)号：US06821887B2

    公开(公告)日：2004-11-23

    申请号：US10391243

    申请日：2003-03-18

    申请人： Karsten Wieczorek ,  Stephan Kruegel ,  Manfred Horstmann ,  Thomas Feudel

    发明人： Karsten Wieczorek ,  Stephan Kruegel ,  Manfred Horstmann ,  Thomas Feudel

    IPC分类号： H01L21302

    CPC分类号： H01L21/28194 ,  H01L21/28097 ,  H01L29/511 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/665 ,  H01L29/66507

    摘要： The polysilicon gate electrode of a MOS transistor may be substantially completely converted into a metal silicide without sacrificing the drain and source junctions in that a thickness of the polysilicon layer, for forming the gate electrode, is targeted to be substantially converted into metal silicide in a subsequent silicidation process. The gate electrode, substantially comprised of metal silicide, offers high conductivity even at critical dimensions in the deep sub-micron range, while at the same time the effect of polysilicon gate depletion is significantly reduced. Manufacturing of the MOS transistor, having the substantially fully-converted metal silicide gate electrode, is essentially compatible with standard MOS process technology.

    摘要翻译： MOS晶体管的多晶硅栅电极可以基本上完​​全转变为金属硅化物，而不牺牲漏极和源极结，因为用于形成栅电极的多晶硅层的厚度被靶向为基本上转化为金属硅化物 随后的硅化工艺。 基本上由金属硅化物组成的栅极电极甚至在深亚微米范围内的临界尺寸下也提供高导电性，同时多晶硅栅极耗尽的效果显着降低。 具有基本上完全转换的金属硅化物栅电极的MOS晶体管的制造基本上与标准MOS工艺技术相兼容。

    Methods of forming drain/source extension structures of a field effect transistor using a doped high-k dielectric layer
    4.
    发明授权
    Methods of forming drain/source extension structures of a field effect transistor using a doped high-k dielectric layer 失效
    使用掺杂的高k电介质层形成场效应晶体管的漏极/源延伸结构的方法

    公开(公告)号：US06849516B2

    公开(公告)日：2005-02-01

    申请号：US10442745

    申请日：2003-05-21

    申请人： Thomas Feudel ,  Manfred Horstmann ,  Karsten Wieczorek ,  Stephan Kruegel

    发明人： Thomas Feudel ,  Manfred Horstmann ,  Karsten Wieczorek ,  Stephan Kruegel

    IPC分类号： H01L21/225 ,  H01L21/336 ,  H01L29/78 ,  H01L21/3205

    CPC分类号： H01L29/6659 ,  H01L21/2253 ,  H01L29/665 ,  H01L29/7833

    摘要： According to one illustrative embodiment of the present invention, a method of forming a field effect transistor includes the formation of a doped high-k dielectric layer above a substrate including a gate electrode formed over an active region and separated therefrom by a gate insulation layer. A heat treatment is carried out with the substrate to diffuse dopants from the high-k dielectric layer into the active region to form extension regions. The high-k dielectric layer is patterned to form sidewall spacers at sidewalls of the gate electrode and an implantation process is carried out with the sidewall spacers as implantation mask to form source and drain regions.

    摘要翻译： 根据本发明的一个说明性实施例，形成场效应晶体管的方法包括在包括在有源区上形成并由栅极绝缘层分离的栅电极的衬底上形成掺杂的高k电介质层。 用衬底进行热处理以将掺杂剂从高k电介质层扩散到活性区域中以形成延伸区域。 图案化高k电介质层以在栅电极的侧壁处形成侧壁间隔物，并且以侧壁间隔物作为注入掩模进行注入工艺以形成源区和漏区。

    Method for manufacturing semiconductor device comprising SOI transistors and bulk transistors
    5.
    发明授权
    Method for manufacturing semiconductor device comprising SOI transistors and bulk transistors 有权
    包括SOI晶体管和体晶体管的半导体器件的制造方法

    公开(公告)号：US07955937B2

    公开(公告)日：2011-06-07

    申请号：US11560896

    申请日：2006-11-17

    申请人： Karsten Wieczorek ,  Manfred Horstmann ,  Thomas Feudel ,  Thomas Heller

    发明人： Karsten Wieczorek ,  Manfred Horstmann ,  Thomas Feudel ,  Thomas Heller

    IPC分类号： H01L21/331

    CPC分类号： H01L21/823481 ,  H01L21/76243 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/0922 ,  H01L27/1203 ,  H01L27/1207

    摘要： By forming bulk-like transistors in sensitive RAM areas of otherwise SOI-based CMOS circuits, a significant savings in valuable chip area may be achieved since the RAM areas may be formed on the basis of a bulk transistor configuration, thereby eliminating hysteresis effects that may typically be taken into consideration by providing transistors of increased transistor width or by providing body ties. Hence, the benefit of high switching speed may be maintained in speed-critical circuitry, such as CPU cores, while at the same time the RAM circuit may be formed in a highly space-efficient manner.

    摘要翻译： 通过在其它基于SOI的CMOS电路的敏感RAM区域中形成块状晶体管，可以实现有价值的芯片面积的显着节省，因为可以基于体晶体管配置形成RAM区域，从而消除可能 通常通过提供增加的晶体管宽度的晶体管或通过提供身体纽带来考虑。 因此，高速切换速度的好处可以保持在诸如CPU内核之类的速度关键电路中，同时可以以高空间效率的方式形成RAM电路。

    Method of manufacturing a field effect transistor
    8.
    发明授权
    Method of manufacturing a field effect transistor 有权
    制造场效应晶体管的方法

    公开(公告)号：US06806153B2

    公开(公告)日：2004-10-19

    申请号：US10462893

    申请日：2003-06-17

    申请人： Karsten Wieczorek ,  Manfred Horstmann ,  Thomas Feudel

    发明人： Karsten Wieczorek ,  Manfred Horstmann ,  Thomas Feudel

    IPC分类号： H01L21336

    CPC分类号： H01L29/6659 ,  H01L21/2022 ,  H01L21/26506 ,  H01L21/26513

    摘要： The present invention allows the manufacturing of field effect transistors with reduced thermal budget. A first amorphized region and a second amorphized region are formed in a substrate adjacent to the gate electrode by implanting ions of a non-doping element, the presence of which does not significantly alter the conductive properties of the substrate. The formation of the amorphized regions may be performed before or after the formation of a source region, a drain region, an extended source region and an extended drain region. The substrate is annealed to achieve solid phase epitaxial regrowth of the amorphized regions and to activate dopants in the source region, the drain region, the extended source region and the extended drain region.

    摘要翻译： 本发明允许制造具有降低的热预算的场效应晶体管。 第一非晶化区域和第二非晶区域通过注入非掺杂元素的离子形成在与栅电极相邻的衬底中，其不存在不会显着地改变衬底的导电性能。 非晶化区域的形成可以在形成源极区域，漏极区域，扩展源极区域和延伸的漏极区域之前或之后进行。 将衬底退火以实现非晶化​​区域的固相外延再生长并激活源极区域，漏极区域，扩展源极区域和延伸漏极区域中的掺杂剂。

    Method of forming lightly doped regions in a semiconductor device
    9.
    发明授权
    Method of forming lightly doped regions in a semiconductor device 有权
    在半导体器件中形成轻掺杂区域的方法

    公开(公告)号：US06410410B1

    公开(公告)日：2002-06-25

    申请号：US09852535

    申请日：2001-05-10

    申请人： Thomas Feudel ,  Manfred Horstmann ,  Karsten Wieczorek

    发明人： Thomas Feudel ,  Manfred Horstmann ,  Karsten Wieczorek

    IPC分类号： H01L21225

    CPC分类号： H01L29/6659 ,  H01L21/2255 ,  H01L29/42368 ,  H01L29/7833

    摘要： A method is disclosed in which a lightly doped region in a semiconductor layer is obtained by diffusing dopant atoms of a first and second type into the underlying semiconductor layer. Preferably, the method is applied to the formation of lightly doped source and drain regions in a field effect transistor so as to obtain a required gradual dopant concentration transition from the general region to the drain and source regions for avoiding the hot carrier effect. Advantageously, a diffusion of the dopant atoms is initiated during an oxidizing step in which the thickness of the gate insulation layer is increased at the edge portions thereof.

    摘要翻译： 公开了一种通过将第一和第二类型的掺杂剂原子扩散到下面的半导体层中而获得半导体层中的轻掺杂区域的方法。 优选地，该方法被应用于在场效应晶体管中形成轻掺杂的源极和漏极区域，以便获得从一般区域到漏极和源极区域所需的逐渐掺杂剂浓度跃迁，以避免热载流子效应。 有利地，掺杂剂原子的扩散在其栅极绝缘层的厚度在其边缘部分增加的氧化步骤期间开始。