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公开(公告)号：USRE37944E1
公开(公告)日：2002-12-31
申请号：US09434331
申请日：1999-11-05
申请人： Dennis A. Fielder , James H. Derbyshire , Peter B. Gillingham , Randy R. Torrance , Cormac M. O'Connell
发明人： Dennis A. Fielder , James H. Derbyshire , Peter B. Gillingham , Randy R. Torrance , Cormac M. O'Connell
IPC分类号： G06F1576
CPC分类号： G09G5/363 , G09G5/39 , G11C7/10 , G11C7/1048 , G11C11/4093 , G11C11/4096 , G11C2207/104
摘要： A single chip display processor comprised of a dynamic random access memory (DRAM) for storing at least one of graphics and video pixel data, a pixel data unit (PDU) for processing the pixel data, integrated in the same integrated circuit (IC) chip as the DRAM, the IC chip further comprising a massively parallel bus for transferring blocks of pixel data at the same time from the DRAM to the PDU, whereby the PDU can process the blocks of pixel data for subsequent display of processed pixel data.
摘要翻译： 一种单芯片显示处理器，包括用于存储图形和视频像素数据中的至少一个的动态随机存取存储器（DRAM），用于处理像素数据的像素数据单元（PDU），集成在同一集成电路（IC）芯片中 作为DRAM，IC芯片还包括用于从DRAM到PDU同时传送像素数据块的大规模并行总线，由此PDU可以处理像素数据块以用于随后显示经处理的像素数据。
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公开(公告)号：USRE44589E1
公开(公告)日：2013-11-12
申请号：US12819467
申请日：2010-06-21
发明人： Dennis A. Fielder , James H. Derbyshire , Peter B. Gillingham , Randy R. Torrance , Cormac M. O'Connell
CPC分类号： G09G5/363 , G09G5/39 , G11C7/10 , G11C7/1048 , G11C11/4093 , G11C11/4096 , G11C2207/104
摘要： A single chip display processor comprised of a dynamic random access memory (DRAM) for storing at least one of graphics and video pixel data, a pixel data unit (PDU) for processing the pixel data, integrated in the same integrated circuit (IC) chip as the DRAM, the IC chip further comprising a massively parallel bus for transferring blocks of pixel data at the same time from the DRAM to the PDU, whereby the PDU can process the blocks of pixel data for subsequent display of processed pixel data.
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公开(公告)号：USRE41565E1
公开(公告)日：2010-08-24
申请号：US11872353
申请日：2007-10-15
申请人： Dennis A. Fielder , Philip S. Shaer , James H. Derbyshire , Peter B. Gillingham , Randy R. Torrance , Cormac M. O'Connell
发明人： Dennis A. Fielder , James H. Derbyshire , Peter B. Gillingham , Randy R. Torrance , Cormac M. O'Connell
CPC分类号： G09G5/363 , G09G5/39 , G11C7/10 , G11C7/1048 , G11C11/4093 , G11C11/4096 , G11C2207/104
摘要： A single chip display processor comprised of a dynamic random access memory (DRAM) for storing at least one of graphics and video pixel data, a pixel data unit (PDU) for processing the pixel data, integrated in the same integrated circuit (IC) chip as the DRAM, the IC chip further comprising a massively parallel bus for transferring blocks of pixel data at the same time from the DRAM to the PDU, whereby the PDU can process the blocks of pixel data for subsequent display of processed pixel data.
摘要翻译： 一种单芯片显示处理器，包括用于存储图形和视频像素数据中的至少一个的动态随机存取存储器（DRAM），用于处理像素数据的像素数据单元（PDU），集成在同一集成电路（IC）芯片中 作为DRAM，IC芯片还包括用于从DRAM到PDU同时传送像素数据块的大规模并行总线，由此PDU可以处理像素数据块以用于随后显示经处理的像素数据。
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公开(公告)号：USRE40326E1
公开(公告)日：2008-05-20
申请号：US10264013
申请日：2002-10-04
申请人： Dennis A. Fielder , James H. Derbyshire , Peter B. Gillingham , Randy R. Torrance , Cormac M. O'Connell
发明人： Dennis A. Fielder , James H. Derbyshire , Peter B. Gillingham , Randy R. Torrance , Cormac M. O'Connell
CPC分类号： G09G5/363 , G09G5/39 , G11C7/10 , G11C7/1048 , G11C11/4093 , G11C11/4096 , G11C2207/104
摘要： A single chip display processor comprised of a dynamic random access memory (DRAM) for storing at least one of graphics and video pixel data, a pixel data unit (PDU) for processing the pixel data, integrated in the same integrated circuit (IC) chip as the DRAM, the IC chip further comprising a massively parallel bus for transferring blocks of pixel data at the same time from the DRAM to the PDU, whereby the PDU can process the blocks of pixel data for subsequent display of processed pixel data.
摘要翻译： 一种单芯片显示处理器，包括用于存储图形和视频像素数据中的至少一个的动态随机存取存储器（DRAM），用于处理像素数据的像素数据单元（PDU），集成在同一集成电路（IC）芯片中 作为DRAM，IC芯片还包括用于从DRAM到PDU同时传送像素数据块的大规模并行总线，由此PDU可以处理像素数据块以用于随后显示经处理的像素数据。
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公开(公告)号：US5715200A
公开(公告)日：1998-02-03
申请号：US682661
申请日：1996-10-01
申请人： Dennis A. Fielder , James H. Derbyshire , Peter B. Gillingham , Cormac M. O'Connell , Randall R. Torrance
发明人： Dennis A. Fielder , James H. Derbyshire , Peter B. Gillingham , Cormac M. O'Connell , Randall R. Torrance
CPC分类号： G11C7/1051 , G06F12/0893
摘要： A memory device with a dynamic random access memory (DRAM) having an array of a plurality of rows and columns of memory elements; a cache memory formed integrally with the DRAM and includinmg at least one register with a plurality of memory elements and connected in pitch-matched relation to the DRAM array, the number of memory elements in a row of the DRAM being n times the number of memory elements in the at least one register, n being an integer greater than or equal to 2; and a connector for connecting the at least one register to the DRAM, the connector for the at least one register being a bus having a width corresponding to the number of memory elements therein.
摘要翻译： PCT No.PCT / GB95 / 02780 Sec。 371日期：1996年10月1日 102（e）日期1996年10月1日PCT提交1995年11月29日PCT公布。 出版物WO96 / 17354 日期：1996年6月6日具有动态随机存取存储器（DRAM）的存储器件，具有存储元件的多个行和列的阵列; 与DRAM一体形成的高速缓冲存储器，并且包括至少一个具有多个存储元件的寄存器并以与音调匹配的关系连接到DRAM阵列，DRAM的一行中的存储器元件的数量是存储器数量的n倍 所述至少一个寄存器中的元素，n是大于或等于2的整数; 以及用于将至少一个寄存器连接到DRAM的连接器，用于至少一个寄存器的连接器是具有对应于其中的存储器元件的数量的宽度的总线。
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6.发明授权Method for transferring data associated with a read/write command between a processor and a reader circuit using a plurality of clock lines 失效使用多个时钟线在处理器和读取器电路之间传送与读取/写入命令相关联的数据的方法公开(公告)号：US06249827B1
公开(公告)日：2001-06-19
申请号：US08987328
申请日：1997-12-09
IPC分类号： G06F1304
CPC分类号： G11C7/109 , G06F13/4243 , G11C7/10 , G11C7/1012 , G11C7/1051 , G11C7/1057 , G11C7/106 , G11C7/1066 , G11C7/1072 , G11C7/1078 , G11C7/1087 , G11C7/22 , G11C2207/2254
摘要： A memory circuit with glitch-less transfer of timing information. In one embodiment, the invention is a memory circuit including a controller, multiple loads, a command link communicatively coupling the controller and the loads and a data link. The data link includes multiple data clocks and communicatively couples the controller and the multiple loads. In another embodiment, the invention transfers data between a memory controller and a RAM by coupling the controller and the RAM using a data bus and multiple clock lines. The invention transfers a read/write command from the controller to the RAM and then transfers data associated with the read/write command, clocking the data using one of the clock lines.
摘要翻译： 具有无故障传输定时信息的存储电路。 在一个实施例中，本发明是包括控制器，多个负载，通信地耦合控制器和负载的命令链路以及数据链路的存储器电路。 数据链路包括多个数据时钟，并且通信地耦合控制器和多个负载。 在另一个实施例中，本发明通过使用数据总线和多个时钟线耦合控制器和RAM来在存储器控制器和RAM之间传送数据。 本发明将读/写命令从控制器传送到RAM，然后传送与读/写命令相关的数据，使用其中一个时钟线为数据计时。
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7.发明授权Memory system having synchronous-link DRAM (SLDRAM) devices and controller 失效具有同步链路DRAM（SLDRAM）器件和控制器的存储器系统公开(公告)号：US06442644B1
公开(公告)日：2002-08-27
申请号：US09132158
申请日：1998-08-10
申请人： David B. Gustavson , David V. James , Hans A. Wiggers , Peter B. Gillingham , Cormac M. O'Connell , Bruce Millar , Jean Crepeau , Kevin J. Ryan , Terry R. Lee , Brent Keeth , Troy A. Manning , Donald N. North , Desi Rhoden , Henry Stracovsky , Yoshikazu Morooka
发明人： David B. Gustavson , David V. James , Hans A. Wiggers , Peter B. Gillingham , Cormac M. O'Connell , Bruce Millar , Jean Crepeau , Kevin J. Ryan , Terry R. Lee , Brent Keeth , Troy A. Manning , Donald N. North , Desi Rhoden , Henry Stracovsky , Yoshikazu Morooka
IPC分类号： G06F1200
CPC分类号： G11C7/1066 , G06F13/409 , G06F13/4243 , G11C7/10 , G11C7/1012 , G11C7/1051 , G11C7/1057 , G11C7/106 , G11C7/1072 , G11C7/1078 , G11C7/1087 , G11C7/109 , G11C7/22 , G11C2207/2254 , H05K1/0219 , H05K1/0246 , H05K2201/0715 , H05K2201/09236 , H05K2201/09254 , H05K2201/09309 , H05K2201/10022 , H05K2201/10159 , H05K2201/10689 , Y02D10/14 , Y02D10/151
摘要： A SLDRAM System is provided with a plurality of in-circuit, calibratable memory modules and a memory controller for issuing unicast and multicast command packets to the memory modules. Command packets are transmitted over a unidirectional command link that includes a complementary pair of command clock lines, a command FLAG line and a plurality of noncomplemented command bit lines. Each of the command clock lines, command bit lines and the FLAG line is a SLIO transmission line. Data transfer operations are carried out in response to the command packets over one or more bidirectional data links that each includes two complementary pairs of data clock lines, and a plurality of noncomplemented data bit lines. Each of the data clock lines and the data bit lines is a SLIO transmission line. Each SLIO transmission line is single-end terminated and preferably tapped into by way of stub resistors.
摘要翻译： SLDRAM系统配备有多个在线可校准存储器模块和用于向存储器模块发出单播和多播命令分组的存储器控制器。 命令分组通过单向命令链路发送，该单向命令链路包括一对互补的命令时钟线，命令FLAG线和多个未实现的命令位线。 每个命令时钟线，命令位线和FLAG线都是SLIO传输线。 响应于一个或多个双向数据链路上的命令分组执行数据传送操作，每个双向数据链路包括两对互补的数据时钟线对，以及多个未实现的数据位线。 每个数据时钟线和数据位线都是SLIO传输线。 每个SLIO传输线都是单端端接的，最好采用短截线电阻。
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公开(公告)号：US5033024A
公开(公告)日：1991-07-16
申请号：US453637
申请日：1989-12-20
申请人： Cormac M. O'Connell , Leonardus Pfennings, deceased , by Henricus J. Kunnen, executor , Peter H. Voss , Thomas J. Davies , Hans Ontrop , Cathal G. Phelan
发明人： Cormac M. O'Connell , Leonardus Pfennings, deceased , by Henricus J. Kunnen, executor , Peter H. Voss , Thomas J. Davies , Hans Ontrop , Cathal G. Phelan
CPC分类号： G11C29/846
摘要： An integrated matrix memory includes standard sub-blocks and a redundant block. Each of the standard sub-blocks has a fixed number of standard sub-blocks, and the redundant block has one or more redundant sub-blocks. For addressing there is provided a detector for the address of a faulty standard sub-block. In that case a redundant sub-block is selected. Selection is realized by way of a sub-bus which forms part of the data path. Thus, a redundant system is achieved in which delay is minimized.
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9.发明授权Integrated circuit including an input buffer circuit having NAND and NOR gates 失效集成电路，包括具有NAND和NOR门的输入缓冲电路
公开(公告)号：US5157284A
公开(公告)日：1992-10-20
申请号：US724099
申请日：1991-07-01
申请人： Cormac M. O'Connell , Peter H. Voss
发明人： Cormac M. O'Connell , Peter H. Voss
IPC分类号： G11C11/417 , G11C8/06 , H01L21/822 , H01L27/04
CPC分类号： G11C8/06
摘要： Using a NAND and a NOR gate as input gates provides a simple and efficient input buffer. In the input buffer circuit, a chip select signal is applied in inverted form to the NOR gate and in non-invented form to the NAND gate. The resulting input buffer is both simpler and faster than earlier circuits.
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公开(公告)号：US5040152A
公开(公告)日：1991-08-13
申请号：US265640
申请日：1988-11-01
申请人： Peter H. Voss , Leonardus C. M. G. Pfennings , Cormac M. O'Connell , Thomas J. Davies , Hans Ontrop , Cathal G. Phelan
发明人： Peter H. Voss , Leonardus C. M. G. Pfennings , Cormac M. O'Connell , Thomas J. Davies , Hans Ontrop , Cathal G. Phelan
IPC分类号： G11C11/41 , G11C5/02 , G11C8/12 , G11C11/401 , G11C11/408 , H01L27/10
摘要： A static RAM memory is optimized for speed. The memory is divided into major memory matrices and each major memory matrix is divided into memory blocks. The memory blocks are divided in groups that per group have address bits in common, which however are per group coupled to separate pads or sets of pads. These pads are interconnected on the package to common package pins.
摘要翻译： 静态RAM存储器针对速度进行了优化。 存储器分为主存储矩阵，每个主存储矩阵分为存储块。 存储器块被分组，每组具有共同的地址位，然而每个组耦合到单独的焊盘或焊盘组。 这些焊盘在封装上互连到公共封装引脚。
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