公开(公告)号：US4476734A

公开(公告)日：1984-10-16

申请号：US472900

申请日：1983-03-07

申请人： Thomas M. Banks ,  Raymond R. Ruckel ,  Samuel F. Spencer ,  John Q. Walker

发明人： Thomas M. Banks ,  Raymond R. Ruckel ,  Samuel F. Spencer ,  John Q. Walker

IPC分类号： G01N1/00 ,  G01N30/18 ,  G01N30/24 ,  G01N1/14

CPC分类号： G01N30/24 ,  G01N35/1095

摘要： The flushing of the syringe with a side port is performed by introducing a liquid solvent through the side port while the plunger is retracted from the barrel. At the completion of the flushing operation the plunger is fully inserted into the barrel expelling all the solvent except that in the needle. The needle is then inserted into the sample and the plunger is raised to withdraw the sample. With this arrangement, it is possible to take a 0.1 L sample and dispense it because of the solvent reserve in the barrel. Furthermore, the solvent reserved in the barrel provides a buffer so that sampled material does not contact the plunger or get into the annular space around the retracted plunger.

摘要翻译： 注射器侧面端口的冲洗是通过在柱塞从筒体缩回的同时引入液体溶剂通过侧端口进行的。 在冲洗操作完成时，柱塞完全插入桶中，除去针中的所有溶剂。 然后将针插入样品中，并将柱塞升起以抽出样品。 通过这种布置，可以取0.1L样品并由于桶中的溶剂储备而分配。 此外，保留在桶中的溶剂提供缓冲液，使得取样的材料不接触柱塞或进入回缩柱塞周围的环形空间。

公开(公告)号：US4869876A

公开(公告)日：1989-09-26

申请号：US605433

申请日：1984-04-30

申请人： Kenneth D. Arfman ,  Theodore J. Pillera, II ,  Raymond R. Ruckel ,  Allan C. Turits ,  John Q. Walker

发明人： Kenneth D. Arfman ,  Theodore J. Pillera, II ,  Raymond R. Ruckel ,  Allan C. Turits ,  John Q. Walker

IPC分类号： B01D15/08 ,  G01N30/30 ,  G01N30/46 ,  G01N30/54 ,  G01N30/88

CPC分类号： G01N30/30 ,  G01N2030/3038 ,  G01N2030/3046 ,  G01N2030/3084 ,  G01N2030/8804 ,  G01N30/461 ,  G01N30/466

摘要： A gas chromatography (GC) system includes a primary complete, independently-operable, self-contained GC system and a secondary, dependently-operable GC system. The primary and secondary systems have two independently controlled GC ovens. Injectors and detectors are supported by heater blocks or ovens mounted on the respective GC ovens and are connected to the electrical and pneumatic controls of the primary GC system. The injectors and detectors of the secondary GC system share operation of the primary GC system. GC columns can be mounted in each oven and operated completely independently or dependently in different ways. A separate power supply for the secondary oven is connectable to a separate circuit or power line in the user environment.

摘要翻译： 气相色谱（GC）系统包括主要完整的，可独立操作的独立GC系统和辅助可靠操作的GC系统。 主要和次要系统有两个独立控制的GC烤箱。 注射器和检测器由安装在相应GC炉上的加热器块或烤箱支撑，并连接到主GC系统的电气和气动控制。 二次GC系统的注射器和检测器共享主GC系统的操作。 GC色谱柱可以安装在每个烤箱中，完全独立或依赖于不同的方式进行操作。 用于二次烤箱的独立电源可连接到用户环境中的单独电路或电源线。

公开(公告)号：US20090265675A1

公开(公告)日：2009-10-22

申请号：US12103825

申请日：2008-04-16

申请人： John Q. Walker ,  Jeffrey P. Burleson ,  Scott A. Service ,  Steven L. Howard

发明人： John Q. Walker ,  Jeffrey P. Burleson ,  Scott A. Service ,  Steven L. Howard

IPC分类号： G06F17/50

CPC分类号： H01L27/0207 ,  H01L27/088 ,  H01L29/4238 ,  H01L29/78

摘要： A method for reducing variation in a desired property between transistors in an integrated circuit that is fabricated with a given process. The process is characterized to form a mathematical model that associates changes in polysilicon density and active density in the integrate circuit with changes in gate length and gate width in the transistors, and associates changes in the gate length and the gate width to the desired property. The integrated circuit is laid out with space sufficient to adjust the gate length and the gate width of the transistors without violating design rules of the transistors. The integrated circuit is divided into portions, and for at least a given one of the portions of the integrated circuit, the polysilicon density and the active density of the given portion is measured. For at least one of the transistors in the given portion of the integrated circuit, at least one of the gate length and the gate width of the transistor is selectively adjusted according to the mathematical model, based on at least one of the polysilicon density and the active density of the given portion, to reduce variation in the desired property between the transistors in the integrated circuit.

摘要翻译： 一种用于减少用给定工艺制造的集成电路中的晶体管之间期望特性的变化的方法。 该过程的特征在于形成数学模型，其将积分电路中的多晶硅密度和有源密度的变化与晶体管中的栅极长度和栅极宽度的变化相关联，并且将栅极长度和栅极宽度的变化关联到期望的性质。 集成电路布置有足以调节晶体管的栅极长度和栅极宽度的空间，而不违反晶体管的设计规则。 集成电路被分成多个部分，并且对于集成电路的至少一个给定的部分，测量给定部分的多晶硅密度和有效密度。 对于集成电路的给定部分中的至少一个晶体管，根据数学模型，基于多晶硅密度和晶体管的至少一个来选择性地调节晶体管的栅极长度和栅极宽度中的至少一个 给定部分的有效密度，以减少集成电路中的晶体管之间的期望特性的变化。

公开(公告)号：US06825546B1

公开(公告)日：2004-11-30

申请号：US10035346

申请日：2001-12-28

申请人： John Q. Walker ,  Todd A. Randazzo

发明人： John Q. Walker ,  Todd A. Randazzo

IPC分类号： H01L2993

CPC分类号： H01L29/93

摘要： A varactor is formed with a semiconductor junction having a retrograde dopant concentration profile in a depletion region. The retrograde dopant concentration profile results in an approximately linear capacitance/voltage characteristic response of the varactor. The retrograde dopant concentration profile also enables a peak of the dopant concentration to function as a low resistance conductive path connecting to the varactor.

摘要翻译： 在耗尽区中形成具有逆向掺杂剂浓度分布的半导体结的变容二极管。 逆向掺杂剂浓度分布导致变容二极管的近似线性电容/电压特性响应。 逆向掺杂剂浓度分布还使得掺杂剂浓度的峰值能够用作连接到变容二极管的低电阻导电路径。

公开(公告)号：US07895550B2

公开(公告)日：2011-02-22

申请号：US12103825

申请日：2008-04-16

申请人： John Q. Walker ,  Jeffrey P. Burleson ,  Scott A. Service ,  Steven L. Howard

发明人： John Q. Walker ,  Jeffrey P. Burleson ,  Scott A. Service ,  Steven L. Howard

IPC分类号： G06F17/50

CPC分类号： H01L27/0207 ,  H01L27/088 ,  H01L29/4238 ,  H01L29/78

摘要： A method for reducing variation in a desired property between transistors in an integrated circuit that is fabricated with a given process. The process is characterized to form a mathematical model that associates changes in polysilicon density and active density in the integrate circuit with changes in gate length and gate width in the transistors, and associates changes in the gate length and the gate width to the desired property. The integrated circuit is laid out with space sufficient to adjust the gate length and the gate width of the transistors without violating design rules of the transistors. The integrated circuit is divided into portions, and for at least a given one of the portions of the integrated circuit, the polysilicon density and the active density of the given portion is measured. For at least one of the transistors in the given portion of the integrated circuit, at least one of the gate length and the gate width of the transistor is selectively adjusted according to the mathematical model, based on at least one of the polysilicon density and the active density of the given portion, to reduce variation in the desired property between the transistors in the integrated circuit.

摘要翻译： 一种用于减少用给定工艺制造的集成电路中的晶体管之间期望特性的变化的方法。 该过程的特征在于形成数学模型，其将积分电路中的多晶硅密度和有源密度的变化与晶体管中的栅极长度和栅极宽度的变化相关联，并且将栅极长度和栅极宽度的变化关联到期望的性质。 集成电路布置有足以调节晶体管的栅极长度和栅极宽度的空间，而不违反晶体管的设计规则。 集成电路被分成多个部分，并且对于集成电路的至少一个给定的部分，测量给定部分的多晶硅密度和有效密度。 对于集成电路的给定部分中的至少一个晶体管，根据数学模型，基于多晶硅密度和晶体管的至少一个来选择性地调节晶体管的栅极长度和栅极宽度中的至少一个 给定部分的有效密度，以减少集成电路中的晶体管之间的期望特性的变化。

公开(公告)号：US06342734B1

公开(公告)日：2002-01-29

申请号：US09559934

申请日：2000-04-27

申请人： Derryl D. J. Allman ,  John Q. Walker ,  Verne C. Hornback ,  Todd A. Randazzo

发明人： Derryl D. J. Allman ,  John Q. Walker ,  Verne C. Hornback ,  Todd A. Randazzo

IPC分类号： H01L2348

CPC分类号： H01L28/40 ,  H01L21/32051 ,  H01L23/53223 ,  H01L2924/0002 ,  H01L2924/00

摘要： A metal-insulator-metal capacitor is formed between interconnect layers of an integrated circuit with one of the plates of the capacitor formed integrally with one of the interconnect layers. A dielectric layer is formed on top of the interconnect layer, and a top capacitor plate is formed thereon. A bottom plate is defined by the interconnect layer and extends laterally beyond the top plate so that via interconnects may connect to both plates. An intermetal dielectric (IMD) layer separates the interconnect layer and the capacitor from the next interconnect layer above, and the via interconnects are formed through the IMD layer to connect the above interconnect layer to the capacitor plates. The dielectric layer on top of the interconnect layer that defines the bottom plate and another dielectric layer formed on top of the top plate may serve as etch stops for forming the vias for the via interconnects to different levels.

摘要翻译： 在集成电路的互连层之间形成金属 - 绝缘体 - 金属电容器，其中电容器的一个板与一个互连层一体形成。 在互连层的顶部形成有电介质层，在其上形成顶部电容器板。 底板由互连层限定，并且横向延伸超过顶板，使得通孔互连可以连接到两个板。 金属间电介质（IMD）层将互连层和电容器与上面的下一个互连层分离，并且通孔互连通过IMD层形成，以将上述互连层连接到电容器板。 限定底板的互连层顶部的介电层和形成在顶板顶部的另一电介质层可用作形成用于通孔互连的不同级别的通孔的蚀刻停止。