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公开(公告)号：US5774021A
公开(公告)日：1998-06-30
申请号：US725557
申请日：1996-10-03
CPC分类号： G05F3/222 , H03F3/211 , H03F3/45071
摘要： Operational transconductance amplifiers (OTAs) are combined at their outputs, yielding a single frequency compensation connection point. In a preferred embodiment, the output of each OTA is asymmetric, i.e., they can only source current and the OTA outputs are tied together to a constant current sink. Consequently, the OTA that sources more current controls the voltage of the merged output. This merged output point provides a voltage output that may be used as a frequency compensation point.
摘要翻译： 操作跨导放大器（OTA）在其输出端组合，产生单个频率补偿连接点。 在优选实施例中，每个OTA的输出是不对称的，即，它们只能源电流并且OTA输出被连接到恒定电流吸收器。 因此，来自更多电流的OTA控制合并输出的电压。 该合并输出点提供可用作频率补偿点的电压输出。
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公开(公告)号：US5973550A
公开(公告)日：1999-10-26
申请号：US158691
申请日：1998-09-22
申请人： Derek F. Bowers , Larry C. Tippie
发明人： Derek F. Bowers , Larry C. Tippie
摘要： A JFET pair having unequal pinchoff voltages is operated in saturation with equal source-drain current to channel width-to-length ratios to provide a reference voltage output. Positive or negative voltage references can be implemented using either n-channel or p-channel JFETs. The pinchoff voltage difference results from the channel for one JFET having a heavier doping level than that of the other JFET.
摘要翻译： 具有不等钳针电压的JFET对以相同的源极 - 漏极电流与通道宽度 - 长度比进行饱和操作，以提供参考电压输出。 可以使用n沟道或p沟道JFET实现正或负的参考电压。 钳位电压差来自具有比其它JFET的掺杂级更高的JFET的沟道。
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公开(公告)号：US5714892A
公开(公告)日：1998-02-03
申请号：US627504
申请日：1996-04-04
申请人： Derek F. Bowers , James J. Ashe , Leo P. Mchugh
发明人： Derek F. Bowers , James J. Ashe , Leo P. Mchugh
IPC分类号： H03K19/094 , H03M1/78 , H03K19/0175
CPC分类号： H03K19/09425 , H03M1/785
摘要： A three state logic input recognizes three logic levels: an intermediate level in addition to the conventional "high" and "low" levels employed by binary logic systems. The three state device may be used in purely ternary logic systems or in "hybrid" systems which combine binary and ternary logic. In a preferred embodiment, the new three state logic device comprises a "passive driver" which is connected to produce one of three predetermined logic levels in corresponding to impedance paths from its input terminal through an external circuit to a positive or negative voltage supply. In hybrid ternary/binary applications, the new three state input device includes a decoder that is connected to decode the three predetermined logic levels provided by the passive driver into binary logic for use by associated binary logic devices. In a digital to analog converter application, the three state input device is employed to recognize both a binary logic and a control signal at one input pin to the DAC.
摘要翻译： 三态逻辑输入识别三个逻辑电平：除二进制逻辑系统采用的常规“高”和“低”电平以外的中间电平。 三状态设备可以用于组合二进制和三元逻辑的纯三元逻辑系统或“混合”系统中。 在一个优选实施例中，新的三状态逻辑器件包括一个“无源驱动器”，其被连接以产生三个预定逻辑电平中的一个，对应于从其输入端通过外部电路到正或负电压源的阻抗路径。 在混合三进制/二进制应用中，新的三状态输入设备包括一个解码器，它被连接以将由被动驱动器提供的三个预定逻辑电平解码成二进制逻辑以供相关的二进制逻辑器件使用。 在数模转换器应用中，三态输入装置用于在DAC的一个输入引脚处识别二进制逻辑和控制信号。
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公开(公告)号：US4675561A
公开(公告)日：1987-06-23
申请号：US798430
申请日：1985-11-15
申请人： Derek F. Bowers
发明人： Derek F. Bowers
IPC分类号： H01L27/08 , H01L21/8249 , H01L27/02 , H01L27/06 , H01L27/092 , H03K17/687 , H03K17/12
CPC分类号： H01L27/0921 , H01L27/0218 , H03K2217/0027
摘要： A CMOS output drive circuit has two field effect transistors (FETs) implemented with a CMOS process and characterized by parasitic bipolar transistors. The back-gates of the two transistors are tied together, such as by forming the devices in a common well, and the back-gate of the second FET is also connected to prevent its associated parasitic bipolar transistor from conducting. Quiescent loads are applied to the two FETs so that their voltages are comparable during low output loading, resulting in a drive circuit with high input impedance and high output voltage swing. The output terminal is taken from the first FET, the voltage of which becomes unbalanced from the second FET at relatively high output loads, turning on the parasitic bipolar transistor for the first FET. This gives the drive circuit a desirably high input impedance and low output impedance for heavy output loads. The circuit thus sacrifices low output impedance for high input impedance and voltage swing during light output loading when output impedance is not very important, and sacrifices high voltage swing for high input impedance and low output impedance at heavy loads at which the impedance levels are more important than voltage swing.
摘要翻译： CMOS输出驱动电路具有用CMOS工艺实现的两个场效应晶体管（FET），其特征在于寄生双极晶体管。 两个晶体管的背栅通过诸如通过在公共阱中形成器件而被连接在一起，并且第二FET的背栅也被连接以防止其相关联的寄生双极晶体管导通。 静态负载被施加到两个FET，使得它们的电压在低输出负载期间是相当的，导致具有高输入阻抗和高输出电压摆幅的驱动电路。 输出端子取自第一FET，其电压在相对高的输出负载下与第二FET不平衡，导通第一FET的寄生双极晶体管。 这为驱动电路提供了期望的高输入阻抗，并且对于重输出负载而言具有低输出阻抗。 因此，当输出阻抗不是非常重要时，电路因此牺牲了高输入阻抗和高输入阻抗的低输出阻抗，并且在阻抗水平更重要的情况下牺牲了高输入阻抗的高电压摆幅和低负载下的低输出阻抗 比电压摆幅。
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公开(公告)号：US4583051A
公开(公告)日：1986-04-15
申请号：US668721
申请日：1984-11-06
申请人： Derek F. Bowers
发明人： Derek F. Bowers
CPC分类号： H03F1/32 , H03F3/3435
摘要： An output circuit amplifier has first and second stage amplifying transistors with an impedance circuit connected between the base of the first stage transistor and the collector-emitter circuit of the second stage transistor to draw current from the first stage transistor base, thereby keeping both transistors out of saturation. The impedance circuit establishes a voltage drop between the two transistors such that large output voltage swings are enabled at an output terminal connected to the second stage transistor. The collector-emitter circuit of the first stage transistor is connected directly to a positive voltage bus to avoid further saturation problems.
摘要翻译： 输出电路放大器具有第一级放大晶体管和第二级放大晶体管，其阻抗电路连接在第一级晶体管的基极与第二级晶体管的集电极 - 发射极之间，以从第一级晶体管基极中抽出电流，从而保持两个晶体管出来 的饱和度。 阻抗电路在两个晶体管之间建立电压降，使得在连接到第二级晶体管的输出端子处使能大的输出电压摆幅。 第一级晶体管的集电极 - 发射极电路直接连接到正电压母线，以避免进一步的饱和问题。
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公开(公告)号：US4503381A
公开(公告)日：1985-03-05
申请号：US472963
申请日：1983-03-07
申请人： Derek F. Bowers
发明人： Derek F. Bowers
摘要： An integrated current mirror circuit in which a compensation transistor is added in each stage of the mirror to compensate for the base-substrate leakage currents of the other transistors in the mirror circuit and to keep the circuit operative even at high temperatures and low current levels. Each compensation transistor is matched with the other transistors in its stage and has its collector-emitter circuit connected between a voltage source terminal and the common base connection of the other transistors. The base of each compensation transistor is unconnected to the remainder of the circuit but exhibits a base-substrate leakage current which is employed in the compensation scheme.
摘要翻译： 一种集成电流镜电路，其中补偿晶体管被添加到反射镜的每个级中以补偿镜电路中的其它晶体管的基底衬底漏电流并且使电路即使在高温和低电流水平下也能工作。 每个补偿晶体管在其级中与其他晶体管匹配，并且其集电极 - 发射极电路连接在电压源端子和其他晶体管的公共基极连接之间。 每个补偿晶体管的基极与电路的其余部分不连接，但是表现出在补偿方案中采用的基底漏极电流。
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公开(公告)号：US08130037B2
公开(公告)日：2012-03-06
申请号：US12730046
申请日：2010-03-23
申请人： Derek F. Bowers
发明人： Derek F. Bowers
IPC分类号： H03F3/45
CPC分类号： H03F1/302 , H03F3/45085 , H03F3/45089 , H03F2200/261 , H03F2200/555 , H03F2203/45294 , H03F2203/45622
摘要： An input bias current cancellation circuit includes reference transistors placed in series and a current summation network. The current summation network can be configured to sum the base currents of the reference transistors to produce a summed current. A current mirror can be provided to attenuate the summed current to produce input bias cancellation currents. The input bias cancellation currents can be provided to the base inputs of an input bipolar differential pair, thereby reducing input current noise.
摘要翻译： 输入偏置电流消除电路包括串联放置的参考晶体管和电流求和网络。 可以将当前求和网络配置为对参考晶体管的基极电流求和以产生求和电流。 可以提供电流镜来衰减总和电流以产生输入偏置消除电流。 可以将输入偏置消除电流提供给输入双极差分对的基极输入，从而降低输入电流噪声。
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公开(公告)号：US07035413B1
公开(公告)日：2006-04-25
申请号：US09544657
申请日：2000-04-06
IPC分类号： H04R5/00
CPC分类号： H04S3/02
摘要： A dynamically variable spectral matrix surround system decodes two-channel stereo into multi-channel surround. In one embodiment, the true stereo signal is present in left and right front and left and right surround channel outputs. When a dominant center channel signal appears, the system subtracts center channel audio from the critical voice band only. The higher frequency portion of the spectrum will remain true stereo at all times. In another embodiment, the front center signal bandwidth is determined. A dynamically variable portion of the audio spectrum is inverted and added to the opposite channel, thereby dynamically subtracting the bandwidth of the front center signal from the left front, left surround, right front and right surround channels but leaving the portion of the audio spectrum that does not contain front center information unaltered. The input is divided into two frequency bands. The low frequency portion remains true stereo at all times because only high frequencies are processed by cancellation steering. By dynamically varying the cancellation bandwidth in the left and right output channels, the typical audible dominance of the difference signals is greatly reduced. When the input contains a dominant left or right signal, the center front and surround channels are steered down in level so as to produce the output only in the front channels. When a dominant surround signal is present in the input, the front channels are steered down in level. Therefore, allows the system produces an output only in the channel where the originally encoded signal was intended.
摘要翻译： 动态可变光谱矩阵环绕系统将双声道立体声解码为多声道环绕声。 在一个实施例中，真实立体声信号存在于左右前和左右环绕声道输出中。 当出现主要中心通道信号时，系统仅从关键语音频段中减去中心声道音频。 频谱的较高频率部分始终保持真正的立体声。 在另一个实施例中，确定前中心信号带宽。 音频频谱的动态可变部分被反转并添加到相反的通道，从而从左前，左环绕，右前和右环绕声道动态地减去前中心信号的带宽，但是使音频频谱的该部分 不包含前置中心信息。 输入分为两个频带。 低频部分始终保持真正的立体声，因为仅通过取消转向处理高频。 通过动态地改变左右输出通道中的消除带宽，差异信号的典型听觉优势大大降低。 当输入包含主要的左或右信号时，中心前置和环绕声道的电平向下转向，以便仅在前置通道中产生输出。 当输入中存在显着的环绕信号时，前方通道的电平被下降。 因此，允许系统仅在原始编码信号的通道中产生输出。
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公开(公告)号：US06239630B1
公开(公告)日：2001-05-29
申请号：US09359512
申请日：1999-07-23
申请人： Derek F. Bowers , Azita Ashe
发明人： Derek F. Bowers , Azita Ashe
IPC分类号： H03L700
CPC分类号： H03K17/145 , H03K17/223
摘要： A power-on reset circuit employs all-CMOS circuitry to initiate a reset signal when the circuit's power supply voltage is low, and terminate the signal in response to the supply voltage exceeding a reference voltage by at least the greater of the threshold voltages of PFET and NFET transistors employed in the circuit. A diode-connected bipolar transistor is implemented with an FET-compatible circuit structure to establish the reference voltage, which compensates for the possibility of fabrication tolerances.
摘要翻译： 上电复位电路采用全CMOS电路来在电路的电源电压低时启动复位信号，并且响应于超过参考电压的电源电压至少将PFET的阈值电压中的较大者终止信号 和用于该电路中的NFET晶体管。 二极管连接的双极晶体管采用与FET兼容的电路结构来实现，以建立参考电压，从而补偿制造公差的可能性。
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公开(公告)号：US5838192A
公开(公告)日：1998-11-17
申请号：US587548
申请日：1996-01-17
申请人： Derek F. Bowers , Larry C. Tippie
发明人： Derek F. Bowers , Larry C. Tippie
摘要： A JFET pair having unequal pinchoff voltages is operated in saturation with equal source-drain current to channel width-to-length ratios to provide a reference voltage output. Positive or negative voltage references can be implemented using either n-channel or p-channel JFETs. The pinchoff voltage difference results from the channel for one JFET having a heavier doping level than that of the other JFET.
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