公开(公告)号：US07142454B2

公开(公告)日：2006-11-28

申请号：US10243315

申请日：2002-09-12

申请人： Tien-Chun Yang ,  Ming-Huei Shieh ,  Kurihara Kazuhiro ,  Pau-Ling Chen

发明人： Tien-Chun Yang ,  Ming-Huei Shieh ,  Kurihara Kazuhiro ,  Pau-Ling Chen

IPC分类号： G11C16/04

CPC分类号： G11C16/26 ,  G11C16/0458 ,  G11C16/0475 ,  G11C16/0491

摘要： A system and method for column selection in a non-volatile memory cell array is disclosed. A group of memory cells is arranged in a rectangular array having rows (X-dimension) and columns (Y-dimension). Within a row, the sources and drains of the memory cells are connected to form a linear chain. A common word line is coupled to each gate in the row. A separate column line is coupled to each node between adjacent memory cells of the chain. A four column Y-decoder is used to select column lines for sense operations. A voltage source is applied to two of the four column lines during the sense operation. Current on one of the column lines may be sensed to provide a measurement for read or verification.

摘要翻译： 公开了一种用于非易失性存储单元阵列中的列选择的系统和方法。 一组存储单元被布置成具有行（X维）和列（Y维）的矩形阵列。 在一行中，存储器单元的源极和漏极被连接以形成线性链。 公共字线连接到行中的每个门。 单独的列线耦合到链的相邻存储器单元之间的每个节点。 四列Y解码器用于选择用于感测操作的列线。 在感测操作期间，将电压源施加到四列中的两条线。 可以感测一列列线上的电流以提供用于读取或验证的测量。

公开(公告)号：US06859393B1

公开(公告)日：2005-02-22

申请号：US10264387

申请日：2002-10-04

申请人： Tien-Chun Yang ,  Shigekazu Yamada ,  Ming-Huei Shieh ,  Pau-Ling Chen

发明人： Tien-Chun Yang ,  Shigekazu Yamada ,  Ming-Huei Shieh ,  Pau-Ling Chen

IPC分类号： G11C16/04

CPC分类号： G11C16/0466 ,  G11C16/0491 ,  G11C2216/14

摘要： A ground structure for page read and page write for flash memory. An array structure of flash memory cells comprises a plurality of sectors. Each sector comprises I/O blocks plus reference arrays and an array of redundant cells. Each I/O block comprises sub I/O blocks. Each sub I/O block within an I/O block, as well as other structures including reference cells, redundant cells and edge structures is coupled to a unique ground reference signal. These unique ground reference signals may be selectively coupled to a system ground or a biased ground reference. This novel ground arrangement enables a page read operation in which one bit from each sub I/O block can be read simultaneously. In addition, one bit from each I/O block may be programmed simultaneously. Further, the ground reference voltage for cells of the array may be selectively adjusted to optimize operation.

摘要翻译： 用于闪存的页面读取和页面写入的接地结构。 闪存单元的阵列结构包括多个扇区。 每个扇区包括I / O块加参考阵列和冗余单元阵列。 每个I / O块包括子I / O块。 I / O块内的每个子I / O块以及包括参考单元，冗余单元和边缘结构的其他结构都耦合到独特的接地参考信号。 这些独特的接地参考信号可以选择性地耦合到系统接地或偏置的接地参考。 这种新颖的接地布置使得能够同时读取来自每个子I / O块的一个位的页面读取操作。 另外，每个I / O块的一位可以同时编程。 此外，可以选择性地调整阵列的单元的接地参考电压以优化操作。

公开(公告)号：US06944057B1

公开(公告)日：2005-09-13

申请号：US10431065

申请日：2003-05-06

申请人： Edward F. Runnion ,  Tien-Chun Yang ,  Binh Quang Le ,  Shigekazu Yamada ,  Darlene G. Hamilton ,  Ming-Huei Shieh ,  Pau-Ling Chen ,  Kazuhiro Kurihara

发明人： Edward F. Runnion ,  Tien-Chun Yang ,  Binh Quang Le ,  Shigekazu Yamada ,  Darlene G. Hamilton ,  Ming-Huei Shieh ,  Pau-Ling Chen ,  Kazuhiro Kurihara

IPC分类号： G11C16/06

CPC分类号： G11C16/3418 ,  G11C16/10

摘要： A method for controlling gate voltage in a memory device is described. The method includes providing a circuit that is adapted to be coupled with the memory device. The circuit is for generating a reference voltage. The method further includes utilizing the reference voltage provided by the circuit to apply a voltage at a gate of the memory device. The voltage has a value corresponding to a temperature of the memory device. The method also includes retaining a proportional relationship between the reference voltage and the temperature of the memory device, regardless of the change in the temperature of the memory device. The reference voltage provides a substantially constant programming time for the memory device regardless of the temperature of the memory device.

摘要翻译： 描述了一种用于控制存储器件中的栅极电压的方法。 该方法包括提供适于与存储器件耦合的电路。 该电路用于产生参考电压。 该方法还包括利用由电路提供的参考电压来在存储器件的栅极处施加电压。 电压具有对应于存储器件的温度的值。 该方法还包括保持参考电压与存储器件的温度之间的比例关系，而与存储器件的温度变化无关。 参考电压为存储器件提供基本上恒定的编程时间，而与存储器件的温度无关。

公开(公告)号：US06728160B1

公开(公告)日：2004-04-27

申请号：US10243433

申请日：2002-09-12

申请人： Tien-Chun Yang ,  Kurihara Kazuhiro ,  Pau-Ling Chen

发明人： Tien-Chun Yang ,  Kurihara Kazuhiro ,  Pau-Ling Chen

IPC分类号： G11C800

CPC分类号： G11C16/24 ,  G11C7/1051 ,  G11C7/12

摘要： A path gate driver circuit of the present invention includes a shunt stage, a level shifter stage, a pull-up stage, and an output stage. The shunt stage has a control terminal coupled to a supply, and an input terminal coupled to a control signal path. The level shifter stage has a first control terminal coupled to the control signal path, a second control terminal coupled to an output terminal of the shunt stage, a first input terminal coupled to a boost-low supply, and a second input terminal coupled to a boost-high supply. The pull-up stage has a control terminal coupled to an output terminal of the level shifter stage, and an input terminal coupled to the boost-high supply. The output stage has a first control terminal coupled to the output terminal of the shunt stage and an output terminal of the pull-up stage, a second control terminal coupled to the control signal path a first input terminal coupled to the boost-low supply, and a second input terminal coupled to the boost-high supply. A boosted control signal is provided at the output terminal of the output stage in response to the control.

摘要翻译： 本发明的路径栅极驱动电路包括分路级，电平转换级，上拉级和输出级。 分流级具有耦合到电源的控制端子和耦合到控制信号路径的输入端子。 电平移位器级具有耦合到控制信号路径的第一控制端，耦合到并联级的输出端的第二控制端，耦合到升压低电源的第一输入端和耦合到 增加高的供应。 上拉级具有耦合到电平移位器级的输出端子的控制端子和耦合到升压高电源的输入端子。 输出级具有耦合到并联级的输出端和上拉级的输出端的第一控制端，耦合到控制信号路径的第二控制端，耦合到升压低电源的第一输入端， 以及耦合到所述升压高电源的第二输入端子。 响应于该控制，在输出级的输出端提供升压控制信号。

公开(公告)号：US06819591B1

公开(公告)日：2004-11-16

申请号：US10762071

申请日：2004-01-20

申请人： Kazuhiro Kurihara ,  Ming-Huei Shieh ,  Santosh Yachareni ,  Pau-Ling Chen

发明人： Kazuhiro Kurihara ,  Ming-Huei Shieh ,  Santosh Yachareni ,  Pau-Ling Chen

IPC分类号： G11C1604

CPC分类号： G11C16/0475 ,  G11C16/0491

摘要： An exemplary memory sector erase method comprises the steps of pre-programming a first bit and a second bit of a plurality of core memory cells of a plurality of memory blocks of a target memory sector, pre-programming one of a third bit and a fourth bit of a first neighboring memory cell adjacent to the target memory sector, and erasing the first bit and the second bit of the plurality of core memory cells of the plurality of memory blocks. According to another embodiment, the method further comprises programming the one of the third bit and the fourth bit of the first neighboring memory cell after the erasing step.

摘要翻译： 示例性存储器扇区擦除方法包括以下步骤：对目标存储器扇区的多个存储器块的多个核心存储器单元的第一位和第二位进行预编程，预编程第三位和第四 与目标存储器扇区相邻的第一相邻存储单元的位，以及擦除多个存储块中的多个存储单元的第一位和第二位。 根据另一实施例，该方法还包括在擦除步骤之后编程第一相邻存储器单元的第三位和第四位之一。

公开(公告)号：US06744666B1

公开(公告)日：2004-06-01

申请号：US10243792

申请日：2002-09-12

申请人： Santosh Yachareni ,  Kazuhiro Kurihara ,  Ming-Huei Shieh ,  Pau-Ling Chen

发明人： Santosh Yachareni ,  Kazuhiro Kurihara ,  Ming-Huei Shieh ,  Pau-Ling Chen

IPC分类号： G11C1134

CPC分类号： G11C16/10 ,  G11C2216/14 ,  G11C2216/16

摘要： Embodiments of the present invention are directed to a method and system to minimize page programming time for page programmable memory devices. In one embodiment, the present invention comprises program logic that programs a page programmable memory device with a plurality of words during a page programming cycle and a detector coupled to the program logic that identifies a particular word in that plurality of words which does not require programming. When the detector identifies a particular word which does not require programming, it sends an indication to the program logic component which, in response to the signal, reduces the length of the page programming cycle.

摘要翻译： 本发明的实施例涉及一种使页面可编程存储器件的页面编程时间最小化的方法和系统。 在一个实施例中，本发明包括在页面编程周期期间用多个单词编程页面可编程存储器件的程序逻辑和耦合到程序逻辑的检测器，该程序逻辑识别出不需要编程的多个单词中的特定单词 。 当检测器识别不需要编程的特定字时，它向程序逻辑组件发送指示，该程序逻辑组件响应于该信号减少了页面编程周期的长度。

公开(公告)号：US07026843B1

公开(公告)日：2006-04-11

申请号：US10759855

申请日：2004-01-16

申请人： Tien-Chun Yang ,  Pau-Ling Chen

发明人： Tien-Chun Yang ,  Pau-Ling Chen

IPC分类号： G01R19/00

CPC分类号： G11C16/26 ,  G11C7/062

摘要： An exemplary cascode amplifier circuit comprises a first intrinsic FET, a second intrinsic FET, a third intrinsic FET, and a fourth FET. The first intrinsic FET has a source connected to a target memory cell via a bit line and a drain connected to a first node. The second intrinsic FET has a gate connected to the source of the first intrinsic FET and a source connected to a reference voltage. The second intrinsic FET also has a drain connected at a second node to a gate of the first intrinsic FET. The third intrinsic FET has a source connected to the first node and a gate connected to a supply voltage, and further provides a load across the supply voltage and the first node. The fourth FET has a source connected to the second node and a drain connected to the supply voltage, the fourth FET having a gate connected to an input control voltage.

摘要翻译： 示例性共源共栅放大器电路包括第一本征FET，第二本征FET，第三本征FET和第四FET。 第一本征FET具有经由位线连接到目标存储器单元的源极和连接到第一节点的漏极。 第二本征FET具有连接到第一本征FET的源极的栅极和连接到参考电压的源极。 第二本征FET还具有在第二节点处连接到第一本征FET的栅极的漏极。 第三本征FET具有连接到第一节点的源极和连接到电源电压的栅极，并且进一步在电源电压和第一节点之间提供负载。 第四FET具有连接到第二节点的源极和连接到电源电压的漏极，第四FET具有连接到输入控制电压的栅极。

公开(公告)号：US07076703B1

公开(公告)日：2006-07-11

申请号：US10305700

申请日：2002-11-26

申请人： Binh Quang Le ,  Pau-Ling Chen

发明人： Binh Quang Le ,  Pau-Ling Chen

IPC分类号： G11C29/00

CPC分类号： G11C29/804

摘要： A method for a memory redundancy, including a memory array typically having a plurality of columns (e.g., bit lines) of memory cells, and identifying a particular (e.g., defective) column of the memory array and further defining a redundancy window by selecting a group of adjacent columns including the defective column. The number of columns in the group of selected columns may be equal to the number of columns in a redundancy array that is coupled to the memory array. The redundancy array is used for storing information that would have been otherwise stored in the memory cells in the redundancy window. The selected group includes at least one column on one side of the defective column and another column on the other side of the defective column. Typically, there will be multiple columns on each side of the defective column.

摘要翻译： 一种用于存储器冗余的方法，包括通常具有存储器单元的多个列（例如，位线）的存储器阵列，以及识别存储器阵列的特定（例如，有缺陷的）列，并进一步通过选择一个 一组相邻列，包括有缺陷的列。 所选列组中的列数可以等于耦合到存储器阵列的冗余阵列中的列数。 冗余阵列用于存储否则将存储在冗余窗口中的存储器单元中的信息。 所选择的组包括在缺陷列的一侧上的至少一个列和在缺陷列的另一侧上的另一个列。 通常，有缺陷的列的每一侧将有多个列。

公开(公告)号：US07038950B1

公开(公告)日：2006-05-02

申请号：US10982296

申请日：2004-11-05

申请人： Darlene Hamilton ,  Ed Hsia ,  Pau-Ling Chen

发明人： Darlene Hamilton ,  Ed Hsia ,  Pau-Ling Chen

IPC分类号： G11C11/34 ,  G11C16/04 ,  G11C16/06

CPC分类号： G11C11/5628 ,  G11C16/3418 ,  G11C16/3431 ,  G11C16/349 ,  G11C2211/5621

摘要： Methods of programming NEW data into unprogrammed bits of a group of memory cells is provided. The method applies an interactive programming algorithm that individually verifies and programs the NEW data, reference (REF) data, and existing or OLD data. OLD data is separately verified to a compensated program verify level from that of the NEW data to improve memory reliability and insure minimal uniform stress levels to the array. The improved programming algorithm prevents older data from being needlessly refreshed, thus mitigating stress to the cells that eventually causes the data areas to decay at different rates and become prematurely unreliable.

摘要翻译： 提供将新数据编程到一组存储器单元的未编程位中的方法。 该方法应用一种交互式编程算法，可以对新数据，参考（REF）数据和现有或OLD数据进行单独验证和编程。 OLD数据被分别验证为与NEW数据的补偿程序验证级别，以提高内存可靠性并确保阵列的最小均匀应力水平。 改进的编程算法防止老化的数据被不必要地刷新，从而减轻细胞的压力，最终导致数据区域以不同的速率衰减并变得过早地不可靠。

公开(公告)号：US06622201B1

公开(公告)日：2003-09-16

申请号：US09525078

申请日：2000-03-14

申请人： Michael VanBuskirk ,  Pau-Ling Chen

发明人： Michael VanBuskirk ,  Pau-Ling Chen

IPC分类号： G06F1200

CPC分类号： G11C7/22

摘要： A sequential access memory structure includes an output bus and a plurality of sequential access memories, each of which is connected to the output bus. Each memory includes a memory array having a plurality of sequentially readable memory elements, a carry output for producing a carry signal when reading of the array has been substantially completed, and a carry input for causing reading of the array in response to a carry signal. The carry output of each memory is connected to a carry input of one other downstream memory respectively in a chain arrangement, and the carry signals cause the arrays to be read sequentially onto the output bus. Each memory further comprises a read-write storage connected between the array and the output bus, the storage including a plurality of sections. Data from the array is loaded into one section of the storage while data is being read from another section of the storage onto the output bus. The sections of memory elements in the array comprise half-pages. The storage comprises two sections, each of which has a half-page of memory elements, and the carry output produces the carry signal prior to reading data from a last half-page of the array out of the storage onto the output bus. Data from the last half-page is read onto the output bus while data from a first half-page of an array of a next downstream memory is being loaded into its storage.

摘要翻译： 顺序访问存储器结构包括输出总线和多个顺序存取存储器，每个存取存储器连接到输出总线。 每个存储器包括具有多个可顺序读取的存储器元件的存储器阵列，当阵列的读取已基本完成时用于产生进位信号的进位输出，以及用于响应于进位信号而引起阵列读取的进位输入。 每个存储器的进位输出分别以链排列连接到另一个下游存储器的进位输入，并且进位信号使得阵列被顺序读取到输出总线上。 每个存储器还包括连接在阵列和输出总线之间的读写存储器，存储器包括多个部分。 来自阵列的数据被加载到存储的一部分中，同时从存储器的另一部分读取数据到输出总线上。 阵列中的内存元素部分包括半页。 存储器包括两个部分，每个部分具有半页存储器元件，并且进位输出在从阵列的最后半页从存储器中读取数据到输出总线之前产生进位信号。 来自上一个半页的数据被读取到输出总线上，而来自下一个下游存储器阵列的前半页的数据被加载到其存储器中。