公开(公告)号：US08159263B1

公开(公告)日：2012-04-17

申请号：US12770559

申请日：2010-04-29

申请人： Tim Tuan ,  Ronald L. Cline ,  Arifur Rahman

发明人： Tim Tuan ,  Ronald L. Cline ,  Arifur Rahman

IPC分类号： H03K19/173

CPC分类号： H03K19/018585 ,  H03K19/0016

摘要： A programmable integrated circuit having a plurality of individually controlled voltage domains. Each voltage domain includes logic circuitry powered by a respective power network. The voltage magnitude of each power network is independently selectable. Each of a plurality of level shifters couples a first and second one of the voltage domains, couples a first port of the logic circuitry of the first voltage domain to a second port of the logic circuitry of the second voltage domain, and shifts from a first signaling protocol of the first port to a second signaling protocol of the second port. The first signaling protocol is referenced to the voltage magnitude of the first voltage domain, and the second signaling protocol is referenced to the voltage magnitude of the second voltage domain. Means are disclosed for controlling the voltage magnitude of the respective power network of one or more of the voltage domains.

摘要翻译： 一种具有多个独立控制的电压域的可编程集成电路。 每个电压域包括由相应的电力网络供电的逻辑电路。 每个电力网络的电压幅度是独立可选的。 多个电平移位器中的每一个耦合第一和第二电压域，将第一电压域的逻辑电路的第一端口耦合到第二电压域的逻辑电路的第二端口，并从第一 第一端口的信令协议到第二端口的第二信令协议。 第一信令协议参考第一电压域的电压幅度，第二信令协议参考第二电压域的电压幅度。 公开了用于控制一个或多个电压域的各个电力网络的电压幅值的装置。

公开(公告)号：US07498835B1

公开(公告)日：2009-03-03

申请号：US11268265

申请日：2005-11-04

申请人： Arifur Rahman ,  Sean W. Kao ,  Tim Tuan ,  Patrick J. Crotty ,  Jinsong Oliver Huang

发明人： Arifur Rahman ,  Sean W. Kao ,  Tim Tuan ,  Patrick J. Crotty ,  Jinsong Oliver Huang

IPC分类号： H03K19/173 ,  G11C5/14

CPC分类号： H03K19/17772 ,  G06F1/3203 ,  G06F1/3287 ,  G11C5/148 ,  H03K19/0016 ,  H03K19/17784 ,  Y02D10/171 ,  Y02D50/20

摘要： A PLD (200) includes a power management unit (PMU 210) that selectively implements one or more different power-reduction techniques in response to power configuration signals (PC). By manipulating the PC signals, the PMU can independently enable/disable various supply voltage circuits (110, 120, 130) that power CLBs (101), IOBs (102), and configuration memory cells (106), can generate a capture signal that causes data stored in storage elements of the CLBs to be captured in configuration memory cells, and/or can switch power terminals of configuration memory cells between voltage supply circuits. Also, the PMU can sequentially apply and remove power from a number of configurable PLD portions in response to the PC signals, wherein each configurable portion may include any number of the PLD's resources.

摘要翻译： PLD（200）包括功率管理单元（PMU 210），其响应于功率配置信号（PC）选择性地实现一个或多个不同的功率降低技术。 通过操纵PC信号，PMU可以独立地启用/禁用为CLB（101），IOB（102）和配置存储器单元（106）供电的各种电源电压电路（110,120,130）可以产生捕获信号， 导致存储在CLB的存储元件中的数据被捕获在配置存储单元中，和/或可以在电压供应电路之间切换配置存储单元的电源端子。 此外，响应于PC信号，PMU可以顺序地从多个可配置PLD部分中施加和去除电力，其中每个可配置部分可以包括任何数量的PLD资源。

公开(公告)号：US07417454B1

公开(公告)日：2008-08-26

申请号：US11210498

申请日：2005-08-24

申请人： Arifur Rahman ,  Tim Tuan ,  Sean W. Kao

发明人： Arifur Rahman ,  Tim Tuan ,  Sean W. Kao

IPC分类号： H03K19/173

CPC分类号： H03K19/17784 ,  H03K17/002 ,  H03K17/693 ,  H03K19/1731 ,  H03K19/17728

摘要： An apparatus is disclosed that may reduce the dynamic power dissipation of a configurable IC device such as an FPGA by reducing the peak-to-peak voltage swing of signals transmitted over the device's interconnect signal lines without including additional level shifter circuits. For some embodiments, existing multiplexing circuit architectures provided within logic resources of various logic blocks of the configurable IC device may be used as level shifter circuits to increase the voltage swing of signals received into the blocks from the interconnect signal lines, and modified multiplexing circuit architectures provided within the logic resources may be used to reduce the voltage swing of signals output from the logic blocks onto the interconnect signal lines.

摘要翻译： 公开了一种可以通过减少在器件的互连信号线上传输的信号的峰 - 峰电压摆幅而不包括额外的电平移位器电路来降低诸如FPGA的可配置IC器件的动态功耗的装置。 对于一些实施例，在可配置IC器件的各种逻辑块的逻辑资源内提供的现有多路复用电路架构可以用作电平移位器电路，以增加从互连信号线接收到块中的信号的电压摆幅，以及修改的多路复用电路架构 提供在逻辑资源内的信号可用于将从逻辑块输出的信号的电压摆幅减小到互连信号线上。

公开(公告)号：US07477073B1

公开(公告)日：2009-01-13

申请号：US11454316

申请日：2006-06-16

申请人： Tim Tuan ,  Arifur Rahman ,  Satyaki Das ,  Sean W. Kao

发明人： Tim Tuan ,  Arifur Rahman ,  Satyaki Das ,  Sean W. Kao

IPC分类号： H03K19/177 ,  H03K19/0175

CPC分类号： H03K19/17736 ,  H03K19/17784

摘要： A PLD utilizes a heterogeneous architecture to reduce power consumption of its active resources. The PLD's programmable resources are divided into a first partition and a second partition, where the resources of the first partition are optimized for low power consumption and the resources of the second partition are optimized for high performance. Portions of a user design containing non-critical timing paths are mapped to and implemented by the resources of the power-optimized first partition, and portions of the user design containing critical timing paths are mapped to and implemented by the resources of the performance-optimized second partition.

摘要翻译： PLD利用异构架构来降低其活动资源的功耗。 PLD的可编程资源分为第一分区和第二分区，其中第一分区的资源被优化用于低功耗，并且第二分区的资源被优化用于高性能。 包含非关键定时路径的用户设计的部分被映射到由功率优化的第一分区的资源并由其实现，并且包含关键定时路径的用户设计的部分被映射到由性能优化的资源实现 第二分区。

公开(公告)号：US07545177B1

公开(公告)日：2009-06-09

申请号：US11725742

申请日：2007-03-20

申请人： Sean W. Kao ,  Tim Tuan ,  Arifur Rahman

发明人： Sean W. Kao ,  Tim Tuan ,  Arifur Rahman

IPC分类号： H03K19/096

CPC分类号： H03K19/0016

摘要： Leakage current reduction from a logic block is implemented via power gating transistors that exhibit increased gate oxide thickness as compared to the thin-oxide devices of the power gated logic block. Increased gate oxide further allows increased gate to source voltage differences to exist on the power gating devices, which enhances performance and reduces gate leakage even further. Placement of the power gating transistors in proximity to other increased gate oxide devices minimizes area penalties caused by physical design constraints of the semiconductor die.

摘要翻译： 与电源门控逻辑块的薄氧化物器件相比，通过电源门控晶体管实现了从逻辑块的漏电流减小，其表现出增加的栅极氧化物厚度。 增加的栅极氧化物进一步允许在电源门控器件上存在增加的栅极 - 源极电压差，这进一步提高了性能并降低了栅极泄漏。 功率门控晶体管靠近其他增加的栅极氧化物器件的放置最小化由半导体管芯的物理设计约束引起的面积损失。

公开(公告)号：US07490302B1

公开(公告)日：2009-02-10

申请号：US11196179

申请日：2005-08-03

申请人： Arifur Rahman ,  Sean W. Kao ,  Sathaki Das ,  Tim Tuan

发明人： Arifur Rahman ,  Sean W. Kao ,  Sathaki Das ,  Tim Tuan

IPC分类号： G06F17/50

CPC分类号： G06F17/5054 ,  G06F2217/78

摘要： Power-gating circuit resources of an integrated circuit is described. The circuit resources are associated into sets responsive to utilization levels. The associating includes providing a first set of the sets, a first number of the circuit resources in the first set being associated with a first level of utilization. The associating also includes providing a second set of the sets, a second number of the circuit resources in the second set being associated with a second level of utilization. The first number is less than the second number responsive to the first level of utilization being greater than the second level of utilization. The circuit resources of the first set are commonly coupled to a reference voltage level via a first gating circuit. The circuit resources of the second set are commonly gated to the same or a different reference voltage level via a second gating circuit.

摘要翻译： 描述了集成电路的功率选通电路资源。 电路资源与响应于利用水平的集合相关联。 关联包括提供第一组集合，第一组中的电路资源的第一数量与第一级别的利用相关联。 关联还包括提供第二组集合，第二组中的电路资源的第二数量与第二级别的利用相关联。 第一个数字小于响应于第一个利用水平的第二个数字大于第二个利用水平。 第一组的电路资源通常经由第一选通电路耦合到参考电压电平。 第二组的电路资源通常经由第二选通电路门控到相同或不同的参考电压电平。

公开(公告)号：US08155907B1

公开(公告)日：2012-04-10

申请号：US12480488

申请日：2009-06-08

申请人： Austin H. Lesea ,  Stephen M. Trimberger ,  Christopher H. Kingsley ,  Satyaki Das ,  Tim Tuan

发明人： Austin H. Lesea ,  Stephen M. Trimberger ,  Christopher H. Kingsley ,  Satyaki Das ,  Tim Tuan

IPC分类号： G06F11/00 ,  G06F19/00 ,  G06F17/40

CPC分类号： G06F17/5045 ,  G06F11/26 ,  G06F2217/86

摘要： Methods of enabling functions of a design to be implemented in an integrated circuit device are disclosed. An exemplary method comprises applying test data to a plurality of dice having different element types for implementing circuits, wherein the plurality of dice have a common layout of the different element types for implementing the circuits; receiving output data from the plurality of dice in response to applying the test data to the plurality of dice; analyzing the output data from the plurality of dice; transforming by a computer the output data to characterization data comprising timing data associated with the different element types for implementing circuits, wherein the characterization data comprises data associated with regions of the dice, and storing the characterization data. A computer program product for enabling functions of a design to be implemented in an integrated circuit device is also disclosed.

摘要翻译： 公开了在集成电路装置中实现设计功能的方法。 示例性方法包括将测试数据应用于具有用于实现电路的不同元件类型的多个骰子，其中所述多个骰子具有用于实现电路的不同元件类型的公共布局; 响应于将所述测试数据应用于所述多个骰子，从所述多个骰子接收输出数据; 分析来自多个骰子的输出数据; 通过计算机将输出数据转换成包括与用于实现电路的不同元件类型相关联的定时数据的表征数据，其中表征数据包括与骰子区域相关联的数据，并存储表征数据。 还公开了一种用于使得能够在集成电路器件中实现设计功能的计算机程序产品。

公开(公告)号：US08130027B1

公开(公告)日：2012-03-06

申请号：US12357703

申请日：2009-01-22

申请人： Tim Tuan

发明人： Tim Tuan

IPC分类号： G05F1/10 ,  G05F3/02

CPC分类号： G11C5/147 ,  H03K19/17784 ,  H03K19/17792

摘要： An apparatus and method for the dynamic detection and compensation of performance variations within an integrated circuit (IC) is provided to detect performance variations within the IC at any stage of test or operation. An arbitrary reference signal is utilized in conjunction with an internal oscillation device to establish a speed reference that may be used to characterize the IC. Dynamic detection and compensation may also be configured within a plurality of geographic locations within the IC, so that performance variations may be detected and compensated. Test data that is indicative of the IC's performance may be dynamically generated continuously, or at programmable intervals, so that performance variations caused by virtually any source may be substantially detected and compensated at any point in time of the IC's life cycle.

摘要翻译： 提供用于动态检测和补偿集成电路（IC）内的性能变化的装置和方法，用于在任何测试或操作阶段检测IC内的性能变化。 与内部振荡装置结合使用任意的参考信号以建立可用于表征IC的速度参考。 也可以在IC内的多个地理位置内配置动态检测和补偿，从而可以检测和补偿性能变化。 表示IC性能的测试数据可以连续地或以可编程的间隔动态产生，从而可以在IC的生命周期的任何时刻基本上检测和补偿实际上任何源引起的性能变化。

公开(公告)号：US07992020B1

公开(公告)日：2011-08-02

申请号：US12043096

申请日：2008-03-05

申请人： Tim Tuan ,  Kerry M. Pierce ,  Albert Franceschino

发明人： Tim Tuan ,  Kerry M. Pierce ,  Albert Franceschino

IPC分类号： G06F1/00 ,  G06F1/26 ,  G06F1/32

CPC分类号： G06F1/3203 ,  G06F1/3296 ,  Y02D10/172

摘要： Power management with a packaged multi-die integrated circuit (IC) is described. A first integrated circuit die is capable of a first operational mode. A second integrated circuit die is coupled to the first integrated circuit die. The first integrated circuit die has a rate of power consumption that is lower than the second integrated circuit die when the first integrated circuit die is in the first operational mode and the second integrated circuit die is in a second operational mode. The first integrated circuit die is configured for power management of the second integrated circuit die for placing the second integrated circuit die in a standby mode from the second operational mode and for returning the second integrated circuit die to the second operational mode from the standby mode.

摘要翻译： 描述了使用封装的多芯片集成电路（IC）进行电源管理。 第一集成电路管芯能够具有第一操作模式。 第二集成电路管芯耦合到第一集成电路管芯。 当第一集成电路管芯处于第一操作模式并且第二集成电路管芯处于第二操作模式时，第一集成电路管芯具有低于第二集成电路管芯的功率消耗率。 第一集成电路管芯被配置为用于第二集成电路管芯的电源管理，用于将第二集成电路管芯从第二操作模式放置在待机模式中，并且用于将第二集成电路管芯退回到从待机模式的第二操作模式。

公开(公告)号：US07581124B1

公开(公告)日：2009-08-25

申请号：US11326542

申请日：2006-01-04

申请人： Neil G. Jacobson ,  Matthew T. Murphy ,  Tim Tuan ,  Kameswara K. Rao ,  Robert O. Conn

发明人： Neil G. Jacobson ,  Matthew T. Murphy ,  Tim Tuan ,  Kameswara K. Rao ,  Robert O. Conn

IPC分类号： G06F1/22

CPC分类号： G11C5/14 ,  G11C5/148 ,  G11C29/021 ,  G11C29/028 ,  G11C2029/0401 ,  H03K19/17784

摘要： A PLD includes a plurality of logic blocks, a test circuit, and a test pin set. The logic blocks are coupled to gating circuits that selectively adjust an operating voltage for the blocks in response to control signals. During operation of the PLD, the control signals are updated in response to externally-generated signals provided to the PLD via the test pin set and routed to the logic blocks using the test circuit.

摘要翻译： PLD包括多个逻辑块，测试电路和测试引脚组。 逻辑块耦合到选通电路，门电路响应于控制信号选择性地调整块的工作电压。 在PLD的操作期间，响应于通过测试引脚设置到PLD的外部产生的信号来更新控制信号，并使用测试电路将其传送到逻辑块。