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    INTERCONNECT STRUCTURES WITH PARTIALLY SELF ALIGNED VIAS AND METHODS TO PRODUCE SAME
    1.
    发明申请
    INTERCONNECT STRUCTURES WITH PARTIALLY SELF ALIGNED VIAS AND METHODS TO PRODUCE SAME 审中-公开
    具有部分自对准VIAS的互连结构及其生产方法

    公开(公告)号：US20090200683A1

    公开(公告)日：2009-08-13

    申请号：US12030756

    申请日：2008-02-13

    申请人： Matthew Earl Colburn ,  Nicholas C. Fuller ,  Elbert Huang ,  Satyanarayana V. Nitta

    发明人： Matthew Earl Colburn ,  Nicholas C. Fuller ,  Elbert Huang ,  Satyanarayana V. Nitta

    IPC分类号： H01L23/48 ,  H01L21/4763

    CPC分类号： H01L21/76811 ,  H01L21/76813

    摘要： An interconnect structure having partially self aligned vias with an interlayer dielectric layer on a substrate, containing at least two conducting metal lines that traverse parallel to the substrate and at least two conducting metal vias that are orthogonal to the substrate. A method of producing the self aligned vias by depositing an interlayer dielectric layer onto a substrate, depositing at least one hardmask onto the interlayer dielectric layer, lithographically forming a via pattern with elongated via features and lithographically forming a line pattern in either order, then either transferring the line patterns first into the interlayer dielectric layer forming line features or transferring the via pattern first into the interlayer dielectric layer as long as the patterns overlap to forming self aligned via features, depositing conducting metals and filling regions corresponding to the line and via features, and planarizing and removing excess metal from the line and via features.

    摘要翻译： 具有部分自对准的通孔的互连结构，其中在衬底上具有层间电介质层，其包含至少两条横穿平行于衬底的导电金属线和至少两个与衬底正交的导电金属通孔。 一种通过在衬底上沉积层间电介质层来生产自对准通孔的方法，将至少一个硬掩模沉积到层间电介质层上，以光刻方式形成具有细长通孔特征的通孔图案，并以任何顺序光刻形成线图案，然后 只要图案重叠以形成自对准的通孔特征，沉积导电金属和对应于该线的通孔特征的填充区域，首先将线图案首先转移到层间介质层形成线的特征中或者将该通孔图案转移到层间电介质层中 并且从线和通孔特征平坦化和去除多余的金属。

    DUAL DAMASCENE PROCESS FLOW ENABLING MINIMAL ULK FILM MODIFICATION AND ENHANCED STACK INTEGRITY
    2.
    发明申请
    DUAL DAMASCENE PROCESS FLOW ENABLING MINIMAL ULK FILM MODIFICATION AND ENHANCED STACK INTEGRITY 审中-公开
    双重DAMASCENE工艺流程启用最小ULK膜修改和增强堆叠完整性

    公开(公告)号：US20090014880A1

    公开(公告)日：2009-01-15

    申请号：US12236809

    申请日：2008-09-24

    申请人： Timothy J. Dalton ,  Nicholas C. Fuller ,  Satyanarayana V. Nitta

    发明人： Timothy J. Dalton ,  Nicholas C. Fuller ,  Satyanarayana V. Nitta

    IPC分类号： H01L23/532

    CPC分类号： H01L21/76801 ,  H01L21/76808 ,  H01L21/76829

    摘要： Interconnect structures possessing an organosilicate glass interlayer dielectric material with minimal stoichiometeric modification and optionally an intact organic adhesion promoter for use in semiconductor devices are provided herein. The interconnect structure is capable of delivering improved device performance, functionality and reliability owing to the reduced effective dielectric constant of the stack compared with that of those conventionally employed because of the use of a sacrificial polymeric material deposited onto the dielectric and optional organic adhesion promoter during the barrier open step done prior to ashing the patterning material. This sacrificial film protects the dielectric and optional organic adhesion promoter from modification/consumption during the subsequent ashing step during which the polymeric film is removed.

    摘要翻译： 本文提供了具有最小化学计量变化的有机硅酸盐玻璃层间介电材料和任选的用于半导体器件的完整有机粘合促进剂的互连结构。 互连结构能够提供改进的器件性能，功能性和可靠性，因为与常规使用的那些相比，堆叠的有效介电常数降低，因为使用沉积在电介质上的牺牲聚合物材料和任选的有机粘合促进剂 在灰化图案材料之前完成的阻挡层开口步骤。 该牺牲膜在后续的灰化步骤期间保护电介质和任选的有机粘合促进剂免于修饰/消耗，在此期间除去聚合物膜。

    Dual damascene process flow enabling minimal ULK film modification and enhanced stack integrity
    3.
    发明授权
    Dual damascene process flow enabling minimal ULK film modification and enhanced stack integrity 失效
    双镶嵌工艺流程可实现极少的ULK膜修饰和增强的堆叠完整性

    公开(公告)号：US07435676B2

    公开(公告)日：2008-10-14

    申请号：US11328981

    申请日：2006-01-10

    申请人： Timothy J. Dalton ,  Nicholas C. Fuller ,  Satyanarayana V. Nitta

    发明人： Timothy J. Dalton ,  Nicholas C. Fuller ,  Satyanarayana V. Nitta

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76801 ,  H01L21/76808 ,  H01L21/76829

    摘要： Interconnect structures possessing an organosilicate glass interlayer dielectric material with minimal stoichiometeric modification and optionally an intact organic adhesion promoter for use in semiconductor devices are provided herein. The interconnect structure is capable of delivering improved device performance, functionality and reliability owing to the reduced effective dielectric constant of the stack compared with that of those conventionally employed because of the use of a sacrificial polymeric material deposited onto the dielectric and optional organic adhesion promoter during the barrier open step done prior to ashing the patterning material. This sacrificial film protects the dielectric and optional organic adhesion promoter from modification/consumption during the subsequent ashing step during which the polymeric film is removed.

    摘要翻译： 本文提供了具有最小化学计量变化的有机硅酸盐玻璃层间介电材料和任选的用于半导体器件的完整有机粘合促进剂的互连结构。 互连结构能够提供改进的器件性能，功能性和可靠性，因为与常规使用的那些相比，堆叠的有效介电常数降低，因为使用沉积在电介质上的牺牲聚合物材料和任选的有机粘合促进剂 在灰化图案材料之前完成的阻挡层开口步骤。 该牺牲膜在后续的灰化步骤期间保护电介质和任选的有机粘合促进剂免于修饰/消耗，在此期间除去聚合物膜。

    METHODOLOGY FOR FABRICATING ISOTROPICALLY SOURCE REGIONS OF CMOS TRANSISTORS
    5.
    发明申请
    METHODOLOGY FOR FABRICATING ISOTROPICALLY SOURCE REGIONS OF CMOS TRANSISTORS 审中-公开
    制造CMOS晶体管等电源区的方法

    公开(公告)号：US20110278580A1

    公开(公告)日：2011-11-17

    申请号：US12779079

    申请日：2010-05-13

    申请人： Nicholas C. Fuller ,  Steve Koester ,  Isaac Lauer ,  Ying Zhang

    发明人： Nicholas C. Fuller ,  Steve Koester ,  Isaac Lauer ,  Ying Zhang

    IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L29/04 ,  H01L21/311

    CPC分类号： H01L29/78675 ,  H01L21/3065 ,  H01L21/3083 ,  H01L21/84 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/7848 ,  H01L29/78618 ,  H01L29/78654

    摘要： A method for fabricating recessed source regions of aggressively scaled CMOS devices. In this method a processing sequence of plasma etch, deposition, followed by plasma etch is used to controllably form recessed regions of the source in the channel of a thin body, much less than 40 nm, device to enable subsequent epitaxial growth of SiGe, SiC, or other materials, and a consequent increase in the device and ring oscillator performance. A Field Effect Transistor device is also provided, which includes: a buried oxide layer; a silicon layer above the buried oxide layer; an isotropically recessed source region; and a gate stack which includes a gate dielectric, a conductive material, and a spacer.

    摘要翻译： 一种用于制造积极缩放CMOS器件的凹陷源区的方法。 在该方法中，使用等离子体蚀刻，沉积，随后进行等离子体蚀刻的处理顺序可控制地在薄体的沟道中形成远远小于40nm的器件的源极的凹陷区域，以使SiGe，SiC的后续外延生长 ，或其他材料，并且随之而来的器件和环形振荡器性能的增加。 还提供场效应晶体管器件，其包括：掩埋氧化物层; 掩埋氧化物层上方的硅层; 各向同性凹陷的源区; 以及包括栅极电介质，导电材料和间隔物的栅极堆叠。

    METHODOLOGY FOR FABRICATING ISOTROPICALLY RECESSED SOURCE REGIONS OF CMOS TRANSISTORS
    7.
    发明申请
    METHODOLOGY FOR FABRICATING ISOTROPICALLY RECESSED SOURCE REGIONS OF CMOS TRANSISTORS 审中-公开
    制造CMOS晶体管等离子体源区的方法

    公开(公告)号：US20120305928A1

    公开(公告)日：2012-12-06

    申请号：US13565035

    申请日：2012-08-02

    申请人： Nicholas C. Fuller ,  Steve Koester ,  Isaac Lauer ,  Ying Zhang

    发明人： Nicholas C. Fuller ,  Steve Koester ,  Isaac Lauer ,  Ying Zhang

    IPC分类号： H01L29/786

    CPC分类号： H01L29/78675 ,  H01L21/3065 ,  H01L21/3083 ,  H01L21/84 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/7848 ,  H01L29/78618 ,  H01L29/78654

    摘要： A Field Effect Transistor (FET) device includes a gate stack formed over a channel region, a source region adjacent to the channel region, wherein a portion of a boundary between the source region and the channel region is defined along a plane defined by a sidewall of the gate stack, a drain region adjacent to the channel region, a portion of the drain region arranged below the gate stack, a native oxide layer disposed over a portion of the source region, along sidewalls of the gate stack, and over a portion of the drain region, a spacer arranged over a portion of the native oxide layer above the source region and the drain region and along the native oxide layer along the sidewalls of the gate stack.

    摘要翻译： 场效应晶体管（FET）器件包括形成在通道区域上的栅极堆叠，与沟道区域相邻的源极区域，其中源极区域和沟道区域之间的边界的一部分沿着由侧壁 栅极堆叠的漏极区域，与沟道区域相邻的漏极区域，布置在栅极堆叠下方的漏极区域的一部分，沿着栅极堆叠的侧壁设置在源极区域的一部分上的自然氧化物层， 漏极区域上的间隔物，其间隔设置在源极区域和漏极区域上方的自然氧化物层的一部分上，并且沿着栅极叠层的侧壁沿着天然氧化物层。

    METHODOLOGY FOR FABRICATING ISOTROPICALLY RECESSED SOURCE AND DRAIN REGIONS OF CMOS TRANSISTORS
    8.
    发明申请
    METHODOLOGY FOR FABRICATING ISOTROPICALLY RECESSED SOURCE AND DRAIN REGIONS OF CMOS TRANSISTORS 有权
    制造CMOS晶体管等离子体源和漏区的方法

    公开(公告)号：US20110278673A1

    公开(公告)日：2011-11-17

    申请号：US12779100

    申请日：2010-05-13

    申请人： Nicholas C. Fuller ,  Steve Koester ,  Isaac Lauer ,  Ying Zhang

    发明人： Nicholas C. Fuller ,  Steve Koester ,  Isaac Lauer ,  Ying Zhang

    IPC分类号： H01L29/786 ,  H01L21/306

    CPC分类号： H01L29/66636 ,  H01L21/3065 ,  H01L21/3083 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L21/84 ,  H01L29/66772 ,  H01L29/7848

    摘要： A method for fabricating recessed source and recessed drain regions of aggressively scaled CMOS devices. In this method a processing sequence of plasma etch, deposition, followed by plasma etch is used to controllably form recessed regions of the source and the drain in the channel of a thin body, much less than 40 nm, device to enable subsequent epitaxial growth of SiGe, SiC, or other materials, and a consequent increase in the device and ring oscillator performance. A Field Effect Transistor device is also provided, which includes: a buried oxide layer; a silicon layer above the buried oxide layer; an isotropically recessed source region; an isotropically recessed drain region; and a gate stack which includes a gate dielectric, a conductive material, and a spacer.

    摘要翻译： 一种用于制造大型CMOS器件的凹陷源极和凹陷漏极区域的方法。 在该方法中，使用等离子体蚀刻，沉积，随后是等离子体蚀刻的处理顺序可控制地形成薄体的通道中的源极和漏极的凹陷区域，远小于40nm的器件，以实现随后的外延生长 SiGe，SiC或其他材料，从而导致器件和环形振荡器性能的提高。 还提供场效应晶体管器件，其包括：掩埋氧化物层; 掩埋氧化物层上方的硅层; 各向同性凹陷的源区; 各向同性凹陷的漏极区域; 以及包括栅极电介质，导电材料和间隔物的栅极堆叠。

    Mixed lithography with dual resist and a single pattern transfer
    9.
    发明授权
    Mixed lithography with dual resist and a single pattern transfer 有权
    具有双光栅和单一图案转印的混合光刻

    公开(公告)号：US07914970B2

    公开(公告)日：2011-03-29

    申请号：US11867428

    申请日：2007-10-04

    申请人： Nicholas C. Fuller ,  Michael A. Guillorn ,  Balasubramanian S. Pranatharthi Haran ,  Jyotica V. Patel

    发明人： Nicholas C. Fuller ,  Michael A. Guillorn ,  Balasubramanian S. Pranatharthi Haran ,  Jyotica V. Patel

    IPC分类号： G03C5/00

    CPC分类号： G03F7/0035 ,  Y10S430/143 ,  Y10T428/24612 ,  Y10T428/24802

    摘要： An inorganic electron beam sensitive oxide layer is formed on a carbon based material layer or an underlying layer. The inorganic electron beam sensitive oxide layer is exposed with an electron beam and developed to form patterned oxide regions. An ultraviolet sensitive photoresist layer is applied over the patterned oxide regions and exposed surfaces of the carbon based material layer, and subsequently exposed with an ultraviolet radiation and developed. The combined pattern of the patterned ultraviolet sensitive photoresist and the patterned oxide regions is transferred into the carbon based material layer, and subsequently into the underlying layer to form trenches. The carbon based material layer serves as a robust mask for performing additional pattern transfer into the underlying layer, and may be easily stripped afterwards. The patterned ultraviolet sensitive photoresist, the patterned oxide regions, and the patterned carbon based material layer are subsequently removed.

    摘要翻译： 在碳基材料层或下层上形成无机电子束敏感氧化物层。 无机电子束敏感氧化层用电子束曝光并显影以形成图案化氧化物区域。 将紫外线敏感的光致抗蚀剂层施加在图案化的氧化物区域和碳基材料层的暴露表面上，随后用紫外线照射并显影。 图案化紫外光敏光致抗蚀剂和图案化氧化物区域的组合图案被转移到碳基材料层中，随后进入下层以形成沟槽。 碳基材料层用作用于执行额外图案转移到下层中的鲁棒掩模，并且之后可以容易地剥离。 随后去除图案化的紫外线敏感光刻胶，图案化氧化物区域和图案化的碳基材料层。