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    Chemical optimization during wastewater treatment, odor control and uses thereof
    2.
    发明授权
    Chemical optimization during wastewater treatment, odor control and uses thereof 有权

    公开(公告)号：US10435316B2

    公开(公告)日：2019-10-08

    申请号：US13247138

    申请日：2011-09-28

    申请人： Brian Reed ,  Carla Dillon

    发明人： Brian Reed ,  Carla Dillon

    IPC分类号： C02F1/52 ,  C02F1/66 ,  C02F1/72 ,  C02F101/10

    摘要： Compositions for the use of sewage or wastewater treatment, controlling odors or a combination thereof are disclosed, wherein the composition comprises at least one iron-based compound. Furthermore, methods of reducing the odors in a sewage or wastewater system are disclosed that include: adding a composition comprising at least one iron-based compound to a sewage or wastewater system. As used herein, the phrase “at least one iron-based compound” includes ferrous chloride, ferric chloride, ferrous sulfate, ferrate, polyferric sulfate, Ferix-3 (Fe2(SO4)3H2O) or a combination thereof.

    CHEMICAL OPTIMIZATION DURING WASTEWATER TREATMENT, ODOR CONTROL AND USES THEREOF
    4.
    发明申请
    CHEMICAL OPTIMIZATION DURING WASTEWATER TREATMENT, ODOR CONTROL AND USES THEREOF 审中-公开
    废水处理中的化学优化，气味控制及其用途

    公开(公告)号：US20120141407A1

    公开(公告)日：2012-06-07

    申请号：US13247138

    申请日：2011-09-28

    申请人： Carla Dillon ,  Brian Reed ,  Talebi Mahin

    发明人： Carla Dillon ,  Brian Reed ,  Talebi Mahin

    IPC分类号： C02F1/68 ,  C01G49/14 ,  C01G49/00 ,  C01G49/10

    CPC分类号： C02F1/5245 ,  C02F1/66 ,  C02F1/722 ,  C02F2101/101 ,  C02F2303/02 ,  C02F2307/08

    摘要： Compositions for the use of sewage or wastewater treatment, controlling odors or a combination thereof are disclosed, wherein the composition comprises at least one iron-based compound. Furthermore, methods of reducing the odors in a sewage or wastewater system are disclosed that include: adding a composition comprising at least one iron-based compound to a sewage or wastewater system. As used herein, the phrase “at least one iron-based compound” includes ferrous chloride, ferric chloride, ferrous sulfate, ferrate, polyferric sulfate, Ferix-3 (Fe2(SO4)3H2O) or a combination thereof.

    摘要翻译： 公开了用于污水或废水处理，控制气味或其组合的组合物，其中所述组合物包含至少一种铁基化合物。 此外，公开了减少污水或废水系统中的气味的方法，其包括：向污水或废水系统中加入包含至少一种铁基化合物的组合物。 如本文所用，短语“至少一种铁基化合物”包括氯化亚铁，氯化铁，硫酸亚铁，高铁酸盐，聚硫酸铁，Ferix-3（Fe 2（SO 4）3 H 2 O）或其组合。

    Methods for Controlling Microloading Variation in Semiconductor Wafer Layout and Fabrication
    5.
    发明申请
    Methods for Controlling Microloading Variation in Semiconductor Wafer Layout and Fabrication 有权
    控制半导体晶片布局和制造中微加载变化的方法

    公开(公告)号：US20100031211A1

    公开(公告)日：2010-02-04

    申请号：US12512932

    申请日：2009-07-30

    申请人： Brian Reed ,  Michael C. Smayling

    发明人： Brian Reed ,  Michael C. Smayling

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5081 ,  G06F2217/12 ,  Y02P90/265

    摘要： Problematic open areas are identified in a semiconductor wafer layout. The problematic open areas have a size variation relative to one or more neighboring open areas of the layout sufficient to cause adverse microloading variation. In one embodiment, the adverse microloading variation is controlled by shifting a number of layout features to interdict the problematic open areas. In another embodiment, the adverse microloading variation is controlled by defining and placing a number of dummy layout features to shield actual layout features that neighbor the problematic open areas. In another embodiment, the adverse microloading variation is controlled by utilizing sacrificial layout features which are actually fabricated on the wafer temporarily to eliminate microloading variation, and which are subsequently removed from the wafer to leave behind the desired permanent structures.

    摘要翻译： 在半导体晶片布局中识别有问题的开放区域。 有问题的开放区域相对于布局的一个或多个相邻开放区域具有尺寸变化，足以导致不利的微加载变化。 在一个实施例中，通过移动多个布局特征来阻止有问题的开放区域来控制不利的微加载变化。 在另一个实施例中，通过限定和放置多个虚拟布局特征来屏蔽相邻有问题的开放区域的实际布局特征来控制不利的微加载变化。 在另一个实施例中，通过利用实际上在晶片上制造的牺牲布局特征来暂时控制不利的微加载变化，以消除微载荷变化，并随后从晶片上移除留下期望的永久结构。

    Feed-forward circuit for reducing delay through an input buffer
    6.
    发明申请
    Feed-forward circuit for reducing delay through an input buffer 有权
    前馈电路，用于通过输入缓冲器减少延迟

    公开(公告)号：US20050156642A1

    公开(公告)日：2005-07-21

    申请号：US10759339

    申请日：2004-01-16

    申请人： Scott Becker ,  Brian Reed ,  Puneet Sawhney ,  Jayanth Thyamagundlam

    发明人： Scott Becker ,  Brian Reed ,  Puneet Sawhney ,  Jayanth Thyamagundlam

    IPC分类号： H03K19/017 ,  H03B1/00

    CPC分类号： H03K19/01707

    摘要： An invention is provided for a feed forward circuit that reduces delay through an inverting circuit. The feed forward circuit includes an inverter having an input and an output, and an inverting circuit having an input and an output. The input of the inverting circuit is coupled to the output of the inverter. A feed forward transistor having a gate coupled to the input of the inverter and a terminal coupled to the output of the inverting circuit also is included. In operation the feed forward transistor decreases the amount of time required for the output of the inverting circuit to change state. In sum, the invention reduces the delay when the inverting circuit transitions to a high state, without affecting the timing of the transition to a low state.

    摘要翻译： 提供了一种用于减少通过反相电路的延迟的前馈电路的发明。 前馈电路包括具有输入和输出的反相器和具有输入和输出的反相电路。 反相电路的输入耦合到逆变器的输出端。 还包括具有耦合到反相器的输入端的栅极和耦合到反相电路的输出的端子的前馈晶体管。 在操作中，前馈晶体管减小了反相电路的输出改变状态所需的时间量。 总之，本发明减小了当反相电路转变到高电平状态时的延迟，而不会影响转换到低电平的时序。

    Multi-channel game puzzle with movable base
    7.
    发明授权
    Multi-channel game puzzle with movable base 失效
    多通道游戏拼图与可移动基座

    公开(公告)号：US5332221A

    公开(公告)日：1994-07-26

    申请号：US81497

    申请日：1993-06-22

    申请人： Brian Reed

    发明人： Brian Reed

    IPC分类号： A63F9/08 ,  A63F9/12

    CPC分类号： A63F7/044 ,  A63F9/083 ,  A63F2007/4043

    摘要： A multi-channel game puzzle with movable base utilizing manual tilting employing the multi-channel game puzzle, the game puzzle including a housing defining a main chamber and having a vertical axis further including a plurality of channels positioned in a common plane within the main chamber being equally spaced and extending radially outward, a central hub having a socket cooperating with a movable shaft for rotably mounting the central hub within the main chamber about the common vertical axis movement reciprocally between an upper locked position for locking the playing pieces in the channels and a lower free swivel position for permitting free swiveling of the inner chamber relative to the housing upon manual tilting of the housing between a first communication position, a second communication position, a third communication position and a fourth communication position and including a plurality of sets of game pieces each set having like marked game pieces also including a unitary blocker piece having distinctive marking characteristics wherein play is commenced by a player grasping the outer surface of the housing, releasing the hub to the free swivel position and tilting to urge the game pieces from one channel from one channel to another and to rotate the central hub relative to the housing for accepting and discharging player pieces for rearrangement of the sequence.

    摘要翻译： 一种使用多通道游戏益智的手动倾斜的可移动底座的多通道游戏难题，游戏难题包括限定主室的壳体，并且具有垂直轴线，该竖直轴线还包括位于主室内的公共平面中的多个通道 间隔开并径向向外延伸的中心轮毂，其具有与可动轴配合的插座，用于将主中心毂可旋转地安装在主腔室内围绕公共垂直轴线在用于锁定通道中的玩具的上锁定位置之间往复运动; 较低的自由旋转位置，用于当在第一通信位置，第二通信位置，第三通信位置和第四通信位置之间手动倾斜壳体时允许内腔相对于壳体的自由旋转，并且包括多组 游戏作品中的每一个都具有像标记的游戏作品，也包括一个单一的 具有独特标记特征的阻挡件，其中玩家从握住壳体的外表面开始玩游戏，将轮毂释放到自由旋转位置和倾斜，以将游戏件从一个通道推动到另一个通道，并使中心毂 相对于用于接收和排出玩家片段以重新排列序列的壳体。

    Methods for controlling microloading variation in semiconductor wafer layout and fabrication
    8.
    发明授权
    Methods for controlling microloading variation in semiconductor wafer layout and fabrication 有权
    用于控制半导体晶片布局和制造中的微加载变化的方法

    公开(公告)号：US09122832B2

    公开(公告)日：2015-09-01

    申请号：US12512932

    申请日：2009-07-30

    申请人： Brian Reed ,  Michael C. Smayling ,  Scott T. Becker

    发明人： Brian Reed ,  Michael C. Smayling ,  Scott T. Becker

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5081 ,  G06F2217/12 ,  Y02P90/265

    摘要： Problematic open areas are identified in a semiconductor wafer layout. The problematic open areas have a size variation relative to one or more neighboring open areas of the layout sufficient to cause adverse microloading variation. In one embodiment, the adverse microloading variation is controlled by shifting a number of layout features to interdict the problematic open areas. In another embodiment, the adverse microloading variation is controlled by defining and placing a number of dummy layout features to shield actual layout features that neighbor the problematic open areas. In another embodiment, the adverse microloading variation is controlled by utilizing sacrificial layout features which are actually fabricated on the wafer temporarily to eliminate microloading variation, and which are subsequently removed from the wafer to leave behind the desired permanent structures.

    摘要翻译： 在半导体晶片布局中识别有问题的开放区域。 有问题的开放区域相对于布局的一个或多个相邻开放区域具有尺寸变化，足以导致不利的微加载变化。 在一个实施例中，通过移动多个布局特征来阻止有问题的开放区域来控制不利的微加载变化。 在另一个实施例中，通过限定和放置多个虚拟布局特征来屏蔽相邻有问题的开放区域的实际布局特征来控制不利的微加载变化。 在另一个实施例中，通过利用实际上在晶片上制造的牺牲布局特征来暂时控制不利的微加载变化，以消除微载荷变化，并且随后从晶片中移除留下期望的永久结构。

    Methods for Defining and Utilizing Sub-Resolution Features in Linear Topology
    9.
    发明申请
    Methods for Defining and Utilizing Sub-Resolution Features in Linear Topology 有权
    定义和利用线性拓扑中的分解特征的方法

    公开(公告)号：US20090300574A1

    公开(公告)日：2009-12-03

    申请号：US12479674

    申请日：2009-06-05

    申请人： Brian Reed ,  Michael C. Smayling ,  Joseph N. Hong ,  Stephen Fairbanks

    发明人： Brian Reed ,  Michael C. Smayling ,  Joseph N. Hong ,  Stephen Fairbanks

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5068 ,  G03F1/36 ,  G06F2217/12 ,  Y02P90/265

    摘要： Regular layout shapes are placed in accordance with a virtual grate. A determination is made as to whether an unoccupied layout space adjacent to a regular layout shape to be reinforced, and extending in a direction perpendicular to the regular layout shape, is large enough to support placement of a sub-resolution shape. Upon determining that the unoccupied layout space is large enough to support placement of the sub-resolution shape, the sub-resolution shape is placed so as to be substantially centered upon a virtual line of the virtual grate within the unoccupied layout space. Also, one or more sub-resolution shapes are placed between and parallel with neighboring regular layout shapes when windows of lithographic reinforcement associated with each of the neighboring regular layout shapes permit. The sub-resolution shapes may be placed according to a virtual grate, or may be placed based on proximity to edges of the neighboring regular layout shapes.

    摘要翻译： 正常的布局形状根据虚拟炉排放置。 确定与正规布局形状相邻的未被占用的布局空间是否被加强并且沿与正常布局形状垂直的方向延伸的尺寸足够大以支持分分辨率形状的放置。 在确定未占用的布局空间足够大以支持分分辨率形状的放置时，子分辨率形状被放置为基本上位于未占用的布局空间内的虚拟格栅的虚拟线上。 此外，当与相邻的规则布局形状中的每一个相关联的光刻加固件的窗口允许时，一个或多个子分辨率形状被放置在相邻的规则布局形状之间并与其平行。 子分辨率形状可以根据虚拟格栅放置，或者可以基于邻近的规则布局形状的边缘的位置放置。