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24 条记录 (耗时 0.035 秒)

    Blocking processing restrictions based on addresses
    1.
    发明授权
    Blocking processing restrictions based on addresses 有权
    基于地址的阻塞处理限制

    公开(公告)号：US06996698B2

    公开(公告)日：2006-02-07

    申请号：US10435961

    申请日：2003-05-12

    申请人： Timothy J. Slegel ,  Jane H. Bartik ,  Lisa C. Heller ,  Erwin F. Pfeffer ,  Ute Gaertner

    发明人： Timothy J. Slegel ,  Jane H. Bartik ,  Lisa C. Heller ,  Erwin F. Pfeffer ,  Ute Gaertner

    IPC分类号： G06F12/00

    CPC分类号： G06F12/1475 ,  G06F12/1036

    摘要： Processing restrictions of a computing environment are filtered and blocked, in certain circumstances, such that processing continues despite the restrictions. One restriction includes an indication that fetching of storage keys is prohibited, in response to a buffer miss. When a processing unit of the computing environment is met with this restriction, it performs a comparison of addresses, which indicates whether the fetching can continue. If fetching can continue, the restriction is ignored.

    摘要翻译： 在某些情况下，计算环境的处理限制被过滤和阻止，使处理继续，尽管有限制。 一个限制包括响应于缓冲区未命中而禁止取出存储密钥的指示。 当计算环境的处理单元满足该限制时，它执行地址的比较，其指示获取是否可以继续。 如果提取可以继续，限制将被忽略。

    Method, system and computer program product for an even sampling spread over differing clock domain boundaries
    9.
    发明授权
    Method, system and computer program product for an even sampling spread over differing clock domain boundaries 失效
    方法，系统和计算机程序产品，用于在不同的时钟域边界上进行均匀采样

    公开(公告)号：US07983372B2

    公开(公告)日：2011-07-19

    申请号：US12031158

    申请日：2008-02-14

    申请人： Jane H. Bartik ,  Willm Hinrichs ,  Martin Recktenwald ,  Patrick M. West, Jr.

    发明人： Jane H. Bartik ,  Willm Hinrichs ,  Martin Recktenwald ,  Patrick M. West, Jr.

    IPC分类号： H04L7/00

    CPC分类号： H04L7/0008

    摘要： The present invention relates to a method, computer program product and system for generating a sample signal from differing clock domain boundaries. The system comprises a cycle base component, a sample offset component being configured to receive a time-based sample pulse signal, and logic to generate a sample pulse. The sample pulse generation logic is configured to receive a time-based sample pulse signal, a free running counter value, a sample offset counter value, and deliver a sample pulse signal.

    摘要翻译： 本发明涉及一种用于从不同时钟域边界产生采样信号的方法，计算机程序产品和系统。 该系统包括循环基础组件，被配置为接收基于时间的采样脉冲信号的采样偏移分量和用于产生采样脉冲的逻辑。 采样脉冲发生逻辑被配置为接收基于时间的采样脉冲信号，自由运行计数器值，采样偏移计数器值，并且传送采样脉冲信号。

    MICROARCHITECTURE, METHOD AND COMPUTER PROGRAM PRODUCT FOR EFFICIENT DATA GATHERING FROM A SET OF TRACE ARRAYS
    10.
    发明申请
    MICROARCHITECTURE, METHOD AND COMPUTER PROGRAM PRODUCT FOR EFFICIENT DATA GATHERING FROM A SET OF TRACE ARRAYS 失效
    微观研究，方法和计算机程序产品，用于从一组跟踪阵列高效数据收集

    公开(公告)号：US20090217012A1

    公开(公告)日：2009-08-27

    申请号：US12036540

    申请日：2008-02-25

    申请人： Patrick M. West, JR. ,  Jane H. Bartik ,  Martin Recktenwald ,  Chung-Lung K. Shum ,  Scott B. Swaney

    发明人： Patrick M. West, JR. ,  Jane H. Bartik ,  Martin Recktenwald ,  Chung-Lung K. Shum ,  Scott B. Swaney

    IPC分类号： G06F9/22

    CPC分类号： G06F11/3466

    摘要： An architecture for collecting performance data in a processor, that includes: a trace read control unit and a trace data collect unit, each unit coupled to a plurality of trace array and multiplex units for providing performance data, the coupling accomplished by a trace read control bus, a data select bus, a trace row address bus and a data return bus; wherein each of the trace array and multiplex units receives a trace read signal and provides data including trace data and the trace read signal to the trace data collect unit. A method and a computer program product are provided.

    摘要翻译： 一种用于在处理器中收集性能数据的架构，其包括：跟踪读取控制单元和跟踪数据收集单元，每个单元耦合到多个跟踪阵列和用于提供性能数据的多路复用单元，所述耦合由跟踪读取控制 总线，数据选择总线，跟踪行地址总线和数据返回总线; 其中每个跟踪阵列和多路复用单元接收跟踪读取信号，并将跟踪数据和跟踪读取信号的数据提供给跟踪数据收集单元。 提供了一种方法和计算机程序产品。