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公开(公告)号：US08151075B2
公开(公告)日：2012-04-03
申请号：US12692125
申请日：2010-01-22
IPC分类号： G06F12/00
CPC分类号： G06F12/0215 , Y02D10/13
摘要： A method for accessing a memory includes receiving a first address wherein the first address corresponds to a demand fetch, receiving a second address wherein the second address corresponds to a speculative prefetch, providing first data from the memory in response to the demand fetch in which the first data is accessed asynchronous to a system clock, and providing second data from the memory in response to the speculative prefetch in which the second data is accessed synchronous to the system clock. The memory may include a plurality of pipeline stages in which providing the first data in response to the demand fetch is performed such that each pipeline stage is self-timed independent of the system clock and providing the second data in response to the speculative prefetch is performed such that each pipeline stage is timed based on the system clock to be synchronous with the system clock.
摘要翻译： 用于访问存储器的方法包括接收第一地址，其中第一地址对应于需求提取，接收第二地址，其中第二地址对应于推测预取，响应于请求提取从存储器提供第一数据，其中， 第一数据被访问与系统时钟异步，并且响应于与系统时钟同步地访问第二数据的推测预取，从存储器提供第二数据。 存储器可以包括多个流水线级，其中响应于需求提取而提供第一数据被执行，使得每个流水线级是独立于系统时钟的自定时的，并且响应于推测的预取来提供第二数据 使得每个流水线级基于与系统时钟同步的系统时钟来定时。
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公开(公告)号：US20110185146A1
公开(公告)日：2011-07-28
申请号：US12692125
申请日：2010-01-22
CPC分类号： G06F12/0215 , Y02D10/13
摘要： A method for accessing a memory includes receiving a first address wherein the first address corresponds to a demand fetch, receiving a second address wherein the second address corresponds to a speculative prefetch, providing first data from the memory in response to the demand fetch in which the first data is accessed asynchronous to a system clock, and providing second data from the memory in response to the speculative prefetch in which the second data is accessed synchronous to the system clock. The memory may include a plurality of pipeline stages in which providing the first data in response to the demand fetch is performed such that each pipeline stage is self-timed independent of the system clock and providing the second data in response to the speculative prefetch is performed such that each pipeline stage is timed based on the system clock to be synchronous with the system clock.
摘要翻译： 用于访问存储器的方法包括接收第一地址，其中第一地址对应于需求提取，接收第二地址，其中第二地址对应于推测预取，响应于请求提取从存储器提供第一数据，其中， 第一数据被访问与系统时钟异步，并且响应于与系统时钟同步地访问第二数据的推测预取，从存储器提供第二数据。 存储器可以包括多个流水线级，其中响应于需求提取而提供第一数据被执行，使得每个流水线级是独立于系统时钟的自定时的，并且响应于推测的预取来提供第二数据 使得每个流水线级基于与系统时钟同步的系统时钟来定时。
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3.发明授权Threshold voltage techniques for detecting an imminent read failure in a memory array 有权用于检测存储器阵列中即将发生的读取故障的阈值电压技术公开(公告)号：US08504884B2
公开(公告)日：2013-08-06
申请号：US12608405
申请日：2009-10-29
IPC分类号： G11C29/00
CPC分类号： G11C29/50004 , G11C16/26 , G11C29/42 , G11C2029/0411
摘要： A technique for detecting an imminent read failure in a memory array includes determining whether a memory array, which does not exhibit an uncorrectable error correcting code (ECC) read during an initial array integrity check at a normal read verify voltage level, exhibits an uncorrectable ECC read during a subsequent array integrity check at a margin read verify voltage level. The technique also includes providing an indication of an imminent read failure for the memory array when the memory array exhibits an uncorrectable ECC read during the subsequent array integrity check. In this case, the margin read verify voltage level is different from the normal read verify voltage level.
摘要翻译： 用于检测存储器阵列中即将发生的读取故障的技术包括确定在正常读取验证电压电平下的初始阵列完整性检查期间不显示不能校正的纠错码（ECC）的存储器阵列是否显示出不可校正的ECC 在随后的阵列完整性检查期间读取读取验证电压电平。 当在后续阵列完整性检查期间存储器阵列呈现不可校正的ECC读取时，该技术还包括提供针对存储器阵列的迫在眉睫的读取失败的指示。 在这种情况下，余量读取验证电压电平与正常读取验证电压电平不同。
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4.发明授权Error correcting device, method for monitoring an error correcting device and data processing system 有权纠错装置，用于监视纠错装置和数据处理系统的方法公开(公告)号：US09246512B2
公开(公告)日：2016-01-26
申请号：US13988821
申请日：2010-12-02
CPC分类号： H03M13/05 , G06F11/0754 , G06F11/0757 , G06F11/0766 , G06F11/0772 , G06F11/1048
摘要： An error correcting device is provided that has an input connectable to receive one or more data units, an error detection module arranged to identify a presence of one or more errors in a received data unit of the one or more data units and to provide an error detection signal for the received data unit, an error correction module arranged to perform an error correction processing on the received data unit and provide a corrected data unit, and a correction evaluation module arranged to perform a comparison of the received data unit with the corrected data unit and to generate a correction error signal depending on a result of the comparison and the error detection signal.
摘要翻译： 提供了一种错误校正装置，其具有可连接以接收一个或多个数据单元的输入;错误检测模块，被布置为识别所述一个或多个数据单元的接收数据单元中存在一个或多个错误，并提供错误 用于接收数据单元的检测信号;纠错模块，被配置为对所接收的数据单元执行纠错处理，并提供校正数据单元;以及校正评估模块，被配置为执行所接收数据单元与校正数据的比较 并根据比较结果和误差检测信号产生校正误差信号。
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公开(公告)号：US08380918B2
公开(公告)日：2013-02-19
申请号：US12683549
申请日：2010-01-07
IPC分类号： G06F13/00
CPC分类号： G06F12/1425
摘要： A method for tracking alteration of a non-volatile storage includes receiving a request to modify a tracked region of the non-volatile storage. In response to the request, it is determined whether or not a modification of data stored in a non-erasable one-time programmable (NEOTP) alteration log region has occurred. In response to determining that the modification of the data stored in the NEOTP alteration log region has occurred, the tracked region of non-volatile storage is modified in response to the request. In response to determining that the modification of the data stored in the NEOTP alteration log region has not occurred, the request to modify the tracked region of the non-volatile memory is denied.
摘要翻译： 用于跟踪非易失性存储器的改变的方法包括接收修改非易失性存储器的被跟踪区域的请求。 响应于该请求，确定是否发生存储在不可擦除的一次性可编程（NEOTP）改变对数区域中的数据的修改。 响应于确定存储在NEOTP改变日志区域中的数据的修改已经发生，响应于该请求来修改非易失性存储的跟踪区域。 响应于确定没有发生存储在NEOTP改变日志区域中的数据的修改，修改非易失性存储器的跟踪区域的请求被拒绝。
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6.发明申请ERROR CORRECTING DEVICE, METHOD FOR MONITORING AN ERROR CORRECTING DEVICE AND DATA PROCESSING SYSTEM 有权错误校正装置，用于监视错误校正装置和数据处理系统的方法公开(公告)号：US20140189462A1
公开(公告)日：2014-07-03
申请号：US13988821
申请日：2010-12-02
IPC分类号： H03M13/05
CPC分类号： H03M13/05 , G06F11/0754 , G06F11/0757 , G06F11/0766 , G06F11/0772 , G06F11/1048
摘要： An error correcting device is provided that has an input connectable to receive one or more data units, an error detection module arranged to identify a presence of one or more errors in a received data unit of the one or more data units and to provide an error detection signal for the received data unit, an error correction module arranged to perform an error correction processing on the received data unit and provide a corrected data unit, and a correction evaluation module arranged to perform a comparison of the received data unit with the corrected data unit and to generate a correction error signal depending on a result of the comparison and the error detection signal.
摘要翻译： 提供了一种错误校正装置，其具有可连接以接收一个或多个数据单元的输入;错误检测模块，被布置为识别所述一个或多个数据单元的接收数据单元中存在一个或多个错误，并提供错误 用于接收数据单元的检测信号;纠错模块，被配置为对所接收的数据单元执行纠错处理，并提供校正数据单元;以及校正评估模块，被配置为执行所接收数据单元与校正数据的比较 并根据比较结果和误差检测信号产生校正误差信号。
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公开(公告)号：US08261011B2
公开(公告)日：2012-09-04
申请号：US12608548
申请日：2009-10-29
IPC分类号： G06F12/00
CPC分类号： G11C16/10 , G11C16/22 , G11C16/26 , G11C16/3459 , G11C2216/26
摘要： A portion of a programmable memory device is configured as a one-time programmable (OTP) memory, where in response to a write access to the memory device, a memory controller determines whether the write access is associated with a memory location designated as an OTP memory location. If so, the memory controller performs a read of the memory location, and allows the write access only if each memory cell of the memory location is in an un-programmed state. Thus, only a single write access to an OTP memory location is permitted, and subsequent write attempts are disallowed. Further, to enhance detection of programmed cells, the read of the OTP memory location is performed with a lower read voltage than a read voltage associated with a write access to a non-OTP memory location, thereby improving detection of programmed memory cells in the OTP memory location.
摘要翻译： 可编程存储器件的一部分被配置为一次性可编程（OTP）存储器，其中响应于对存储器件的写入访问，存储器控制器确定写访问是否与被指定为OTP的存储器位置相关联 内存位置。 如果是这样，则存储器控制器执行存储器位置的读取，并且仅当存储器位置的每个存储器单元处于未编程状态时才允许写访问。 因此，只允许对OTP存储器位置的单个写入访问，并且不允许后续写入尝试。 此外，为了增强对编程单元的检测，OTP存储器位置的读取以比与非OTP存储器位置的写入访问相关联的读取电压更低的读取电压来执行，从而改进对OTP中的编程存储器单元的检测 内存位置。
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8.发明申请THRESHOLD VOLTAGE TECHNIQUES FOR DETECTING AN IMMINENT READ FAILURE IN A MEMORY ARRAY 有权用于检测存储器阵列中的立即读取故障的阈值电压技术公开(公告)号：US20110107161A1
公开(公告)日：2011-05-05
申请号：US12608405
申请日：2009-10-29
CPC分类号： G11C29/50004 , G11C16/26 , G11C29/42 , G11C2029/0411
摘要： A technique for detecting an imminent read failure in a memory array includes determining whether a memory array, which does not exhibit an uncorrectable error correcting code (ECC) read during an initial array integrity check at a normal read verify voltage level, exhibits an uncorrectable ECC read during a subsequent array integrity check at a margin read verify voltage level. The technique also includes providing an indication of an imminent read failure for the memory array when the memory array exhibits an uncorrectable ECC read during the subsequent array integrity check. In this case, the margin read verify voltage level is different from the normal read verify voltage level.
摘要翻译： 用于检测存储器阵列中即将发生的读取故障的技术包括确定在正常读取验证电压电平下的初始阵列完整性检查期间不显示不能校正的纠错码（ECC）的存储器阵列是否显示出不可校正的ECC 在随后的阵列完整性检查期间读取读取验证电压电平。 当在后续阵列完整性检查期间存储器阵列呈现不可校正的ECC读取时，该技术还包括提供针对存储器阵列的迫在眉睫的读取失败的指示。 在这种情况下，余量读取验证电压电平与正常读取验证电压电平不同。
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公开(公告)号：US20150067314A1
公开(公告)日：2015-03-05
申请号：US14015889
申请日：2013-08-30
申请人： Timothy J. Strauss , Thomas Jew , Kelly K. Taylor
发明人： Timothy J. Strauss , Thomas Jew , Kelly K. Taylor
IPC分类号： G06F21/57
CPC分类号： G06F21/572
摘要： A microcontroller that includes a secure firmware flash controller is provided. The secure firmware flash controller utilizes a hardware assisted boot sequence that performs a firmware code validation. If the firmware code fails validation for any reason, the firmware flash controller locks out access to the firmware RAM and firmware flash controller, and passes control back to the microcontroller for further measures that are protected by security protocols on the microcontroller.
摘要翻译： 提供了一个包含安全固件闪存控制器的微控制器。 安全固件闪存控制器利用执行固件代码验证的硬件辅助引导顺序。 如果固件代码由于任何原因验证失败，固件闪存控制器锁定对固件RAM和固件闪存控制器的访问，并将控制权传回微控制器，以获得受微控制器上安全协议保护的更多措施。
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公开(公告)号：US07624329B2
公开(公告)日：2009-11-24
申请号：US11468638
申请日：2006-08-30
IPC分类号： G11C29/00
CPC分类号： G11C29/44 , G06F11/1068 , G11C16/04 , G11C16/22 , G11C16/3454 , G11C29/52 , G11C2029/0411 , G11C2029/4402 , G11C2229/723
摘要： Methods and apparatus for programming a non-volatile memory array comprising addressable units are provided. The addressable units are configured to store at least a main portion and an error correction portion. An exemplary method for programming the non-volatile memory array includes, in response to a first condition, switching from an error correction enabled mode to an error correction disabled mode and programming at least the main portion of at least one addressable unit of the non-volatile memory array in the error correction disabled mode. The exemplary method further includes, in response to a second condition, switching from the error correction disabled mode to an error correction fill mode and programming at least the error correction portion of the at least one addressable unit of the non-volatile memory array in the error correction fill mode.
摘要翻译： 提供了用于编程包括可寻址单元的非易失性存储器阵列的方法和装置。 可寻址单元被配置为至少存储主要部分和纠错部分。 用于对非易失性存储器阵列进行编程的示例性方法包括响应于第一条件从错误校正允许模式切换到纠错禁止模式，并且至少编程非易失性存储器阵列的至少一个可寻址单元的主要部分， 易失性存储器阵列处于纠错禁用模式。 该示例性方法还包括响应于第二条件，从误差校正禁用模式切换到纠错填充模式，并且至少编程非易失性存储器阵列的至少一个可寻址单元的纠错部分 纠错填充模式。
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