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公开(公告)号：US07624329B2
公开(公告)日：2009-11-24
申请号：US11468638
申请日：2006-08-30
IPC分类号： G11C29/00
CPC分类号： G11C29/44 , G06F11/1068 , G11C16/04 , G11C16/22 , G11C16/3454 , G11C29/52 , G11C2029/0411 , G11C2029/4402 , G11C2229/723
摘要： Methods and apparatus for programming a non-volatile memory array comprising addressable units are provided. The addressable units are configured to store at least a main portion and an error correction portion. An exemplary method for programming the non-volatile memory array includes, in response to a first condition, switching from an error correction enabled mode to an error correction disabled mode and programming at least the main portion of at least one addressable unit of the non-volatile memory array in the error correction disabled mode. The exemplary method further includes, in response to a second condition, switching from the error correction disabled mode to an error correction fill mode and programming at least the error correction portion of the at least one addressable unit of the non-volatile memory array in the error correction fill mode.
摘要翻译： 提供了用于编程包括可寻址单元的非易失性存储器阵列的方法和装置。 可寻址单元被配置为至少存储主要部分和纠错部分。 用于对非易失性存储器阵列进行编程的示例性方法包括响应于第一条件从错误校正允许模式切换到纠错禁止模式，并且至少编程非易失性存储器阵列的至少一个可寻址单元的主要部分， 易失性存储器阵列处于纠错禁用模式。 该示例性方法还包括响应于第二条件，从误差校正禁用模式切换到纠错填充模式，并且至少编程非易失性存储器阵列的至少一个可寻址单元的纠错部分 纠错填充模式。
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公开(公告)号：US20080072117A1
公开(公告)日：2008-03-20
申请号：US11468638
申请日：2006-08-30
IPC分类号： G11C29/00
CPC分类号： G11C29/44 , G06F11/1068 , G11C16/04 , G11C16/22 , G11C16/3454 , G11C29/52 , G11C2029/0411 , G11C2029/4402 , G11C2229/723
摘要： Methods and apparatus for programming a non-volatile memory array comprising addressable units are provided. The addressable units are configured to store at least a main portion and an error correction portion. An exemplary method for programming the non-volatile memory array includes, in response to a first condition, switching from an error correction enabled mode to an error correction disabled mode and programming at least the main portion of at least one addressable unit of the non-volatile memory array in the error correction disabled mode. The exemplary method further includes, in response to a second condition, switching from the error correction disabled mode to an error correction fill mode and programming at least the error correction portion of the at least one addressable unit of the non-volatile memory array in the error correction fill mode.
摘要翻译： 提供了用于编程包括可寻址单元的非易失性存储器阵列的方法和装置。 可寻址单元被配置为至少存储主要部分和纠错部分。 用于对非易失性存储器阵列进行编程的示例性方法包括响应于第一条件从错误校正允许模式切换到纠错禁止模式，并且至少编程非易失性存储器阵列的至少一个可寻址单元的主要部分， 易失性存储器阵列处于纠错禁用模式。 该示例性方法还包括响应于第二条件，从误差校正禁用模式切换到纠错填充模式，并且至少编程非易失性存储器阵列的至少一个可寻址单元的纠错部分 纠错填充模式。
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公开(公告)号：US09685339B2
公开(公告)日：2017-06-20
申请号：US13873917
申请日：2013-04-30
IPC分类号： H01L27/115 , H01L21/28 , H01L29/423 , H01L27/11521
CPC分类号： H01L21/28273 , H01L27/11521 , H01L29/42328 , H01L29/42332
摘要： A split gate memory array includes a first row having memory cells; a second row having memory cells, wherein the second row is adjacent to the first row; and a plurality of segments. Each segment includes a first plurality of memory cells of the first row, a second plurality of memory cells of the second row, a first control gate portion which forms a control gate of each memory cell of the first plurality of memory cells, and a second control gate portion which forms a control gate of each memory cell of the second plurality of memory cells. The first control gate portion and the second control gate portion converge to a single control gate portion between neighboring segments of the plurality of segments.
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公开(公告)号：US09111629B2
公开(公告)日：2015-08-18
申请号：US13441335
申请日：2012-04-06
CPC分类号： G11C16/30 , G11C5/145 , G11C8/08 , G11C16/3454
摘要： A semiconductor memory device includes a non-volatile memory, a memory controller, and a charge pump system. The memory controller establishes first parameters for a first programming cycle of a first plurality of memory cells of the non-volatile memory prior to the first programming cycle being performed. The charge pump system includes a plurality of charge pumps and provides a first programming pulse for use in performing the first program cycle. The first programming pulse is provided by selecting, according to the first parameters, which of the plurality of charge pumps are to be enabled during the first program cycle and which are to be disabled during the first program cycle.
摘要翻译： 半导体存储器件包括非易失性存储器，存储器控制器和电荷泵系统。 存储器控制器在执行第一编程周期之前为非易失性存储器的第一多个存储器单元的第一编程周期建立第一参数。 电荷泵系统包括多个电荷泵并提供用于执行第一程序循环的第一编程脉冲。 第一编程脉冲通过根据第一参数选择在第一编程周期期间启用多个电荷泵中的哪一个并在第一编程周期期间被禁用来提供。
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公开(公告)号：US08971147B2
公开(公告)日：2015-03-03
申请号：US13663636
申请日：2012-10-30
申请人： Gilles Muller , Ronald J. Syzdek
发明人： Gilles Muller , Ronald J. Syzdek
CPC分类号： G11C8/08 , G11C16/0425 , G11C16/0433 , G11C16/08 , G11C16/26 , G11C16/30
摘要： A memory having an array of multi-gate memory cells and a word line driver circuit coupled to a sector of memory cells of the array. In at least one mode of operation, the word line driver circuit is controllable to place an associated control gate word line coupled to the control gate word line driver and coupled to the sector in a floating state during a read operation where the sector is a non selected sector.
摘要翻译： 具有多栅极存储器单元阵列的存储器和耦合到阵列的存储器单元的扇区的字线驱动器电路。 在至少一种操作模式中，字线驱动器电路是可控制的，以将耦合到控制栅极字线驱动器的相关联的控制栅极字线放置在浮动状态下，在读取操作期间扇区是非线性的， 选定部门。
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6.发明申请EMULATED ELECTRICALLY ERASABLE MEMORY HAVING AN ADDRESS RAM FOR DATA STORED IN FLASH MEMORY 审中-公开具有存储在闪存中的数据的地址RAM的模拟电可擦除存储器公开(公告)号：US20130346680A1
公开(公告)日：2013-12-26
申请号：US13530169
申请日：2012-06-22
IPC分类号： G06F12/02
CPC分类号： G06F12/0246 , G06F2212/7201 , G06F2212/7207
摘要： A memory system comprises a memory controller, an address RAM coupled to the memory controller, and a non-volatile memory coupled to the memory controller. The non-volatile memory has an address portion and a data portion. The address portion of the non-volatile memory provides data portion addresses and data portion addresses of valid data to the memory controller. The memory controller loads the data portion addresses and stores them in the address RAM at locations defined by the data portion addresses of valid data into the address RAM. The memory controller uses the data portion addresses, and locations of data blocks within the address RAM, to locate the data blocks within the data portion of non-volatile memory. The memory controller uses the data portion addresses, and locations of the data block addresses within the address RAM, to locate data blocks within the data portion of non-volatile memory
摘要翻译： 存储器系统包括存储器控制器，耦合到存储器控制器的地址RAM以及耦合到存储器控制器的非易失性存储器。 非易失性存储器具有地址部分和数据部分。 非易失性存储器的地址部分向存储器控制器提供有效数据的数据部分地址和数据部分地址。 存储器控制器加载数据部分地址并将它们存储在地址RAM中，在由有效数据的数据部分地址定义的地址到地址RAM中。 存储器控制器使用数据部分地址和地址RAM内的数据块的位置来定位非易失性存储器的数据部分内的数据块。 存储器控制器使用数据部分地址和地址RAM内的数据块地址的位置来定位非易失性存储器的数据部分内的数据块
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公开(公告)号：US07742340B2
公开(公告)日：2010-06-22
申请号：US12048683
申请日：2008-03-14
申请人： Fuchen Mu , Marco A. Cabassi , Ronald J. Syzdek
发明人： Fuchen Mu , Marco A. Cabassi , Ronald J. Syzdek
IPC分类号： G11C16/06
CPC分类号： G11C16/28 , G11C7/14 , G11C11/5642
摘要： A set of reference cells is used for sensing the data values stored at bit cells of a memory device. In response to an event, the reference cell providing the highest output of the set is selected as the reference cell to be used for subsequent memory access operations. The remaining reference cells are disabled so that they can recover back to or near their original non-degraded states. At each successive event, the set of reference cells can be reassessed to identify the reference cell that provides the highest output at that time and the memory device can be reconfigured to utilize the reference cell so identified. By utilizing the reference cell having the highest output to provide the read reference and disabling the remaining reference cells, the likelihood of the read reference falling below a minimum threshold can be reduced.
摘要翻译： 一组参考单元用于感测存储在存储器件的位单元中的数据值。 响应于事件，提供集合的最高输出的参考单元被选择为用于后续存储器存取操作的参考单元。 剩余的参考单元被禁用，使得它们可以恢复到其原始非退化状态或其附近。 在每个连续事件中，可以重新评估参考单元集合以识别在该时间提供最高输出的参考单元，并且可重新配置存储器件以利用如此识别的参考单元。 通过利用具有最高输出的参考单元来提供读取参考并禁用剩余的参考单元，可以减少低于最小阈值的读取参考的可能性。
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公开(公告)号：US20140211559A1
公开(公告)日：2014-07-31
申请号：US13751548
申请日：2013-01-28
IPC分类号： G11C11/40
摘要： A method of programming a split gate memory applies voltages differently to the terminals of the selected cells and the deselected cells. For cells being programming by being coupled to a selected row and a selected column, coupling the control gate to a first voltage, coupling the select gate to a second voltage, programming is achieved by coupling the drain terminal to a current sink that causes the split gate memory cell to be conductive, and coupling the source terminal to a third voltage. For cells not being programmed by not being coupled to a selected row, non-programming is maintained by coupling the control gate to the first voltage, coupling the select gate to a fourth voltage which is greater than a voltage applied to the select gate during a read in which the split gate memory cells are deselected but sufficiently low to prevent programming.
摘要翻译： 编程分离栅极存储器的方法对所选择的单元和未选择的单元的端子不同地施加电压。 对于通过耦合到选定的列和选定的列进行编程的单元，将控制栅极耦合到第一电压，将选择栅极耦合到第二电压，通过将漏极端子耦合到导致分裂的电流阱来实现编程 栅极存储单元导通，并将源极端子耦合到第三电压。 对于不是通过不耦合到所选择的行来编程的单元，通过将控制栅极耦合到第一电压来维持非编程，将选择栅极耦合到第四电压，该第四电压大于施加到选择栅极的电压 读取分离栅极存储单元被取消选择但足够低以防止编程。
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公开(公告)号：US08704587B2
公开(公告)日：2014-04-22
申请号：US13555848
申请日：2012-07-23
CPC分类号： G11C16/30 , G11C5/145 , H02M3/07 , H02M2001/0022
摘要： A configurable multistage charge pump including multiple pumpcells, at least one bypass switch and control logic. The pumpcells are coupled together in series including a first pumpcell receiving an input voltage and at least one remaining pumpcell including a last pumpcell which generates an output voltage. Each bypass switch is coupled to selectively provide the input voltage to a pumpcell input of a corresponding one of the remaining pumpcells. The control logic is configured to determine one of multiple voltage ranges of the input voltage, to enable each pumpcell for a first voltage range and to disable and bypass at least one pumpcell for at least one other voltage range. A method of operating a multistage charge pump including detecting an input voltage, selecting a voltage range based on an input voltage, and enabling a number of cascaded pumpcells corresponding to the selected voltage range.
摘要翻译： 一个可配置的多级电荷泵，包括多个泵浦单元，至少一个旁路开关和控制逻辑。 泵浦单元串联连接在一起，包括接收输入电压的第一泵浦单元和至少一个包括产生输出电压的最后一个泵浦单元的剩余泵浦单元。 每个旁路开关被耦合以选择性地将输入电压提供给相应的剩余泵浦单元的泵单元输入。 控制逻辑被配置为确定输入电压的多个电压范围中的一个，以使得每个泵浦电池能够达到第一电压范围，并且在至少一个其它电压范围内禁用和旁路至少一个泵浦电池。 一种操作多级电荷泵的方法，包括检测输入电压，基于输入电压选择电压范围，以及使能与选定电压范围对应的多个级联泵浦电池。
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公开(公告)号：US20090231925A1
公开(公告)日：2009-09-17
申请号：US12048683
申请日：2008-03-14
申请人： Fuchen Mu , Marco A. Cabassi , Ronald J. Syzdek
发明人： Fuchen Mu , Marco A. Cabassi , Ronald J. Syzdek
CPC分类号： G11C16/28 , G11C7/14 , G11C11/5642
摘要： A set of reference cells is used for sensing the data values stored at bit cells of a memory device. In response to an event, the reference cell providing the highest output of the set is selected as the reference cell to be used for subsequent memory access operations. The remaining reference cells are disabled so that they can recover back to or near their original non-degraded states. At each successive event, the set of reference cells can be reassessed to identify the reference cell that provides the highest output at that time and the memory device can be reconfigured to utilize the reference cell so identified. By utilizing the reference cell having the highest output to provide the read reference and disabling the remaining reference cells, the likelihood of the read reference falling below a minimum threshold can be reduced.
摘要翻译： 一组参考单元用于感测存储在存储器件的位单元中的数据值。 响应于事件，提供集合的最高输出的参考单元被选择为用于后续存储器存取操作的参考单元。 剩余的参考单元被禁用，使得它们可以恢复到其原始非退化状态或其附近。 在每个连续事件中，可以重新评估参考单元集合以识别在该时间提供最高输出的参考单元，并且可重新配置存储器件以利用如此识别的参考单元。 通过利用具有最高输出的参考单元来提供读取参考并禁用剩余的参考单元，可以减少低于最小阈值的读取参考的可能性。
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