-
公开(公告)号：US20120307141A1
公开(公告)日：2012-12-06
申请号：US13194821
申请日：2011-07-29
IPC分类号： H04N7/01
CPC分类号： G06T3/40 , G06F3/1431 , G09G5/005 , G09G5/18 , G09G2340/0414 , G09G2340/0421 , G09G2340/0442 , G09G2370/04 , H04N5/126 , H04N19/61 , H04N19/85
摘要： An inline scaling unit configured to retime an input video frame is disclosed. The scaling unit is configured to receive pixels within a line of a video frame to be displayed on a primary display that is within a first clock domain. The scaling unit down-scales the group of pixels and writes the down-scaled pixels to a buffer circuit in the first clock domain. The scaling unit includes a control circuit configured to generate horizontal and vertical control signals for the retimed video frame to be displayed on a secondary display that is within a second clock domain. The horizontal and vertical control signals are then used to enable reading from the buffer circuit in the second clock domain. The scaling unit outputs the down-scaled pixels and the generated control signals within the retimed video frame such that input video frame and the retimed video frame may be displayed concurrently.
摘要翻译： 公开了配置用于重新输入视频帧的内联缩放单元。 缩放单元被配置为接收要显示在第一时钟域内的主显示器上的视频帧的行内的像素。 缩放单元缩小像素组，并将缩小的像素写入第一时钟域中的缓冲电路。 缩放单元包括控制电路，该控制电路被配置为产生要在第二时钟域内的辅助显示器上显示的重新定时视频帧的水平和垂直控制信号。 然后，水平和垂直控制信号用于使能从第二时钟域中的缓冲电路读取。 缩放单元输出重定时视频帧内的缩小像素和生成的控制信号，使得可以同时显示输入视频帧和重新定时视频帧。
-
公开(公告)号：US20120306926A1
公开(公告)日：2012-12-06
申请号：US13194850
申请日：2011-07-29
IPC分类号： G09G5/00
CPC分类号： G06T3/4007
摘要： A scaling unit is disclosed that is within a computing device having an internal display and an external interface. The scaling unit facilitates the concurrent presentation of images on the internal display and an external display connected to the external interface. In configurations in which the external interface does not have sufficient data width to concurrently display images on the external display at the same resolution as the internal display, the scaling unit may be used to reduce the number of pixels in a line, thus reducing bandwidth requirements at the external interface. The scaling unit may also scale further to maintain an aspect ratio of the image displayed on the internal display. Further vertical scaling may be performed outside the computing device (e.g., by a dongle coupled between the computing device and the external display), such that the scaling unit may be implemented with reduced memory requirements.
摘要翻译： 公开了一种在具有内部显示器和外部接口的计算设备内的缩放单元。 缩放单元便于在内部显示器上同时呈现图像，并且外部显示器连接到外部接口。 在外部接口不具有足够的数据宽度以与外部显示器以与内部显示器相同的分辨率同时显示图像的配置中，缩放单元可以用于减少一行中的像素数量，从而减少带宽需求 在外部接口。 缩放单元还可以进一步缩放以保持在内部显示器上显示的图像的纵横比。 可以在计算设备外部（例如，通过耦合在计算设备和外部显示器之间的加密狗）进行进一步的垂直缩放，使得缩放单元可以以减少的存储器要求来实现。
-
公开(公告)号：US20130057567A1
公开(公告)日：2013-03-07
申请号：US13226604
申请日：2011-09-07
IPC分类号： G09G5/02
CPC分类号： G06F3/1454 , G09G2340/0407 , G09G2340/06
摘要： The same pixel stream may be displayed on an internal display and an external display while maintaining the original aspect ratio corresponding to the internal display dimensions. A connector with limited number of pins may only support a two-wire display port interface to the external display, which may not provide enough bandwidth to transmit the full resolution image to the external display. To transmit the full resolution image, a color space conversion from RGB space to YCbCr color space may be performed. The Luma component may be transmitted at full resolution, while the chroma components may be scaled. Accordingly, there is no loss of image resolution, while some amount of color resolution may be lost. However, there is no need to retime frames within the system on chip (SOC), and the same pixel stream may be used as the basis for display on both the internal and the external display.
摘要翻译： 可以在内部显示器和外部显示器上显示相同的像素流，同时保持对应于内部显示器尺寸的原始宽高比。 具有有限数量引脚的连接器可能仅支持外部显示器的两线显示端口接口，这可能不能提供足够的带宽以将全分辨率图像传输到外部显示器。 为了传输全分辨率图像，可以执行从RGB空间到YCbCr颜色空间的颜色空间转换。 亮度分量可以以全分辨率传输，而色度分量可以被缩放。 因此，不会有图像分辨率的损失，而一些颜色分辨率可能会丢失。 然而，不需要在片上系统（SOC）内重新定时帧，并且可以使用相同的像素流作为在内部和外部显示器上显示的基础。
-
公开(公告)号：US09035961B2
公开(公告)日：2015-05-19
申请号：US13610633
申请日：2012-09-11
申请人： Brijesh Tripathi , Peter F. Holland
发明人： Brijesh Tripathi , Peter F. Holland
CPC分类号： G06F12/0888 , G06F2212/455 , G09G5/001 , G09G5/363 , G09G5/39 , G09G5/395 , G09G2360/121 , G09G2360/123
摘要： A system and method for efficiently allocating data in a memory hierarchy. A system includes a memory controller for controlling accesses to a memory and a display controller for processing video frame data. The memory controller includes a cache capable of storing data read from the memory. A given video frame may be processed by the display controller and presented on a respective display screen. During processing, control logic within the display controller sends multiple memory access requests to the memory controller with cache hint information. For the frame data, the cache hint information may alternate between (i) indicating to store frame data read in response to respective requests in the memory cache and (ii) indicating to not store the frame data read in response to respective requests in the memory cache.
摘要翻译： 一种用于在存储器层级中有效分配数据的系统和方法。 系统包括用于控制对存储器的访问的存储器控制器和用于处理视频帧数据的显示控制器。 存储器控制器包括能够存储从存储器读取的数据的高速缓存器。 给定的视频帧可以由显示控制器处理并呈现在相应的显示屏幕上。 在处理期间，显示控制器内的控制逻辑使用高速缓存提示信息向存储器控制器发送多个存储器访问请求。 对于帧数据，缓存提示信息可以在（i）指示存储响应于存储器高速缓存中的相应请求而读取的帧数据和（ii）指示不存储响应于存储器中的各个请求而读取的帧数据的交替 缓存。
-
公开(公告)号：US20140071140A1
公开(公告)日：2014-03-13
申请号：US13610620
申请日：2012-09-11
摘要： A system and method for efficiently scheduling memory access requests. A semiconductor chip includes a memory controller for controlling accesses to a shared memory and a display controller for processing frame data. In response to detecting an idle state for the system and the supported one or more displays, the display controller aggregates memory requests for a given display pipeline of one or more display pipelines prior to attempting to send any memory requests from the given display pipeline to the memory controller. Arbitration may be performed while the given display pipeline sends the aggregated memory requests. In response to not receiving memory access requests from the functional blocks or the display controller, the memory controller may transition to a low-power mode.
摘要翻译： 一种用于有效地调度存储器访问请求的系统和方法。 半导体芯片包括用于控制对共享存储器的访问的存储器控制器和用于处理帧数据的显示控制器。 响应于检测到系统和所支持的一个或多个显示器的空闲状态，显示控制器在尝试将来自给定显示管道的任何存储器请求发送到所述显示管道之前对一个或多个显示管道的给定显示管线集合存储器请求 内存控制器 可以在给定的显示管道发送聚合的存储器请求时执行仲裁。 响应于不接收来自功能块或显示控制器的存储器访问请求，存储器控制器可以转换到低功率模式。
-
公开(公告)号：US20140075117A1
公开(公告)日：2014-03-13
申请号：US13610633
申请日：2012-09-11
申请人： Brijesh Tripathi , Peter F. Holland
发明人： Brijesh Tripathi , Peter F. Holland
IPC分类号： G06F12/08
CPC分类号： G06F12/0888 , G06F2212/455 , G09G5/001 , G09G5/363 , G09G5/39 , G09G5/395 , G09G2360/121 , G09G2360/123
摘要： A system and method for efficiently allocating data in a memory hierarchy. A system includes a memory controller for controlling accesses to a memory and a display controller for processing video frame data. The memory controller includes a cache capable of storing data read from the memory. A given video frame may be processed by the display controller and presented on a respective display screen. During processing, control logic within the display controller sends multiple memory access requests to the memory controller with cache hint information. For the frame data, the cache hint information may alternate between (i) indicating to store frame data read in response to respective requests in the memory cache and (ii) indicating to not store the frame data read in response to respective requests in the memory cache.
摘要翻译： 一种用于在存储器层级中有效分配数据的系统和方法。 系统包括用于控制对存储器的访问的存储器控制器和用于处理视频帧数据的显示控制器。 存储器控制器包括能够存储从存储器读取的数据的高速缓存器。 给定的视频帧可以由显示控制器处理并呈现在相应的显示屏幕上。 在处理期间，显示控制器内的控制逻辑使用高速缓存提示信息向存储器控制器发送多个存储器访问请求。 对于帧数据，缓存提示信息可以在（i）指示存储响应于存储器高速缓存中的相应请求而读取的帧数据和（ii）指示不存储响应于存储器中的各个请求而读取的帧数据的交替 缓存。
-
公开(公告)号：US08922571B2
公开(公告)日：2014-12-30
申请号：US13610620
申请日：2012-09-11
IPC分类号： G09G5/39
摘要： A system and method for efficiently scheduling memory access requests. A semiconductor chip includes a memory controller for controlling accesses to a shared memory and a display controller for processing frame data. In response to detecting an idle state for the system and the supported one or more displays, the display controller aggregates memory requests for a given display pipeline of one or more display pipelines prior to attempting to send any memory requests from the given display pipeline to the memory controller. Arbitration may be performed while the given display pipeline sends the aggregated memory requests. In response to not receiving memory access requests from the functional blocks or the display controller, the memory controller may transition to a low-power mode.
摘要翻译： 一种用于有效地调度存储器访问请求的系统和方法。 半导体芯片包括用于控制对共享存储器的访问的存储器控制器和用于处理帧数据的显示控制器。 响应于检测到系统和所支持的一个或多个显示器的空闲状态，显示控制器在尝试将来自给定显示管道的任何存储器请求发送到所述显示管道之前对一个或多个显示管道的给定显示管线集合存储器请求 内存控制器 可以在给定的显示管道发送聚合的存储器请求时执行仲裁。 响应于不接收来自功能块或显示控制器的存储器访问请求，存储器控制器可以转换到低功率模式。
-
公开(公告)号：US08675004B2
公开(公告)日：2014-03-18
申请号：US12685171
申请日：2010-01-11
IPC分类号： G06F13/372
摘要： A graphics system may include a display pipe with a buffer configured to store pixels to be processed by a display controller for displaying on a display device, with a buffer control circuit coupled to the buffer to supply pixels to the display controller. When the buffer control circuit detects an underrun of the buffer responsive to the display controller attempting to read pixels from the buffer that have not yet been written to the buffer, the buffer control circuit may supply an underrun pixel to the display. The underrun pixel may be selected from a set of previously stored set of underrun pixels, which may include a most recent valid pixel read by the display controller. A read pointer representative of the location in the buffer from where the display controller is currently attempting to read may be advanced even when an underrun condition occurs. The underrun pixel may be supplied to the display controller until the underrun has been resolved, at which point the most recent valid pixel read from the buffer may be supplied to the display controller.
摘要翻译： 图形系统可以包括具有缓冲器的显示管道，缓冲器被配置为存储要由显示控制器处理的像素，用于在显示设备上显示，缓冲器控制电路耦合到缓冲器以向显示控制器提供像素。 当缓冲器控制电路响应于显示控制器尝试读取尚未写入缓冲器的缓冲器的像素时，缓冲器控制电路检测到欠载，缓冲器控制电路可以向显示器提供欠载像素。 欠载像素可以从先前存储的欠载像素组中选择，其可以包括由显示控制器读取的最新有效像素。 即使在出现欠载条件的情况下，代表显示控制器当前尝试读取的缓冲器中的位置的读取指针也可以被提前。 欠载像素可以被提供给显示控制器，直到欠载已被解析为止，此时从缓冲器读取的最新的有效像素可以被提供给显示控制器。
-
公开(公告)号：US20110169849A1
公开(公告)日：2011-07-14
申请号：US12685171
申请日：2010-01-11
IPC分类号： G09G5/36
摘要： A graphics system may include a display pipe with a buffer configured to store pixels to be processed by a display controller for displaying on a display device, with a buffer control circuit coupled to the buffer to supply pixels to the display controller. When the buffer control circuit detects an underrun of the buffer responsive to the display controller attempting to read pixels from the buffer that have not yet been written to the buffer, the buffer control circuit may supply an underrun pixel to the display. The underrun pixel may be selected from a set of previously stored set of underrun pixels, which may include a most recent valid pixel read by the display controller. A read pointer representative of the location in the buffer from where the display controller is currently attempting to read may be advanced even when an underrun condition occurs. The underrun pixel may be supplied to the display controller until the underrun has been resolved, at which point the most recent valid pixel read from the buffer may be supplied to the display controller.
摘要翻译： 图形系统可以包括具有缓冲器的显示管道，缓冲器被配置为存储要由显示控制器处理的像素，用于在显示设备上显示，缓冲器控制电路耦合到缓冲器以向显示控制器提供像素。 当缓冲器控制电路响应于显示控制器尝试读取尚未写入缓冲器的缓冲器的像素时，缓冲器控制电路检测到欠载，缓冲器控制电路可以向显示器提供欠载像素。 欠载像素可以从先前存储的欠载像素组中选择，其可以包括由显示控制器读取的最新有效像素。 即使在出现欠载条件的情况下，代表显示控制器当前尝试读取的缓冲器中的位置的读取指针也可以被提前。 欠载像素可以被提供给显示控制器，直到欠载已被解析为止，此时从缓冲器读取的最新的有效像素可以被提供给显示控制器。
-
公开(公告)号：US20120131306A1
公开(公告)日：2012-05-24
申请号：US12950293
申请日：2010-11-19
申请人： Joseph P. Bratt , Peter F. Holland
发明人： Joseph P. Bratt , Peter F. Holland
IPC分类号： G06F12/10
CPC分类号： G06F12/0215 , G06F12/0802 , G06F12/0862 , G06F12/1027 , G06F12/123 , G06F2212/302 , G06F2212/654
摘要： In an embodiment, a display pipe includes one or more translation units corresponding to images that the display pipe is reading for display. Each translation unit may be configured to prefetch translations ahead of the image data fetches, which may prevent translation misses in the display pipe (at least in most cases). The translation units may maintain translations in first-in, first-out (FIFO) fashion, and the display pipe fetch hardware may inform the translation unit when a given translation or translation is no longer needed. The translation unit may invalidate the identified translations and prefetch additional translation for virtual pages that are contiguous with the most recently prefetched virtual page.
摘要翻译： 在一个实施例中，显示管道包括与显示管正在读取以供显示的图像对应的一个或多个平移单元。 每个翻译单元可以被配置为在图像数据提取之前预取翻译，这可以防止显示管道中的翻译缺失（至少在大多数情况下）。 翻译单元可以以先入先出（FIFO）方式保持翻译，并且显示管取出硬件可以在不再需要给定的翻译或翻译时通知翻译单元。 翻译单元可以使所识别的翻译失效，并且为与最近预取的虚拟页面连续的虚拟页面预取附加翻译。
-
-
-
-
-
-
-
-
-
搜索结果
27 条记录 (耗时 0.021 秒)
