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    Trigate transistor having extended metal gate electrode
    1.
    发明授权
    Trigate transistor having extended metal gate electrode 有权
    用具有扩展金属栅电极的晶体管

    公开(公告)号：US08120073B2

    公开(公告)日：2012-02-21

    申请号：US12317966

    申请日：2008-12-31

    申请人： Titash Rakshit ,  Stephen M. Cea ,  Jack T Kavalieros ,  Ravi Pillarisetty

    发明人： Titash Rakshit ,  Stephen M. Cea ,  Jack T Kavalieros ,  Ravi Pillarisetty

    IPC分类号： H01L29/06 ,  H01L29/08

    CPC分类号： H01L29/785 ,  H01L29/66795

    摘要： A trigate device having an extended metal gate electrode comprises a semiconductor body having a top surface and opposing sidewalls formed on a substrate, an isolation layer formed on the substrate and around the semiconductor body, wherein a portion of the semiconductor body remains exposed above the isolation layer, and a gate stack formed on the top surface and opposing sidewalls of the semiconductor body, wherein the gate stack extends a depth into the isolation layer, thereby causing a bottom surface of the gate stack to be below a top surface of the isolation layer.

    摘要翻译： 具有延伸的金属栅电极的触发装置包括半导体本体，其具有形成在基板上的顶表面和相对的侧壁，形成在基板上并围绕半导体主体的隔离层，其中半导体主体的一部分保持暴露在隔离物的上方 层，以及形成在半导体主体的顶表面和相对侧壁上的栅极堆叠，其中栅极堆叠将深度延伸到隔离层中，从而使栅极堆叠的底表面在隔离层的顶表面下方 。

    Trigate transistor having extended metal gate electrode
    2.
    发明申请
    Trigate transistor having extended metal gate electrode 有权
    用具有扩展金属栅电极的晶体管

    公开(公告)号：US20100163970A1

    公开(公告)日：2010-07-01

    申请号：US12317966

    申请日：2008-12-31

    申请人： Titash Rakshit ,  Stephen M. Cea ,  Jack T. Kavalieros ,  Ravi Pillarisetty

    发明人： Titash Rakshit ,  Stephen M. Cea ,  Jack T. Kavalieros ,  Ravi Pillarisetty

    IPC分类号： H01L29/78

    CPC分类号： H01L29/785 ,  H01L29/66795

    摘要： A trigate device having an extended metal gate electrode comprises a semiconductor body having a top surface and opposing sidewalls formed on a substrate, an isolation layer formed on the substrate and around the semiconductor body, wherein a portion of the semiconductor body remains exposed above the isolation layer, and a gate stack formed on the top surface and opposing sidewalls of the semiconductor body, wherein the gate stack extends a depth into the isolation layer, thereby causing a bottom surface of the gate stack to be below a top surface of the isolation layer.

    摘要翻译： 具有延伸的金属栅电极的触发装置包括半导体本体，其具有形成在基板上的顶表面和相对的侧壁，形成在基板上并围绕半导体主体的隔离层，其中半导体主体的一部分保持暴露在隔离物的上方 层，以及形成在半导体主体的顶表面和相对侧壁上的栅极堆叠，其中栅极堆叠将深度延伸到隔离层中，从而使栅极堆叠的底表面在隔离层的顶表面下方 。

    Systems And Methods To Increase Uniaxial Compressive Stress In Tri-Gate Transistors
    3.
    发明申请
    Systems And Methods To Increase Uniaxial Compressive Stress In Tri-Gate Transistors 审中-公开
    在三栅晶体管中提高单轴压缩应力的系统和方法

    公开(公告)号：US20090152589A1

    公开(公告)日：2009-06-18

    申请号：US11958275

    申请日：2007-12-17

    申请人： Titash Rakshit ,  Martin D. Giles ,  Tahir Ghani ,  Anand Murthy ,  Stephen M. Cea

    发明人： Titash Rakshit ,  Martin D. Giles ,  Tahir Ghani ,  Anand Murthy ,  Stephen M. Cea

    IPC分类号： H01L29/778 ,  H01L21/8234

    CPC分类号： H01L21/26506 ,  H01L21/823437 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

    摘要： A transistor structure that increases uniaxial compressive stress on the channel region of a tri-gate transistor comprises at least two semiconductor bodies formed on a substrate, each semiconductor body having a pair of laterally opposite sidewalls and a top surface, a common source region formed on one end of the semiconductor bodies, wherein the common source region is coupled to all of the at least two semiconductor bodies, a common drain region formed on another end of the semiconductor bodies, wherein the common drain region is coupled to all of the at least two semiconductor bodies, and a common gate electrode formed over the at least two semiconductor bodies, wherein the common gate electrode provides a gate electrode for each of the at least two semiconductor bodies and wherein the common gate electrode has a pair of laterally opposite sidewalls that are substantially perpendicular to the sidewalls of the semiconductor bodies.

    摘要翻译： 增加三栅极晶体管的沟道区上的单轴压应力的晶体管结构包括形成在衬底上的至少两个半导体本体，每个半导体本体具有一对横向相对的侧壁和顶表面，共同源极区形成在 所述半导体主体的一端，其中所述公共源极区域耦合到所述至少两个半导体主体中的所有半导体主体，形成在所述半导体主体的另一端上的公共漏极区域，其中，所述公共漏极区域至少与所述半导体主体 两个半导体主体和形成在所述至少两个半导体主体上的公共栅电极，其中所述公共栅电极为所述至少两个半导体主体中的每一个提供栅电极，并且其中所述公共栅极具有一对横向相对的侧壁， 基本上垂直于半导体主体的侧壁。

    TWO-DIMENSIONAL CONDENSATION FOR UNIAXIALLY STRAINED SEMICONDUCTOR FINS
    8.
    发明申请
    TWO-DIMENSIONAL CONDENSATION FOR UNIAXIALLY STRAINED SEMICONDUCTOR FINS 有权
    用于非均匀应变半导体FINS的二维冷凝

    公开(公告)号：US20160049513A1

    公开(公告)日：2016-02-18

    申请号：US14882440

    申请日：2015-10-13

    申请人： Jack T. Kavalieros ,  Nancy Zelick ,  Been-Yih Jin ,  Markus Kuhn ,  Stephen M. Cea

    发明人： Jack T. Kavalieros ,  Nancy Zelick ,  Been-Yih Jin ,  Markus Kuhn ,  Stephen M. Cea

    IPC分类号： H01L29/78 ,  H01L29/10 ,  H01L29/165

    CPC分类号： H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/7842 ,  H01L29/7849 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/7854

    摘要： Techniques are disclosed for enabling multi-sided condensation of semiconductor fins. The techniques can be employed, for instance, in fabricating fin-based transistors. In one example case, a strain layer is provided on a bulk substrate. The strain layer is associated with a critical thickness that is dependent on a component of the strain layer, and the strain layer has a thickness lower than or equal to the critical thickness. A fin is formed in the substrate and strain layer, such that the fin includes a substrate portion and a strain layer portion. The fin is oxidized to condense the strain layer portion of the fin, so that a concentration of the component in the strain layer changes from a pre-condensation concentration to a higher post-condensation concentration, thereby causing the critical thickness to be exceeded.

    摘要翻译： 公开了用于实现半导体翅片的多面冷凝的技术。 这些技术可以用于例如制造基于鳍的晶体管。 在一个示例的情况下，在体基板上设置应变层。 应变层与取决于应变层的部件的临界厚度相关联，并且应变层具有低于或等于临界厚度的厚度。 在基板和应变层中形成翅片，使得翅片包括基板部分和应变层部分。 将翅片氧化以冷凝翅片的应变层部分，使得应变层中的组分的浓度从预凝结浓度变为较高的缩合后浓度，从而超过临界厚度。