公开(公告)号：US20160049513A1

公开(公告)日：2016-02-18

申请号：US14882440

申请日：2015-10-13

申请人： Jack T. Kavalieros ,  Nancy Zelick ,  Been-Yih Jin ,  Markus Kuhn ,  Stephen M. Cea

发明人： Jack T. Kavalieros ,  Nancy Zelick ,  Been-Yih Jin ,  Markus Kuhn ,  Stephen M. Cea

IPC分类号： H01L29/78 ,  H01L29/10 ,  H01L29/165

CPC分类号： H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/7842 ,  H01L29/7849 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/7854

摘要： Techniques are disclosed for enabling multi-sided condensation of semiconductor fins. The techniques can be employed, for instance, in fabricating fin-based transistors. In one example case, a strain layer is provided on a bulk substrate. The strain layer is associated with a critical thickness that is dependent on a component of the strain layer, and the strain layer has a thickness lower than or equal to the critical thickness. A fin is formed in the substrate and strain layer, such that the fin includes a substrate portion and a strain layer portion. The fin is oxidized to condense the strain layer portion of the fin, so that a concentration of the component in the strain layer changes from a pre-condensation concentration to a higher post-condensation concentration, thereby causing the critical thickness to be exceeded.

摘要翻译： 公开了用于实现半导体翅片的多面冷凝的技术。 这些技术可以用于例如制造基于鳍的晶体管。 在一个示例的情况下，在体基板上设置应变层。 应变层与取决于应变层的部件的临界厚度相关联，并且应变层具有低于或等于临界厚度的厚度。 在基板和应变层中形成翅片，使得翅片包括基板部分和应变层部分。 将翅片氧化以冷凝翅片的应变层部分，使得应变层中的组分的浓度从预凝结浓度变为较高的缩合后浓度，从而超过临界厚度。

公开(公告)号：US20110147811A1

公开(公告)日：2011-06-23

申请号：US12646427

申请日：2009-12-23

申请人： Jack T. Kavalieros ,  Nancy Zelick ,  Been-Yih Jin ,  Markus Kuhn ,  Stephen M. Cea

发明人： Jack T. Kavalieros ,  Nancy Zelick ,  Been-Yih Jin ,  Markus Kuhn ,  Stephen M. Cea

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/7842 ,  H01L29/7849 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/7854

摘要： Techniques are disclosed for enabling multi-sided condensation of semiconductor fins. The techniques can be employed, for instance, in fabricating fin-based transistors. In one example case, a strain layer is provided on a bulk substrate. The strain layer is associated with a critical thickness that is dependent on a component of the strain layer, and the strain layer has a thickness lower than or equal to the critical thickness. A fin is formed in the substrate and strain layer, such that the fin includes a substrate portion and a strain layer portion. The fin is oxidized to condense the strain layer portion of the fin, so that a concentration of the component in the strain layer changes from a pre-condensation concentration to a higher post-condensation concentration, thereby causing the critical thickness to be exceeded.

摘要翻译： 公开了用于实现半导体翅片的多面冷凝的技术。 这些技术可以用于例如制造基于鳍的晶体管。 在一个示例的情况下，在体基板上设置应变层。 应变层与取决于应变层的部件的临界厚度相关联，并且应变层具有低于或等于临界厚度的厚度。 在基板和应变层中形成翅片，使得翅片包括基板部分和应变层部分。 将翅片氧化以冷凝翅片的应变层部分，使得应变层中的组分的浓度从预凝结浓度变为较高的缩合后浓度，从而超过临界厚度。

公开(公告)号：US09159835B2

公开(公告)日：2015-10-13

申请号：US13488238

申请日：2012-06-04

申请人： Jack T. Kavalieros ,  Nancy Zelick ,  Been-Yih Jin ,  Markus Kuhn ,  Stephen M. Cea

发明人： Jack T. Kavalieros ,  Nancy Zelick ,  Been-Yih Jin ,  Markus Kuhn ,  Stephen M. Cea

IPC分类号： H01L29/66 ,  H01L29/78

CPC分类号： H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/7842 ,  H01L29/7849 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/7854

摘要： Techniques are disclosed for enabling multi-sided condensation of semiconductor fins. The techniques can be employed, for instance, in fabricating fin-based transistors. In one example case, a strain layer is provided on a bulk substrate. The strain layer is associated with a critical thickness that is dependent on a component of the strain layer, and the strain layer has a thickness lower than or equal to the critical thickness. A fin is formed in the substrate and strain layer, such that the fin includes a substrate portion and a strain layer portion. The fin is oxidized to condense the strain layer portion of the fin, so that a concentration of the component in the strain layer changes from a pre-condensation concentration to a higher post-condensation concentration, thereby causing the critical thickness to be exceeded.

摘要翻译： 公开了用于实现半导体翅片的多面冷凝的技术。 这些技术可以用于例如制造基于鳍的晶体管。 在一个示例的情况下，在体基板上设置应变层。 应变层与取决于应变层的部件的临界厚度相关联，并且应变层具有低于或等于临界厚度的厚度。 在基板和应变层中形成翅片，使得翅片包括基板部分和应变层部分。 将翅片氧化以冷凝翅片的应变层部分，使得应变层中的组分的浓度从预凝结浓度变为较高的缩合后浓度，从而超过临界厚度。

公开(公告)号：US09419140B2

公开(公告)日：2016-08-16

申请号：US14882440

申请日：2015-10-13

申请人： Jack T. Kavalieros ,  Nancy Zelick ,  Been-Yih Jin ,  Markus Kuhn ,  Stephen M. Cea

发明人： Jack T. Kavalieros ,  Nancy Zelick ,  Been-Yih Jin ,  Markus Kuhn ,  Stephen M. Cea

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L29/165

CPC分类号： H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/7842 ,  H01L29/7849 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/7854

摘要： Techniques are disclosed for enabling multi-sided condensation of semiconductor fins. The techniques can be employed, for instance, in fabricating fin-based transistors. In one example case, a strain layer is provided on a bulk substrate. The strain layer is associated with a critical thickness that is dependent on a component of the strain layer, and the strain layer has a thickness lower than or equal to the critical thickness. A fin is formed in the substrate and strain layer, such that the fin includes a substrate portion and a strain layer portion. The fin is oxidized to condense the strain layer portion of the fin, so that a concentration of the component in the strain layer changes from a pre-condensation concentration to a higher post-condensation concentration, thereby causing the critical thickness to be exceeded.

公开(公告)号：US20120241818A1

公开(公告)日：2012-09-27

申请号：US13488238

申请日：2012-06-04

申请人： Jack T. Kavalieros ,  Nancy Zelick ,  Been-Yih Jin ,  Markus Kuhn ,  Stephen M. Cea

发明人： Jack T. Kavalieros ,  Nancy Zelick ,  Been-Yih Jin ,  Markus Kuhn ,  Stephen M. Cea

IPC分类号： H01L29/78

CPC分类号： H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/7842 ,  H01L29/7849 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/7854

摘要： Techniques are disclosed for enabling multi-sided condensation of semiconductor fins. The techniques can be employed, for instance, in fabricating fin-based transistors. In one example case, a strain layer is provided on a bulk substrate. The strain layer is associated with a critical thickness that is dependent on a component of the strain layer, and the strain layer has a thickness lower than or equal to the critical thickness. A fin is formed in the substrate and strain layer, such that the fin includes a substrate portion and a strain layer portion. The fin is oxidized to condense the strain layer portion of the fin, so that a concentration of the component in the strain layer changes from a pre-condensation concentration to a higher post-condensation concentration, thereby causing the critical thickness to be exceeded.

摘要翻译： 公开了用于实现半导体翅片的多面冷凝的技术。 这些技术可以用于例如制造基于鳍的晶体管。 在一个示例的情况下，在体基板上设置应变层。 应变层与取决于应变层的部件的临界厚度相关联，并且应变层具有低于或等于临界厚度的厚度。 在基板和应变层中形成翅片，使得翅片包括基板部分和应变层部分。 将翅片氧化以冷凝翅片的应变层部分，使得应变层中的组分的浓度从预凝结浓度变为较高的缩合后浓度，从而超过临界厚度。

公开(公告)号：US08211772B2

公开(公告)日：2012-07-03

申请号：US12646427

申请日：2009-12-23

申请人： Jack T. Kavalieros ,  Nancy M. Zelick ,  Been-Yih Jin ,  Markus Kuhn ,  Stephen M. Cea

发明人： Jack T. Kavalieros ,  Nancy M. Zelick ,  Been-Yih Jin ,  Markus Kuhn ,  Stephen M. Cea

IPC分类号： H01L21/336

CPC分类号： H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/7842 ,  H01L29/7849 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/7854

摘要： Techniques are disclosed for enabling multi-sided condensation of semiconductor fins. The techniques can be employed, for instance, in fabricating fin-based transistors. In one example case, a strain layer is provided on a bulk substrate. The strain layer is associated with a critical thickness that is dependent on a component of the strain layer, and the strain layer has a thickness lower than or equal to the critical thickness. A fin is formed in the substrate and strain layer, such that the fin includes a substrate portion and a strain layer portion. The fin is oxidized to condense the strain layer portion of the fin, so that a concentration of the component in the strain layer changes from a pre-condensation concentration to a higher post-condensation concentration, thereby causing the critical thickness to be exceeded.

摘要翻译： 公开了用于实现半导体翅片的多面冷凝的技术。 这些技术可以用于例如制造基于鳍的晶体管。 在一个示例的情况下，在体基板上设置应变层。 应变层与取决于应变层的部件的临界厚度相关联，并且应变层具有低于或等于临界厚度的厚度。 在基板和应变层中形成翅片，使得翅片包括基板部分和应变层部分。 将翅片氧化以冷凝翅片的应变层部分，使得应变层中的组分的浓度从预凝结浓度变为较高的缩合后浓度，从而超过临界厚度。

公开(公告)号：US20140103396A1

公开(公告)日：2014-04-17

申请号：US14133457

申请日：2013-12-18

申请人： Suman Datta ,  Jack T. Kavalieros ,  Been-Yih Jin

发明人： Suman Datta ,  Jack T. Kavalieros ,  Been-Yih Jin

IPC分类号： H01L29/10 ,  H01L29/78

CPC分类号： H01L29/1033 ,  H01L29/0673 ,  H01L29/201 ,  H01L29/205 ,  H01L29/41725 ,  H01L29/66431 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66787 ,  H01L29/775 ,  H01L29/78 ,  H01L29/785

摘要： A method to form a strain-inducing semiconductor region is described. In one embodiment, formation of a strain-inducing semiconductor region laterally adjacent to a crystalline substrate results in a uniaxial strain imparted to the crystalline substrate, providing a strained crystalline substrate. In another embodiment, a semiconductor region with a crystalline lattice of one or more species of charge-neutral lattice-forming atoms imparts a strain to a crystalline substrate, wherein the lattice constant of the semiconductor region is different from that of the crystalline substrate, and wherein all species of charge-neutral lattice-forming atoms of the semiconductor region are contained in the crystalline substrate.

摘要翻译： 描述形成应变诱导半导体区域的方法。 在一个实施方案中，形成横向邻近晶体衬底的应变诱导半导体区域导致赋予晶体衬底的单轴应变，从而提供应变的晶体衬底。 在另一个实施方案中，具有一种或多种电荷 - 中性晶格形成原子的晶格的半导体区域向晶体衬底赋予应变，其中半导体区域的晶格常数与晶体衬底的晶格常数不同，以及 其中所述半导体区域的电荷 - 中性晶格形成原子的所有种类都包含在所述晶体衬底中。

公开(公告)号：US08120065B2

公开(公告)日：2012-02-21

申请号：US12541763

申请日：2009-08-14

申请人： Suman Datta ,  Justin K. Brask ,  Been-Yih Jin ,  Jack T. Kavalieros ,  Mantu K. Hudait

发明人： Suman Datta ,  Justin K. Brask ,  Been-Yih Jin ,  Jack T. Kavalieros ,  Mantu K. Hudait

IPC分类号： H01L21/02

CPC分类号： H01L29/66636 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/517 ,  H01L29/66628 ,  H01L29/7848 ,  Y10S438/933 ,  Y10S438/938

摘要： Enhancement mode transistors are described where a Group III-N compound is used in the source and drain regions to place tensile strain on the channel. The source and drain regions may be raised or embedded, and fabricated in conjunction with recessed or raised compression regions for p channel transistors.

摘要翻译： 描述了增强模式晶体管，其中在源极和漏极区域中使用III-N族化合物以在通道上施加拉伸应变。 源极和漏极区域可以被凸起或嵌入，并且与用于p沟道晶体管的凹陷或凸起的压缩区域一起制造。

公开(公告)号：US20110180851A1

公开(公告)日：2011-07-28

申请号：US13038190

申请日：2011-03-01

申请人： Brian S. Doyle ,  Been-Yih Jin ,  Jack T. Kavalieros ,  Suman Datta ,  Justin K. Brask ,  Robert S. Chau

发明人： Brian S. Doyle ,  Been-Yih Jin ,  Jack T. Kavalieros ,  Suman Datta ,  Justin K. Brask ,  Robert S. Chau

IPC分类号： H01L29/772

CPC分类号： H01L21/845 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/068 ,  H01L29/1054 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785

摘要： Described herein are a device utilizing a gate electrode material with a single work function for both the pMOS and nMOS transistors where the magnitude of the transistor threshold voltages is modified by semiconductor band engineering and article made thereby. Further described herein are methods of fabricating a device formed of complementary (pMOS and nMOS) transistors having semiconductor channel regions which have been band gap engineered to achieve a low threshold voltage.

摘要翻译： 这里描述了利用具有单功函数的栅电极材料的器件，用于pMOS和nMOS晶体管，其中晶体管阈值电压的幅度由半导体带工程和由此制成的制品修改。 本文进一步描述的是制造由互补（pMOS和nMOS）晶体管形成的器件的方法，该晶体管具有被设计成能够实现低阈值电压的带隙的半导体沟道区。

公开(公告)号：US20110156005A1

公开(公告)日：2011-06-30

申请号：US12655468

申请日：2009-12-30

申请人： Ravi Pillarisetty ,  Been-Yih Jin ,  Benjamin Chu-Kung ,  Matthew V. Metz ,  Jack T. Kavalieros ,  Marko Radosavljevic ,  Roza Kotlyar ,  Willy Rachmady ,  Niloy Mukherjee ,  Gilbert Dewey ,  Robert S. Chau

发明人： Ravi Pillarisetty ,  Been-Yih Jin ,  Benjamin Chu-Kung ,  Matthew V. Metz ,  Jack T. Kavalieros ,  Marko Radosavljevic ,  Roza Kotlyar ,  Willy Rachmady ,  Niloy Mukherjee ,  Gilbert Dewey ,  Robert S. Chau

IPC分类号： H01L29/772

CPC分类号： H01L27/092 ,  H01L21/02532 ,  H01L21/02546 ,  H01L21/283 ,  H01L27/088 ,  H01L29/0653 ,  H01L29/155 ,  H01L29/165 ,  H01L29/267 ,  H01L29/517 ,  H01L29/66431 ,  H01L29/66522 ,  H01L29/66553 ,  H01L29/775 ,  H01L29/7782

摘要： A quantum well transistor has a germanium quantum well channel region. A silicon-containing etch stop layer provides easy placement of a gate dielectric close to the channel. A group III-V barrier layer adds strain to the channel. Graded silicon germanium layers above and below the channel region improve performance. Multiple gate dielectric materials allow use of a high-k value gate dielectric.

摘要翻译： 量子阱晶体管具有锗量子阱沟道区域。 含硅蚀刻停止层提供了靠近通道的栅电介质的容易放置。 III-V族阻挡层增加了通道的应变。 通道区域上方和下方的分级硅锗层提高性能。 多栅极电介质材料允许使用高k值栅极电介质。