公开(公告)号：US20090258472A1

公开(公告)日：2009-10-15

申请号：US11528400

申请日：2006-09-28

申请人： Tobias Florian ,  Michael Graf ,  Stefan Schwantes

发明人： Tobias Florian ,  Michael Graf ,  Stefan Schwantes

IPC分类号： H01L21/762

CPC分类号： H01L29/7824 ,  H01L21/743 ,  H01L21/76205 ,  H01L21/76251 ,  H01L21/76286 ,  H01L23/535 ,  H01L27/1203 ,  H01L29/66681 ,  H01L29/78603 ,  H01L29/78639 ,  H01L2924/0002 ,  H01L2924/00

摘要： Method for manufacturing a semiconductor array, in which a conductive substrate (100), a component region (400), and an insulation layer (200), isolating the component region (400) from the conductive substrate (100), are formed, a trench (700) is etched in the component region (400) as far as the insulation layer (200), then the trench (700) is etched further as far as the conductive substrate (100), the walls (701) of the trench (700) are formed with an insulation material (710), and an electrical conductor (750, 755, 760) is introduced into the trench (700) and connected conductively to the conductive substrate (100), wherein before the trench (700) is etched, a layer sequence comprising a first oxide layer (510), a polysilicon layer (520) on top of the first oxide layer (510), and a second oxide layer (530) on top of the polysilicon layer (520) is applied to the component region (400).

摘要翻译： 形成半导体阵列的方法，其中，形成将导电基板（100）与元件区域（400）隔离的导电基板（100），部件区域（400）和绝缘层（200） 沟槽（700）在分隔区域（400）中被蚀刻到绝缘层（200），然后将沟槽（700）进一步蚀刻到导电基底（100），沟槽（701）的壁 （700）形成有绝缘材料（710），并且电导体（750,755,760）被引入到沟槽（700）中并且导电地连接到导电衬底（100），其中在沟槽（700）之前， 被蚀刻，包括在第一氧化物层（510）的顶部上的第一氧化物层（510），多晶硅层（520）和在多晶硅层（520）的顶部上的第二氧化物层（530）的层序列是 施加到部件区域（400）。

公开(公告)号：US20070164443A1

公开(公告)日：2007-07-19

申请号：US11528398

申请日：2006-09-28

申请人： Tobias Florian ,  Michael Graf ,  Stefan Schwantes

发明人： Tobias Florian ,  Michael Graf ,  Stefan Schwantes

IPC分类号： H01L23/48

CPC分类号： H01L29/7824 ,  H01L21/743 ,  H01L21/76205 ,  H01L21/76251 ,  H01L21/76286 ,  H01L23/535 ,  H01L27/1203 ,  H01L29/66681 ,  H01L29/78603 ,  H01L29/78639 ,  H01L2924/0002 ,  H01L2924/00

摘要： Semiconductor array, with an element region (400), with a conductive substrate (100), with a buried insulation layer (200), which isolates the element region (400) from the conductive substrate (100), with at least one trench (700), which is filled with an insulation material (710) and which isolates at least one element (1000) in the element region (400) from other elements in the element region (400), with an electrical conductor (750), which is connected conductively to the conductive substrate (100), wherein the electrical conductor (750) is disposed within the trench (700) isolated by the insulation material (710), and wherein the trench (700) is formed within a recess (600) in a surface. Furthermore, a method for manufacturing a semiconductor array is provided.

摘要翻译： 具有导电衬底（100）的元件区（400）的半导体阵列与埋入绝缘层（200）隔离，所述绝缘层将元件区域（400）与导电衬底（100）隔离，至少一个沟槽 700），其填充有绝缘材料（710），并且使元件区域（400）中的至少一个元件（1000）与元件区域（400）中的其它元件与电导体（750）隔离，所述元件区域 导电地连接到导电基板（100），其中电导体（750）设置在由绝缘材料（710）隔离的沟槽（700）内，并且其中沟槽（700）形成在凹部（600）内， 在表面。 此外，提供了一种制造半导体阵列的方法。

公开(公告)号：US07521756B2

公开(公告)日：2009-04-21

申请号：US11636668

申请日：2006-12-11

申请人： Franz Dietz ,  Michael Graf ,  Stefan Schwantes

发明人： Franz Dietz ,  Michael Graf ,  Stefan Schwantes

IPC分类号： H01L29/76

CPC分类号： H01L29/0696 ,  H01L29/0886 ,  H01L29/42368 ,  H01L29/7816 ,  H01L29/7835

摘要： A lateral DMOS transistor is disclosed that includes a first region of a first conductivity type, which is surrounded on the sides by a second region of a second conductivity type, whereby a boundary line between both regions has opposite straight sections and curved sections linking the straight sections, and with a first dielectric structure, which serves as a field region and is embedded in the first region and surrounds a subregion of the first region. Whereby the first distance between the first dielectric structure and the boundary line is greater along the straight sections than along the curved sections.

摘要翻译： 公开了一种横向DMOS晶体管，其包括第一导电类型的第一区域，其在侧面被第二导电类型的第二区域包围，由此两个区域之间的边界线具有相对的直线部分和连接直线的弯曲部分 并且具有用作场区域并被嵌入在第一区域中并且围绕第一区域的子区域的第一电介质结构。 由此，第一电介质结构和边界线之间的第一距离沿着直线部分比沿着弯曲部分更大。

公开(公告)号：US20070262376A1

公开(公告)日：2007-11-15

申请号：US11518449

申请日：2006-09-11

申请人： Volker Dudek ,  Michael Graf ,  Stefan Schwantes

发明人： Volker Dudek ,  Michael Graf ,  Stefan Schwantes

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/0873 ,  H01L21/266 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66681 ,  H01L29/7824

摘要： High-voltage field-effect transistor is provided that includes a drain terminal, a source terminal, a body terminal, and a gate terminal. A gate oxide and a gate electrode, adjacent to the gate oxide, is connected to the gate terminal. A drain semiconductor region of a first conductivity type is connected to the drain terminal. A source semiconductor region of a first conductivity type is connected to the source terminal. A body terminal semiconductor region of a second conductivity type is connected to the body terminal. A body semiconductor region of the second conductivity type, is partially adjacent to the gate oxide to form a channel and is adjacent to the body terminal semiconductor region. A drift semiconductor region of the first conductivity type is adjacent to the drain semiconductor region and the body semiconductor region, wherein in the drift semiconductor region, a potential barrier is formed in a region distanced from the body semiconductor region.

摘要翻译： 提供了高压场效应晶体管，其包括漏极端子，源极端子，主体端子和栅极端子。 与栅极氧化物相邻的栅极氧化物和栅电极连接到栅极端子。 第一导电类型的漏极半导体区域连接到漏极端子。 第一导电类型的源极半导体区域连接到源极端子。 第二导电类型的主体端子半导体区域连接到主体端子。 第二导电类型的体半导体区域部分地与栅极氧化物相邻以形成沟道并且邻近体终端半导体区域。 第一导电类型的漂移半导体区域与漏极半导体区域和体半导体区域相邻，其中在漂移半导体区域中，在远离体半导体区域的区域中形成势垒。

公开(公告)号：US20070235779A1

公开(公告)日：2007-10-11

申请号：US11730514

申请日：2007-04-02

申请人： Franz Dietz ,  Volker Dudek ,  Thomas Hoffmann ,  Michael Graf ,  Stefan Schwantes

发明人： Franz Dietz ,  Volker Dudek ,  Thomas Hoffmann ,  Michael Graf ,  Stefan Schwantes

IPC分类号： H01L29/76 ,  H01L21/8234

CPC分类号： H01L29/66659 ,  H01L29/42368 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7835

摘要： A lateral DMOS-transistor is provided that includes a MOS-diode made of a semi-conductor material of a first type of conductivity, a source-area of a second type of conductivity and a drain-area of a second type of conductivity which is separated from the MOS-diode by a drift region made of a semi-conductor material of a second type of conductivity which is at least partially covered by a dielectric gate layer which also covers the semi-conductor material of the MOS-diode. The dielectric gate-layer comprises a first region of a first thickness and a second region of a second thickness. The first region covers the semi-conductor material of the MOS-diode and the second region is arranged on the drift region. A transition takes place from the first thickness to the second thickness such that an edge area of the drift region which is oriented towards the MOS-diode is arranged below the second area of the gate layer. The invention also relates to a method for the production of these types of DMOS-transistors.

摘要翻译： 提供了一种横向DMOS晶体管，其包括由第一导电类型的半导体材料制成的MOS二极管，第二导电类型的源极区域和第二导电类型的漏极区域，其为 通过由第二导电类型的半导体材料制成的漂移区域与MOS二极管分开，所述漂移区域至少部分被还覆盖MOS二极管的半导体材料的介电栅极层覆盖。 介电栅极层包括第一厚度的第一区域和第二厚度的第二区域。 第一区域覆盖MOS二极管的半导体材料，第二区域布置在漂移区域上。 从第一厚度到第二厚度发生转变，使得朝向MOS二极管定向的漂移区的边缘区域布置在栅极层的第二区域的下方。 本发明还涉及一种用于生产这些类型的DMOS晶体管的方法。

公开(公告)号：US20070221965A1

公开(公告)日：2007-09-27

申请号：US11386316

申请日：2006-03-22

申请人： Gayle Miller ,  Irwin Rathbun ,  Stefan Schwantes ,  Michael Graf ,  Volker Dudek

发明人： Gayle Miller ,  Irwin Rathbun ,  Stefan Schwantes ,  Michael Graf ,  Volker Dudek

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L21/2253 ,  H01L21/26586 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/7835

摘要： A method of fabricating an electronic device and a resulting electronic device. The method includes forming a pad oxide layer on a substrate, forming a silicon nitride layer over the pad oxide layer, and forming a top oxide layer over the silicon nitride layer. A first dopant region is then formed in a first portion of the substrate. A first portion of the top oxide layer is removed; a remaining portion of the top oxide layer is used to align a second dopant mask and a second dopant region is formed. An annealing step drives-in the dopants but oxygen diffusion to the substrate is limited by the silicon nitride layer; the silicon nitride layer thereby assures that the uppermost surface of the silicon is substantially planar in an area proximate to the dopant regions after the annealing step.

摘要翻译： 一种制造电子设备的方法和由此产生的电子设备。 该方法包括在衬底上形成衬垫氧化物层，在衬垫氧化物层上形成氮化硅层，并在氮化硅层上形成顶部氧化物层。 然后在衬底的第一部分中形成第一掺杂区域。 除去顶部氧化物层的第一部分; 使用顶部氧化物层的剩余部分来对准第二掺杂剂掩模，并且形成第二掺杂剂区域。 退火步骤驱动掺杂剂，但是氧化物扩散到衬底受到氮化硅层的限制; 因此，氮化硅层确保在退火步骤之后，在靠近掺杂剂区域的区域中硅的最上表面基本上是平面的。

公开(公告)号：US07560334B2

公开(公告)日：2009-07-14

申请号：US11254580

申请日：2005-10-20

申请人： Stefan Schwantes ,  Volker Dudek ,  Michael Graf ,  Alan Renninger ,  James Shen

发明人： Stefan Schwantes ,  Volker Dudek ,  Michael Graf ,  Alan Renninger ,  James Shen

IPC分类号： H01L21/8242

CPC分类号： H01L27/0805 ,  H01L27/0629 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11531 ,  H01L29/0653 ,  H01L29/66659

摘要： A method and system for fabricating a stacked capacitor and a DMOS transistor are disclosed. In one aspect, the method and system include providing a bottom plate, an insulator, and an additional layer including first and second plates. The insulator covers at least a portion of the bottom plate and resides between the first and second top plates and the bottom plate. The first and second top plates are electrically coupled through the bottom plate. In another aspect, the method and system include forming a gate oxide. The method and system also include providing SV well(s) after the gate oxide is provided. A portion of the SV well(s) resides under a field oxide region of the device. Each SV well includes first, second, and third implants having a sufficient energy to provide the portion of the SV well at a desired depth under the field oxide region without significant additional thermal processing. A gate, source, and drain are also provided.

摘要翻译： 公开了一种用于制造叠层电容器和DMOS晶体管的方法和系统。 一方面，该方法和系统包括提供底板，绝缘体和包括第一和第二板的附加层。 绝缘体覆盖底板的至少一部分并且位于第一和第二顶板与底板之间。 第一和第二顶板通过底板电耦合。 另一方面，该方法和系统包括形成栅极氧化物。 该方法和系统还包括在提供栅极氧化物之后提供SV阱。 SV阱的一部分位于器件的场氧化物区域的下方。 每个SV井包括具有足够能量的第一，第二和第三植入物，以在场氧化物区域下的期望深度处提供SV井的部分，而不需要显着的额外的热处理。 还提供了门，源和漏极。

公开(公告)号：US07402846B2

公开(公告)日：2008-07-22

申请号：US11254387

申请日：2005-10-20

申请人： Stefan Schwantes ,  Michael Graf ,  Volker Dudek ,  Gayle W. Miller, Jr. ,  Irwin Rathbun ,  Peter Grombach ,  Manfred Klaussner

发明人： Stefan Schwantes ,  Michael Graf ,  Volker Dudek ,  Gayle W. Miller, Jr. ,  Irwin Rathbun ,  Peter Grombach ,  Manfred Klaussner

IPC分类号： H01L27/10 ,  H01L29/739 ,  H01L29/73 ,  H01L29/74 ,  H01L23/62 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L27/0266 ,  H01L29/0696 ,  H01L29/1087 ,  H01L29/7835

摘要： An electrostatic discharge (ESD) protection structure is disclosed. The ESD protection structure includes an active device. The active device includes a plurality of drains. Each of the drains has a contact row and at least one body contact row. The at least one body contact row is located on the active device in a manner to reduce the amount of voltage required for triggering the ESD protection structure.

摘要翻译： 公开了一种静电放电（ESD）保护结构。 ESD保护结构包括有源器件。 有源器件包括多个漏极。 每个排水沟具有接触排和至少一个身体接触排。 所述至少一个体接触排以减少触发ESD保护结构所需的电压量的方式位于有源器件上。

公开(公告)号：US20070207589A1

公开(公告)日：2007-09-06

申请号：US11744992

申请日：2007-05-07

申请人： Franz Dietz ,  Volker Dudek ,  Michael Graf ,  Stefan Schwantes ,  Gayle Miller

发明人： Franz Dietz ,  Volker Dudek ,  Michael Graf ,  Stefan Schwantes ,  Gayle Miller

IPC分类号： H01L21/76

CPC分类号： G03F7/70425 ,  G03F7/70633 ,  G03F9/7076

摘要： A first mark, in a double-well integrated circuit technology, is formed by a first etching of a first mask layer on top of an ONO stack. After a first well is doped, a second etching occurs at the first etching sites in the uppermost layer of oxide of the ONO stack forming a first alignment artifact. A second mask layer is applied after removing the first mask layer. A second well doping occurs at second mask layer etching sites to maintain clearance between the two wells within active areas and provide an overlap of the two wells in a frame area. At the first alignment artifact in the overlap of the two wells, further etchings remove remaining layers of the ONO stack and remove silicon from the upper most layer of the semiconductor forming a second registration mark, which may be covered by a protective layer.

摘要翻译： 在双井集成电路技术中的第一标记是通过在ONO堆叠的顶部上的第一掩模层的第一蚀刻形成的。 在第一阱被掺杂之后，在ONO堆叠的最上层的氧化物的第一蚀刻位置处发生第二蚀刻，形成第一对准伪影。 在去除第一掩模层之后施加第二掩模层。 第二阱掺杂发生在第二掩模层蚀刻位置处，以保持有效区域内的两个阱之间的间隙，并且在框架区域中提供两个阱的重叠。 在两个阱的重叠处的第一对准伪影处，进一步蚀刻去除ONO堆叠的剩余层，并从半导体层的最上层去除硅，形成可被保护层覆盖的第二对准标记。

公开(公告)号：US07973333B2

公开(公告)日：2011-07-05

申请号：US11730514

申请日：2007-04-02

申请人： Franz Dietz ,  Volker Dudek ,  Thomas Hoffmann ,  Michael Graf ,  Stefan Schwantes

发明人： Franz Dietz ,  Volker Dudek ,  Thomas Hoffmann ,  Michael Graf ,  Stefan Schwantes

IPC分类号： H01L29/66

CPC分类号： H01L29/66659 ,  H01L29/42368 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7835

摘要： A lateral DMOS-transistor is provided that includes a MOS-diode made of a semi-conductor material of a first type of conductivity, a source-area of a second type of conductivity and a drain-area of a second type of conductivity which is separated from the MOS-diode by a drift region made of a semi-conductor material of a second type of conductivity which is at least partially covered by a dielectric gate layer which also covers the semi-conductor material of the MOS-diode. The dielectric gate-layer comprises a first region of a first thickness and a second region of a second thickness. The first region covers the semi-conductor material of the MOS-diode and the second region is arranged on the drift region. A transition takes place from the first thickness to the second thickness such that an edge area of the drift region which is oriented towards the MOS-diode is arranged below the second area of the gate layer. The invention also relates to a method for the production of these types of DMOS-transistors.

摘要翻译： 提供了一种横向DMOS晶体管，其包括由第一导电类型的半导体材料制成的MOS二极管，第二导电类型的源极区域和第二导电类型的漏极区域，其为 通过由第二导电类型的半导体材料制成的漂移区域与MOS二极管分开，所述漂移区域至少部分被还覆盖MOS二极管的半导体材料的介电栅极层覆盖。 介电栅极层包括第一厚度的第一区域和第二厚度的第二区域。 第一区域覆盖MOS二极管的半导体材料，第二区域布置在漂移区域上。 从第一厚度到第二厚度发生转变，使得朝向MOS二极管定向的漂移区的边缘区域布置在栅极层的第二区域的下方。 本发明还涉及一种用于生产这些类型的DMOS晶体管的方法。