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    Picture coding and decoding apparatus using vector quantization
    1.
    再颁专利
    Picture coding and decoding apparatus using vector quantization 失效
    图像编码和解码装置使用矢量量化

    公开(公告)号：USRE35414E

    公开(公告)日：1996-12-31

    申请号：US818277

    申请日：1992-01-08

    申请人： Tokumichi Murakami ,  Kohtaro Asai ,  Koh Kamizawa ,  Masami Nishida ,  Eizo Yamazaki ,  Atsushi Itoh ,  Naoto Kinjoh

    发明人： Tokumichi Murakami ,  Kohtaro Asai ,  Koh Kamizawa ,  Masami Nishida ,  Eizo Yamazaki ,  Atsushi Itoh ,  Naoto Kinjoh

    IPC分类号： G06T9/00 ,  H04N5/14 ,  H04N7/26 ,  H04N7/28 ,  H04N7/32 ,  H04N7/46 ,  H04N7/12 ,  H04N7/18

    CPC分类号： G06T9/008 ,  H04N19/152 ,  H04N19/577 ,  H04N19/587 ,  H04N19/80 ,  H04N19/94 ,  H04N19/50 ,  H04N5/145

    摘要： An interframe video data coding and decoding apparatus utilizes a differential amplitude suppression circuit in combination with a block encoder and a motion detector to non-linearly suppress amplitude values of interframe differential block data based on a motion detection threshold value determined by an encoding control circuit. The determined threshold value is based on the amount of encoded data being stored in a transmission buffer memory. The suppressed amplitude differential block data is added to corresponding blocks in a frame memory to update the contents of the frame memory during each frame of input video data. In another embodiment, vector quantization encoders are utilized to transmit a motion vector index with encoded frame differential data. In yet another embodiment, a time integral circuit integrates a continuous input video signal series by frame and writes the integrated frame signal into one of two frame memories, while interframe coding is performed on data stored in the other frame memory. Two transmission buffers are provided so that transmission can occur simultaneously with writing of the encoded interframe data into the buffer, by alternating switched connections of the two buffers.

    摘要翻译： 帧间视频数据编码和解码装置利用差分幅度抑制电路与块编码器和运动检测器组合，以基于由编码控制电路确定的运动检测阈值非线性地抑制帧间差分块数据的幅度值。 确定的阈值基于存储在发送缓冲存储器中的编码数据的量。 抑制幅度差分块数据被添加到帧存储器中的相应块，以在每个输入视频数据帧期间更新帧存储器的内容。 在另一实施例中，矢量量化编码器用于传送具有编码帧差分数据的运动矢量索引。 在另一个实施例中，时间积分电路逐帧集成连续输入视频信号，并将集成帧信号写入两个帧存储器之一，同时对存储在另一帧存储器中的数据进行帧间编码。 提供两个传输缓冲器，使得传输可以通过交替的两个缓冲器的交换连接将编码的帧间数据写入缓冲器同时发生。

    Picture coding and decoding apparatus using vector quantization
    2.
    发明授权
    Picture coding and decoding apparatus using vector quantization 失效
    图像编码和解码装置使用矢量量化

    公开(公告)号：US5010401A

    公开(公告)日：1991-04-23

    申请号：US340009

    申请日：1989-04-07

    申请人： Tokumichi Murakami ,  Kohtaro Asai ,  Koh Kamizawa ,  Masami Nishida ,  Eizo Yamazaki ,  Atsushi Itoh ,  Naoto Kinjoh

    发明人： Tokumichi Murakami ,  Kohtaro Asai ,  Koh Kamizawa ,  Masami Nishida ,  Eizo Yamazaki ,  Atsushi Itoh ,  Naoto Kinjoh

    IPC分类号： G06T9/00 ,  H04N7/26 ,  H04N7/28 ,  H04N7/32 ,  H04N7/46

    CPC分类号： G06T9/008 ,  H04N19/152 ,  H04N19/577 ,  H04N19/587 ,  H04N19/80 ,  H04N19/94 ,  H04N19/50

    摘要： An interframe video data coding and decoding apparatus utilizes a differential amplitude suppression circuit in combination with a block encoder and a motion detector to non-linearly suppress amplitude values of interframe differential block data based on a motion detection threshold value determined by an encoding control circuit. The determined threshold value is based on the amount of encoded data being stored in a transmission buffer memory. The suppressed amplitude differential block data is added to corresponding blocks in a frame memory to update the contents of the frame memory during each frame of input video data. In another embodiment, vector quantization encoders are utilized to transmit a motion vector index with encoded frame differential data. In yet another embodiment, a time integral circuit integrates a continuous input video signal series by frame and writes the integrated frame signal into one of two frame memories, while interframe coding is performed on data stored in the other frame memory. Two transmission buffers are provided so that transmission can occur simultaneously with writing of the encoded interframe data into the buffer, by alternating switched connections of the two buffers.

    摘要翻译： PCT No.PCT / JP88 / 00796 Sec。 371日期：1989年4月7日 102（e）日本1989年4月7日PCT PCT日期为1988年8月11日。帧间视频数据编码和解码装置利用差分幅度抑制电路与块编码器和运动检测器组合来非线性地抑制振幅值 基于由编码控制电路确定的运动检测阈值的帧间差分块数据。 确定的阈值基于存储在发送缓冲存储器中的编码数据的量。 抑制幅度差分块数据被添加到帧存储器中的相应块，以在每个输入视频数据帧期间更新帧存储器的内容。 在另一实施例中，矢量量化编码器用于传送具有编码帧差分数据的运动矢量索引。 在另一个实施例中，时间积分电路逐帧集成连续输入视频信号，并将集成帧信号写入两个帧存储器之一，同时对存储在另一帧存储器中的数据进行帧间编码。 提供两个传输缓冲器，使得传输可以通过交替的两个缓冲器的交换连接将编码的帧间数据写入缓冲器同时发生。

    Vector quantizer
    7.
    发明授权
    Vector quantizer 失效
    矢量量化器

    公开(公告)号：US4670851A

    公开(公告)日：1987-06-02

    申请号：US663436

    申请日：1984-10-22

    申请人： Tokumichi Murakami ,  Kohtaro Asai ,  Atsushi Itoh

    发明人： Tokumichi Murakami ,  Kohtaro Asai ,  Atsushi Itoh

    IPC分类号： G06T7/20 ,  G06T9/00 ,  H04N7/32 ,  H04N7/36 ,  G06F15/40 ,  H04N7/12

    CPC分类号： G06T7/2026 ,  G06T9/008 ,  H04N19/152 ,  H04N19/51 ,  G06T2207/10016 ,  H04N19/50

    摘要： A vector quantizer for quantizing the vector of image and audio information, the vector quantizer being capable of efficiently encoding a compensation predictive error signal at a reduced bit rate by performing adaptive vector quantization after judging the significance of the compensation predictive error signal in blocks, and capable of movement compensation inter-frame vector encoding in which variable-length encoding of movement vector is facilitated and information production control is achieved easily.

    摘要翻译： 一种用于量化图像和音频信息的矢量的矢量量化器，所述矢量量化器能够在以块为单位判断补偿预测误差信号的重要性之后通过执行自适应矢量量化而以降低的比特率有效地编码补偿预测误差信号，以及 能够进行运动补偿的帧间矢量编码，其中容易地实现运动矢量的可变长度编码和信息制作控制。

    Digital signal processor system having host processor for writing instructions into internal processor memory
    8.
    发明授权
    Digital signal processor system having host processor for writing instructions into internal processor memory 失效
    数字信号处理器系统具有用于将指令写入内部处理器存储器的主处

    公开(公告)号：US5237667A

    公开(公告)日：1993-08-17

    申请号：US755503

    申请日：1991-08-27

    申请人： Tokumichi Murakami ,  Koh Kamizawa ,  Yoshiaki Katoh ,  Hideo Ohira ,  Masatoshi Kameyama ,  Naoto Kinjo

    发明人： Tokumichi Murakami ,  Koh Kamizawa ,  Yoshiaki Katoh ,  Hideo Ohira ,  Masatoshi Kameyama ,  Naoto Kinjo

    IPC分类号： G06F7/575 ,  G06F9/32 ,  G06F9/355 ,  G06F9/38 ,  G06F13/28 ,  G06F15/78

    CPC分类号： G06F7/575 ,  G06F13/28 ,  G06F15/7832 ,  G06F15/7842 ,  G06F15/786 ,  G06F9/30058 ,  G06F9/30094 ,  G06F9/355 ,  G06F9/3877 ,  G06F9/3885 ,  G06F2207/3884

    摘要： A digital signal processor of a simple circuit configuration capable of implementing arithmetic processes and interruption processes efficiently in a reduced number of steps at a high processing speed. The digital signal processor comprises instruction execution pipeline stages including a stage in which data is read from a data memory and the data is applied to an arithmetic unit; an arithmetic unit for the execution stage, including a barrel shifter, a multiplier and an arithmetic and logic unit, a normalizing barrel shifter, a round-off/accumulation adder, internal data memories and a DMA transfer bus for a write/accumulation stage, an address generating unit capable of parallel and two-dimensional generation of two inputs one output data memory addresses and a DMA control unit for controlling the two-dimensional data transfer through a DMA bus between the internal data memories and an external data memory for an instruction execution stage.

    摘要翻译： 一种简单的电路配置的数字信号处理器，其能够以高处理速度以减少的步数有效地实现算术处理和中断处理。 数字信号处理器包括指令执行流水线级，包括从数据存储器读取数据并将数据应用于运算单元的阶段; 用于执行级的运算单元，包括桶形移位器，乘法器和算术和逻辑单元，归一化桶形移位器，舍入/累积加法器，用于写入/累加级的内部数据存储器和DMA传输总线， 地址产生单元，其能够并行和二维地生成两个输入，一个输出数据存储器地址和用于控制通过内部数据存储器之间的DMA总线和用于指令的外部数据存储器的二维数据传输的DMA控制单元 执行阶段

    Digital signal processor
    10.
    再颁专利
    Digital signal processor 失效
    数字信号处理器

    公开(公告)号：USRE34850E

    公开(公告)日：1995-02-07

    申请号：US803457

    申请日：1991-12-06

    申请人： Tokumichi Murakami ,  Koh Kamizawa ,  Masatoshi Kameyama

    发明人： Tokumichi Murakami ,  Koh Kamizawa ,  Masatoshi Kameyama

    IPC分类号： G06F15/16 ,  G06F9/32 ,  G06F13/28 ,  G06F15/167 ,  G06F15/78 ,  G06F15/80 ,  G06F17/10 ,  G06T1/00 ,  H03H17/02 ,  G06F13/14

    CPC分类号： G06F13/28 ,  G06F15/7857

    摘要： A digital signal processor comprises a bus structure including a program bus, data bus and data input/output bus, a program memory, a program controller, an internal data memory made up of a plurality of 2-port memories for storing block data, an arithmetic operator, a DMA controller for implementing block data input/output between the internal data memory and an external data memory in parallel to an internal operation by the arithmetic operator, an address generator for generating addresses for the internal operation and DMA transfer concurrently and in parallel to the internal operation, and parallel data input/output ports for implementing parallel data communication with an external device independently of input/output operations and in asynchronous fashion. The processor executes an intricate adaptive process algorism such as image signal processing at high speed and at high throughput.

    摘要翻译： 数字信号处理器包括总线结构，包括程序总线，数据总线和数据输入/输出总线，程序存储器，程序控制器，由用于存储块数据的多个2-端口存储器构成的内部数据存储器， 算术运算器，用于在算术运算器的内部操作中并行地实现内部数据存储器和外部数据存储器之间的块数据输入/输出的DMA控制器，用于同时产生用于内部操作和DMA传输的地址的地址生成器 与内部操作并行的并行数据输入/输出端口，用于独立于输入/输出操作和异步方式实现与外部设备的并行数据通信。 处理器执行复杂的自适应处理算法，例如高速和高吞吐量的图像信号处理。