公开(公告)号：US12191202B2

公开(公告)日：2025-01-07

申请号：US17321041

申请日：2021-05-14

Applicant: Tokyo Electron Limited

Inventor： Blaze Messer ,  Andrew Metz

IPC: H01L21/768 ,  H01L21/311 ,  H01L21/67

Abstract: In certain embodiments, a method for processing a semiconductor substrate includes receiving a semiconductor substrate that includes a nitride etch stop layer aligned to a gate electrode and a metal-based etch stop layer aligned to a source/drain contact region. The method further includes selectively etching the metal-based etch stop layer, to remove the metal-based etch stop layer and expose a surface of the source/drain contact region, by exposing the semiconductor substrate to a plasma formed in a gas comprising a corrosive material and fluorocarbon.

公开(公告)号：US11978631B2

公开(公告)日：2024-05-07

申请号：US17116911

申请日：2020-12-09

Applicant: Tokyo Electron Limited

Inventor： Junling Sun ,  Katie Lutker-Lee ,  Angelique Raley ,  Andrew Metz

IPC: H01L21/033 ,  H01L21/02 ,  H01L21/027 ,  H01L21/311 ,  H01L21/66 ,  H01L21/768

CPC classification number: H01L21/0337 ,  H01L21/0338 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76816 ,  H01L22/12 ,  H01L22/20 ,  H01L21/02063 ,  H01L21/0276 ,  H01L21/0279

Abstract: A method for forming a device includes forming a hole pattern in a resist layer disposed over a substrate. The substrate includes contact regions disposed over a major surface of the substrate and a dielectric layer disposed over the contact regions. The resist layer is disposed over the dielectric layer and the hole pattern includes through openings in the resist layer that are aligned with the contact regions. The through openings include a first through opening having a first critical dimension and a second through opening having a second critical dimension greater than the first critical dimension. The method includes modifying the hole pattern by depositing a material including silicon within the through openings by exposing the hole pattern to a first plasma generated from a gas mixture including SiCl4 and hydrogen, and then etching holes in the dielectric layer through the modified hole pattern, exposing the contact regions.

公开(公告)号：US20230343592A1

公开(公告)日：2023-10-26

申请号：US17660111

申请日：2022-04-21

Applicant: Tokyo Electron Limited

Inventor： Shihsheng Chang ,  Andrew Metz ,  Yun Han ,  Ya-Ming Chen ,  Kai-Hung Yu ,  Eric Chih-Fang Liu

IPC: H01L21/033

CPC classification number: H01L21/0332

Abstract: A method of fabricating an amorphous carbon layer (ACL) mask includes forming an ACL on an underlying layer. The ACL includes a soft ACL portion that has a first hardness and a hard ACL portion that has a second hardness. The soft ACL portion underlies the hard ACL portion. The second hardness is greater than the first hardness. The method further includes forming a patterned layer over the ACL and forming an ACL mask by etching through both the soft ACL portion and the hard ACL portion of the ACL to expose the underlying layer using the patterned layer as an etch mask. Forming the ACL may include depositing one or both of the soft ACL portion and the hard ACL portion. Processing conditions may also be varied while forming the ACL to create a hardness gradient that transitions from softer to harder.

公开(公告)号：US20220392765A1

公开(公告)日：2022-12-08

申请号：US17339495

申请日：2021-06-04

Applicant: Tokyo Electron Limited

Inventor： Yun Han ,  Caitlin Philippi ,  Andrew Metz ,  Alok Ranjan

IPC: H01L21/02 ,  C23C16/32 ,  C23C16/42

Abstract: A method for processing a substrate includes performing a cyclic plasma process including a plurality of cycles, each cycle of the plurality of cycles including purging a plasma processing chamber including the substrate with a first deposition gas including carbon. The substrate includes a first layer including silicon and a second layer including a metal oxide. The method further includes exposing the substrate to a first plasma generated from the first deposition gas to selectively deposit a first polymeric film over the first layer relative to the second layer; purging the plasma processing chamber with an etch gas including fluorine; and exposing the substrate to a second plasma generated from the etch gas to etch the second layer.

公开(公告)号：US20220189781A1

公开(公告)日：2022-06-16

申请号：US17514233

申请日：2021-10-29

Applicant: Tokyo Electron Limited

Inventor： Shihsheng Chang ,  David O'Meara ,  Andrew Metz ,  Yun Han

IPC: H01L21/3065 ,  H01J37/305 ,  H01L21/02 ,  H01J37/32 ,  H01L21/033

Abstract: Improved process flows and methods are provided herein for forming a passivation layer on sidewall surfaces of openings formed in an amorphous carbon layer (ACL) to avoid bowing during an ACL etch process. More specifically, improved process flows and methods are provided to form a silicon-containing passivation layer on sidewall surfaces of the openings created within the ACL without utilizing atomic layer deposition (ALD) techniques or converting the silicon-containing passivation layer to an oxide or a nitride. As such, the improved process flows and methods disclosed herein may be used to protect the sidewall surfaces of the ACL and prevent bowing during the ACL etch process, while also reducing processing time and improving throughput.

公开(公告)号：US20150263131A1

公开(公告)日：2015-09-17

申请号：US14203838

申请日：2014-03-11

Applicant: Tokyo Electron Limited

Inventor： Andrew Metz

IPC: H01L29/66 ,  H01L29/40 ,  H01L21/768 ,  H01L29/49

CPC classification number: H01L29/66545 ,  H01L21/76801 ,  H01L21/76897 ,  H01L29/401 ,  H01L29/495 ,  H01L29/4966

Abstract: Techniques disclosed herein provide a gate pitch scaling solution for creating source/drain contacts in a replacement metal gate fabrication scheme. Such techniques provide a self-aligned contact process that protects gate electrodes from shorts due to etching from misaligned patterns. Techniques herein provide a dual layer cap formed by making a semi conformal material deposition over a non-planar topography of RMG formation structures, and using selective etching and planarization to yield a dual layer protective cap that does not excessively increase an aspect ratio.

Abstract translation: 本文公开的技术提供了用于在替换金属栅极制造方案中产生源极/漏极接触的栅极间距缩放解决方案。 这种技术提供了自对准接触工艺，其保护栅电极免受由于未对准图案的蚀刻而引起的短路。 本文的技术提供了通过在RMG形成结构的非平面形貌上进行半适形材料沉积而形成的双层盖，并且使用选择性蚀刻和平坦化来产生不会过度增加纵横比的双层保护帽。

公开(公告)号：US20220375759A1

公开(公告)日：2022-11-24

申请号：US17327305

申请日：2021-05-21

Applicant: Tokyo Electron Limited

Inventor： Yunho Kim ,  Du Zhang ,  Shihsheng Chang ,  Mingmei Wang ,  Andrew Metz

IPC: H01L21/311 ,  H01J37/32

Abstract: A method for processing a substrate includes performing a cyclic process including a plurality of cycles, where the cyclic process includes: forming, in a plasma processing chamber, a passivation layer over sidewalls of a recess in a carbon-containing layer, by exposing the substrate to a first gas including boron, silicon, or aluminum, the carbon-containing layer being disposed over a substrate, purging the plasma processing chamber with a second gas including a hydrogen-containing gas, an oxygen-containing gas, or molecular nitrogen, and exposing the substrate to a plasma generated from the second gas, where each cycle of the plurality of cycles extends the recess vertically into the carbon-containing layer.

公开(公告)号：US20220246747A1

公开(公告)日：2022-08-04

申请号：US17167260

申请日：2021-02-04

Applicant: Tokyo Electron Limited

Inventor： Yun Han ,  Alok Ranjan ,  Shihsheng Chang ,  Andrew Metz ,  Peter Ventzek

IPC: H01L29/66 ,  H01L21/8234 ,  H01L29/78 ,  H01L27/088

Abstract: Improved process flows and methods are provided herein for fabricating a transistor on a substrate. In the disclosed process flows and methods, a contact etch stop layer (CESL) is conformally deposited directly onto a plurality of transistor structures, and a sacrificial layer is conformally deposited directly onto the CESL to protect the CESL from oxidation and thinning during subsequent processing step(s). The sacrificial layer improves the etch stop capability of the CESL during a subsequently performed oxide etch process. By providing a CESL with improved etch stop capability, the disclosed process flows and methods provide a controlled CESL etch process, which reduces or avoids damage to underlying transistor structures.

公开(公告)号：US11195723B1

公开(公告)日：2021-12-07

申请号：US17119019

申请日：2020-12-11

Applicant: Tokyo Electron Limited

Inventor： Shihsheng Chang ,  David O'Meara ,  Andrew Metz ,  Yun Han

IPC: H01L21/3065 ,  H01L21/033 ,  H01J37/305 ,  H01J37/32 ,  H01L21/02

Abstract: Improved process flows and methods are provided herein for forming a passivation layer on sidewall surfaces of openings formed in an amorphous carbon layer (ACL) to avoid bowing during an ACL etch process. More specifically, improved process flows and methods are provided to form a silicon-containing passivation layer on sidewall surfaces of the openings created within the ACL without utilizing atomic layer deposition (ALD) techniques or converting the silicon-containing passivation layer to an oxide or a nitride. As such, the improved process flows and methods disclosed herein may be used to protect the sidewall surfaces of the ACL and prevent bowing during the ACL etch process, while also reducing processing time and improving throughput.

公开(公告)号：US20210343502A1

公开(公告)日：2021-11-04

申请号：US17176342

申请日：2021-02-16

Applicant: Tokyo Electron Limited

Inventor： Junling Sun ,  Andrew Metz ,  Angelique Raley

IPC: H01J37/32 ,  H01L21/311

Abstract: Systems and methods are provided herein for etch features on a substrate, while maintaining a near-unity critical dimension (CD) shrink ratio. The features etched may include, but are not limited to contacts, vias, etc. More specifically, the techniques described herein use a pulsed plasma to control the polymer build-up ratio between the major CD and minor CD of the feature, and thus, control the CD shrink ratio when etching features having substantially different major and minor dimensions. The CD shrink ratio is controlled by selecting or adjusting one or more operational parameters (e.g., duty cycle, RF power, etch chemistry, etc.) of the plasma etch process(es) to control the amount of polymer build-up at the major and minor dimensions of the feature.