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公开(公告)号：US11942307B2
公开(公告)日：2024-03-26
申请号：US17451094
申请日：2021-10-15
发明人： Zhiying Chen , Barton Lane , Yun Han , Peter Lowell George Ventzek , Alok Ranjan
IPC分类号： H01J37/32
CPC分类号： H01J37/32174 , H01J2237/3341
摘要： A method for plasma processing includes: sustaining a plasma in a plasma processing chamber, the plasma processing chamber including a first radio frequency (RF) electrode and a second RF electrode, where sustaining the plasma includes: coupling an RF source signal to the first RF electrode; and coupling a bias signal between the first RF electrode and the second RF electrode, the bias signal having a bipolar DC (B-DC) waveform including a plurality of B-DC pulses, each of the B-DC pulses including: a negative bias duration during which the pulse has negative polarity relative to a reference potential, a positive bias duration during which the pulse has positive polarity relative to the reference potential, and a neutral bias duration during which the pulse has neutral polarity relative to the reference potential.
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公开(公告)号：US20230317462A1
公开(公告)日：2023-10-05
申请号：US17690715
申请日：2022-03-09
发明人： Yun Han , Alok Ranjan , Tomoyuki Oishi , Shuhei Ogawa , Ken Kobayashi , Peter Biolsi
IPC分类号： H01L21/3065 , H01L21/8234
CPC分类号： H01L21/3065 , H01L21/823431
摘要： A method of processing a substrate that includes: performing a cyclic plasma etch process including a plurality of cycles, each of the plurality of cycles including: etching a patterning layer including a polycrystalline semiconductor material to form or extend a recess by exposing the substrate to a first plasma, the substrate including an oxide layer, the patterning layer formed over the oxide layer, exposing the substrate to a second plasma, the second plasma including dihydrogen, and extending the recess by exposing the substrate to a third plasma, the second plasma being different from the first plasma and the third plasma.
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公开(公告)号：US11699741B2
公开(公告)日：2023-07-11
申请号：US17336043
申请日：2021-06-01
IPC分类号： H01L29/66 , H01L21/8234 , H01L29/78 , H01L29/06 , H01L21/311 , H01L21/3213 , H01L21/285 , H01L21/02 , H01L29/786
CPC分类号： H01L29/6656 , H01L21/823431 , H01L21/823468 , H01L29/6653 , H01L29/66545 , H01L29/66553 , H01L29/66742 , H01L29/785 , H01L21/0228 , H01L21/02178 , H01L21/02181 , H01L21/02183 , H01L21/02186 , H01L21/28556 , H01L21/31122 , H01L21/32135 , H01L29/0653 , H01L29/78696
摘要： In an example, a method includes depositing a first sidewall spacer layer over a substrate having a layer stack including alternating layers of a nanosheet and a sacrificial layer, and a dummy gate formed over the layer stack, the first sidewall spacer layer formed over the dummy gate. The method includes depositing a metal-containing liner over the first sidewall spacer layer; forming a first sidewall spacer along the dummy gate by anisotropically etching the metal-containing liner and the first sidewall spacer layer; performing an anisotropic etch back process to form a plurality of vertical recesses in the layer stack; laterally etching the layer stack and form a plurality of lateral recesses between adjacent nanosheets; depositing a second sidewall spacer layer to fill the plurality of lateral recesses; and etching a portion of the second sidewall spacer layer to expose tips of the nanosheet layers.
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公开(公告)号：US20230187214A1
公开(公告)日：2023-06-15
申请号：US17550651
申请日：2021-12-14
IPC分类号： H01L21/3065 , H01J37/32
CPC分类号： H01L21/3065 , H01J37/32146 , H01J37/3244 , H01J37/32522 , H01J2237/334
摘要： A method of etching a substrate that includes: generating a first plasma from a first gas flowing into a first chamber by applying a first power pulse to a first electrode located in the first chamber over a first time duration; and forming a recess in a substrate located in a second chamber, the forming including: providing radicals from the first chamber into the second chamber; applying a plurality of second power pulses to a second electrode located in the second chamber during a second time duration to generate a second plasma in the second chamber from a second gas flowing into the second chamber, the first chamber being pressurized higher than the second chamber; and applying a plurality of third power pulses to a third electrode located in the second chamber during a third time duration to accelerate ions of the second plasma.
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公开(公告)号：US11658037B2
公开(公告)日：2023-05-23
申请号：US15930708
申请日：2020-05-13
发明人： Sonam D. Sherpa , Alok Ranjan
IPC分类号： H01L21/311 , H01J37/32
CPC分类号： H01L21/31116 , H01J37/32009 , H01J2237/3174
摘要： In one exemplary embodiment, described herein is an ALE process for etching an oxide. In one embodiment, the oxide is silicon oxide. The ALE modification step includes the use of a carbon tetrafluoride (CF4) based plasma. This modification step preferentially removes oxygen from the surface of the silicon oxide, providing a silicon rich surface. The ALE removal step includes the use of a hydrogen (H2) based plasma. This removal step removes the silicon enriched monolayer formed in the modification step. The silicon oxide etch ALE process utilizing CF4 and H2 steps may be utilized in a wide range of substrate process steps. For example, the ALE process may be utilized for, but is not limited to, self-aligned contact etch steps, silicon fin reveal steps, oxide mandrel pull steps, oxide spacer trim, and oxide liner etch.
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公开(公告)号：US20230081352A1
公开(公告)日：2023-03-16
申请号：US17991527
申请日：2022-11-21
IPC分类号： H01L21/3065 , H01L21/311 , H01J37/32 , H05H1/46
摘要： A method of plasma processing includes cyclically performing a cycle including the steps of performing a glow phase and performing an afterglow phase. The glow phase includes providing a first SP pulse comprising a first SP power level for a first duration to an SP electrode to generate a capacitively coupled plasma in a plasma processing chamber. The first SP pulse terminates at the end of the glow phase. The afterglow phase is performed after the glow phase and includes providing a BP pulse train to a BP electrode coupled to a target substrate within the plasma processing chamber in an afterglow of the capacitively coupled plasma for a second duration between about 10 μs and about 100 μs. The BP pulse train includes a plurality of BP spikes. Each of the plurality of BP spikes is a DC pulse that has a first BP power level.
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公开(公告)号：US11605542B2
公开(公告)日：2023-03-14
申请号：US17341069
申请日：2021-06-07
发明人： Peter Ventzek , Alok Ranjan
IPC分类号： H01L21/306 , H01L21/02 , H01L21/3065 , H01L21/324 , H01L21/311
摘要： A method for treating a substrate includes receiving the substrate in a vacuum process chamber. The substrate includes a III-V film layer disposed on the substrate. The III-V film layer includes an exposed surface, an interior portion underlying the exposed surface, and one or more of the following: Al, Ga, In, N, P, As, Sb, Si, or Ge. The method further includes altering the chemical composition of the exposed surface and a fraction of the interior portion of the III-V film layer to form an altered portion of the III-V film layer using a first plasma treatment, removing the altered portion of the III-V film layer using a second plasma treatment, and repeating the altering and removing of the III-V film layer until a predetermined amount of the III-V film layer is removed from the substrate.
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公开(公告)号：US20220246747A1
公开(公告)日：2022-08-04
申请号：US17167260
申请日：2021-02-04
发明人： Yun Han , Alok Ranjan , Shihsheng Chang , Andrew Metz , Peter Ventzek
IPC分类号： H01L29/66 , H01L21/8234 , H01L29/78 , H01L27/088
摘要： Improved process flows and methods are provided herein for fabricating a transistor on a substrate. In the disclosed process flows and methods, a contact etch stop layer (CESL) is conformally deposited directly onto a plurality of transistor structures, and a sacrificial layer is conformally deposited directly onto the CESL to protect the CESL from oxidation and thinning during subsequent processing step(s). The sacrificial layer improves the etch stop capability of the CESL during a subsequently performed oxide etch process. By providing a CESL with improved etch stop capability, the disclosed process flows and methods provide a controlled CESL etch process, which reduces or avoids damage to underlying transistor structures.
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公开(公告)号：US20220068607A1
公开(公告)日：2022-03-03
申请号：US17008314
申请日：2020-08-31
发明人： Peter Ventzek , Alok Ranjan
IPC分类号： H01J37/32 , H01L21/3065 , H01L21/67
摘要： A method for processing a substrate includes forming a patterned layer over the substrate, the layer including an opening, where a surface of the opening includes a sidewall and a bottom wall. The method includes processing the patterned layer with an anisotropic process by generating a flux of gas clusters over the substrate in a first process chamber, where the gas clusters include radical precursors; exposing the substrate to the flux of gas clusters. The method includes sustaining plasma including ions in a second process chamber; and exposing the substrate to the ions by directing the ions toward the bottom wall of the opening.
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公开(公告)号：US20220028695A1
公开(公告)日：2022-01-27
申请号：US17483346
申请日：2021-09-23
发明人： Alok Ranjan , Peter Ventzek , Mitsunori Ohata
IPC分类号： H01L21/3065 , H01J37/32 , H01L21/683 , H01L21/67 , H01L21/3213
摘要： A plasma processing apparatus includes a processing chamber, a source power coupling element configured to generate plasma in the processing chamber, and a source power supply node coupled to the source power coupling element and configured to supply radio frequency power to the source power coupling element. The plasma processing apparatus further includes a substrate holder disposed in the processing chamber, a first bias power supply node coupled to the substrate holder and configured to supply first direct current biased power to the substrate holder, and a second bias power supply node coupled to the substrate holder and configured to supply second direct current biased power to the substrate holder. The first direct current biased power includes a first bias power frequency less than about 800 kHz and the second direct current biased power includes a second bias power frequency greater than 800 kHz.
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