公开(公告)号：US20210020435A1

公开(公告)日：2021-01-21

申请号：US16922809

申请日：2020-07-07

Applicant: Tokyo Electron Limited

Inventor： Daniel FULFORD ,  Jodi GRZESKOWIAK ,  Anton J. DEVILLIERS

IPC: H01L21/02 ,  H01L21/311 ,  H01L21/3105

Abstract: The disclosure relates to a method for tuning stress transitions of films on a substrate. The method includes forming a stress-adjustment layer on the substrate, wherein the stress-adjustment layer includes first regions formed of a first material and second regions formed of a second material, wherein the first material includes a first internal stress and the second material includes a second internal stress, and wherein the first internal stress is different compared to the second internal stress; and forming transition regions between the first regions and the second regions, wherein the transition regions include an interface between the first material and the second material that has a predetermined slope that is greater than zero degrees and less than 90 degrees.

公开(公告)号：US20230367217A1

公开(公告)日：2023-11-16

申请号：US18354388

申请日：2023-07-18

Applicant: Tokyo Electron Limited

Inventor： Jodi GRZESKOWIAK ,  Anthony SCHEPIS ,  Anton DEVILLIERS

IPC: G03F7/09 ,  H01L21/027 ,  H01L21/3065 ,  H01L21/308 ,  G03F7/004 ,  G03F7/11

CPC classification number: G03F7/094 ,  H01L21/0276 ,  H01L21/3065 ,  H01L21/3085 ,  G03F7/0045 ,  H01L21/3088 ,  G03F7/11 ,  G03F7/091 ,  H01L21/3086

Abstract: A method for patterning a substrate in which a patterned photoresist structure can be formed on the substrate, the patterned photoresist structure having a sidewall. A conformal layer of spacer material can be deposited on the sidewall. The patterned photoresist structure can then be removed from the substrate, leaving behind the spacer material. Then, the substrate can be directionally etched using the sidewall spacer as an etch mask to form the substrate having a target critical dimension.

公开(公告)号：US20230352343A1

公开(公告)日：2023-11-02

申请号：US18308230

申请日：2023-04-27

Applicant: Tokyo Electron Limited

Inventor： Jeffrey SMITH ,  David POWER ,  Eric Chih-Fang LIU ,  Anton J. DEVILLIERS ,  Kandabara TAPILY ,  Jodi GRZESKOWIAK ,  David CONKLIN ,  Michael MURPHY

IPC: H01L21/768 ,  H01L21/311 ,  H01L21/033 ,  H01L23/522

CPC classification number: H01L21/76897 ,  H01L21/76816 ,  H01L21/31144 ,  H01L21/0337 ,  H01L21/76811 ,  H01L23/5226

Abstract: A process includes forming, over a dielectric layer, a hardmask stack including a first layer below a second layer below a third layer below a fourth layer. The first and third layers include a different hardmask material from the second and fourth layers. A trench pattern including sidewall spacer structures is formed over the hardmask stack. The fourth layer is etched in a first region. The fourth and third layers are etched in a second region. The fourth and third layers are etched in a third region. The fourth layer is etched in a fourth region. The second and first layers are etched in the second and third regions. The third layer is etched in the first and fourth regions. In the dielectric layer, trenches are formed in the first and fourth regions, and via openings, deeper than the trenches, are formed in the second and third regions.

公开(公告)号：US20210082750A1

公开(公告)日：2021-03-18

申请号：US17021586

申请日：2020-09-15

Applicant: Tokyo Electron Limited

Inventor： Kai-Hung YU ,  Jodi GRZESKOWIAK ,  Nicholas JOY ,  Jeffrey SMITH

IPC: H01L21/768

Abstract: A method of metallization includes receiving a substrate having a recess formed therein. The recess has a bottom and sidewalls, and a conformal liner is deposited on the bottom and sidewalls of the recess. The conformal liner is removed from an upper portion of the recess to expose upper sidewalls of the recess while leaving the conformal liner in a lower portion of the recess covering the bottom and lower sidewalls of the recess. Metal is deposited in a lower portion of the recess to form a metallization feature including the conformal liner in the lower portion of the recess and the metal.

公开(公告)号：US20200152472A1

公开(公告)日：2020-05-14

申请号：US16674790

申请日：2019-11-05

Applicant: Tokyo Electron Limited

Inventor： Anton DEVILLIERS ,  Robert BRANDT ,  Jeffrey SMITH ,  Jodi GRZESKOWIAK ,  Daniel FULFORD

IPC: H01L21/3105 ,  H01L21/027 ,  G03F7/004 ,  G03F7/09 ,  G03F7/38 ,  G03F7/16 ,  G03F7/32 ,  G03F7/20

Abstract: Techniques herein include methods for planarizing films including films used in the fabrication of semiconductor devices. Such fabrication can generate structures on a surface of a substrate, and these structures can have a spatially variable density across the surface. Planarization methods herein include depositing a first acid-labile film overtop the structures and the substrate, the first acid-labile film filling between the structures. A second acid-labile film is deposited overtop the first acid-labile film. An acid source film is deposited overtop the second acid-labile film, the acid source film including an acid generator configured to generate an acid in response to receiving radiation having a predetermined wavelength of light. A pattern of radiation is projected over the acid source film, the pattern of radiation having a spatially variable intensity at predetermined areas of the pattern of radiation.

公开(公告)号：US20210088904A1

公开(公告)日：2021-03-25

申请号：US17023470

申请日：2020-09-17

Applicant: Tokyo Electron Limited

Inventor： Anton J. DEVILLIERS ,  Jodi GRZESKOWIAK ,  Daniel FULFORD ,  Richard A. FARRELL ,  Jeffrey SMITH

IPC: G03F7/039 ,  H01L21/027 ,  G03F7/16 ,  G03F7/30 ,  G03F7/20

Abstract: A method of forming a pattern on a substrate is provided. The method includes forming a first layer on an underlying layer of the substrate, where the first layer is patterned to have a first structure. The method also includes depositing a grafting material on side surfaces of the first structure, where the grafting material includes a solubility-shifting material. The method further includes diffusing the solubility-shifting material by a predetermined distance into a neighboring structure that abuts the solubility-shifting material, where the solubility-shifting material changes solubility of the neighboring structure in a developer, and removing soluble portions of the neighboring structure using the developer to form a second structure.

公开(公告)号：US20210020453A1

公开(公告)日：2021-01-21

申请号：US16784619

申请日：2020-02-07

Applicant: Tokyo Electron Limited

Inventor： Daniel FULFORD ,  Jodi GRZESKOWIAK ,  Anton J. DEVILLIERS

IPC: H01L21/321 ,  H01L21/768

Abstract: The disclosure relates to techniques and methods for planarizing a substrate by amplifying and controlling z-height technology. Variability of z-height can be modeled or measured for each device. A counter height pattern can then be created and processed on a substrate. By using different materials with different etch rates, a planarizing pattern can be transferred to the substrate or system to create a planarized substrate surface for improved lithography. Additionally, a transition region slope can be precisely controlled using the same methods.

公开(公告)号：US20200152448A1

公开(公告)日：2020-05-14

申请号：US16679594

申请日：2019-11-11

Applicant: Tokyo Electron Limited

Inventor： Jodi GRZESKOWIAK ,  Anton J. Devilliers ,  Daniel Fulford

IPC: H01L21/02 ,  C09D179/08 ,  G03F7/30 ,  G03F7/20 ,  H01L21/768

Abstract: Techniques herein include methods of forming conformal films on substrates including semiconductor wafers. Conventional film forming techniques can be slow and expensive. Methods herein include depositing a self-assembled monolayer (SAM) film over the substrate. The SAM film can include an acid generator configured to generate acid in response to a predetermined stimulus. A polymer film is deposited over the SAM film. The polymer film is soluble to a predetermined developer and configured to change solubility in response to exposure to the acid. The acid generator is stimulated and generates acid. The acid is diffused into the polymer film. The polymer film is developed with the predetermined developer to remove portions of the polymer film that are not protected from the predetermined developer. These process steps can be repeated a desired number of times to grow an aggregate film layer by layer.

公开(公告)号：US20230274940A1

公开(公告)日：2023-08-31

申请号：US18312650

申请日：2023-05-05

Applicant: Tokyo Electron Limited

Inventor： Michael MURPHY ,  Jodi GRZESKOWIAK ,  Anton J. DEVILLIERS

IPC: H01L21/308 ,  H01L21/027 ,  H01L21/033 ,  G03F7/00 ,  G03F7/11

CPC classification number: H01L21/3086 ,  H01L21/0274 ,  H01L21/0337 ,  H01L21/0338 ,  G03F7/0035 ,  G03F7/11

Abstract: In method of patterning a substrate, a first relief pattern is formed based on a first layer deposited over a substrate. Openings in the first relief pattern are filled with a reversal material. The first relief pattern is then removed from the substrate and the reversal material remains on the substrate to define a second relief pattern. A fill material is deposited over the substrate that is in contact with the second relief pattern, and sensitive to a photo-acid generated from a photo-acid generator in the second relief pattern. Selected portions of the second relief pattern are exposed to a first actinic radiation to generate the photo-acid in the selected portions of the second relief pattern. The photo-acid are driven from the selected portions of the second relief pattern into portions of the fill material so that the portions of the fill material to become soluble to a predetermined developer.

公开(公告)号：US20210098294A1

公开(公告)日：2021-04-01

申请号：US17034930

申请日：2020-09-28

Applicant: Tokyo Electron Limited

Inventor： Jeffrey SMITH ,  Lars LIEBMANN ,  Daniel CHANEMOUGAME ,  Hiroki NIIMI ,  Kandabara TAPILY ,  Subhadeep KAL ,  Jodi GRZESKOWIAK ,  Anton DEVILLIERS

IPC: H01L21/768 ,  H01L21/28 ,  H01L21/3205 ,  H01L21/8234 ,  H01L29/66

Abstract: A method of fabricating a semiconductor device is provided. The method includes forming BPR structures filled with a replacement BPR material, first S/D structures, first replacement silicide layers, and a pre-metallization dielectric that covers the first replacement silicide layers and the first S/D structures. The method also includes forming first interconnect openings in the pre-metallization dielectric and first replacement interconnect layers in the first interconnect openings. The first replacement interconnect layers are connected to the first replacement silicide layers. A thermal process is executed. The method further includes replacing, from a first side of the first wafer, a first group of the first replacement interconnect layers, a first group of the first replacement silicide layers, and the replacement BPR material, and replacing, from a second side of the first wafer, a second group of the first replacement interconnect layers, and a second group of the first replacement silicide layers.