公开(公告)号：US11756790B2

公开(公告)日：2023-09-12

申请号：US17196385

申请日：2021-03-09

Applicant: Tokyo Electron Limited

Inventor： Yen-Tien Lu ,  Xinghua Sun ,  Shihsheng Chang ,  Eric Chih-Fang Liu ,  Angelique Raley ,  Katie Lutker-Lee

IPC: H01L21/033 ,  H01L21/3065 ,  H01L21/308

CPC classification number: H01L21/0332 ,  H01L21/3065 ,  H01L21/3081

Abstract: A method is described for patterning a dielectric layer disposed over a semiconductor substrate layer. The patterning process includes forming a patterned hard mask layer over the dielectric layer, the patterned hard mask layer exposing a portion of a major surface of the dielectric layer. A portion of the dielectric layer is removed by a cyclic etch process, where performing one cycle of the cyclic etch process comprises forming a capping layer selectively over the patterned hard mask layer and performing a timed etch process that removes material from the dielectric layer. In another method, the deposition over the hard mask and the removal of the portion of the dielectric layer are performed concurrently.

公开(公告)号：US20210265205A1

公开(公告)日：2021-08-26

申请号：US17179117

申请日：2021-02-18

Applicant: Tokyo Electron Limited

Inventor： Yen-Tien Lu ,  Xinghua Sun ,  Michael Edley ,  Angelique Raley

IPC: H01L21/768

Abstract: Stacked structures, process steps, and methods for via and trench formation use a dielectric etch stop layer (ESL) to reduce or eliminate problems, such as process lag and chamfer erosion, that occur during conventional etch processes. A stacked structure is formed that includes a dielectric ESL within a dielectric layer, such as a low-dielectric (low-K) layer, to form a first low-K layer below the dielectric ESL and a second low-K dielectric layer above the dielectric ESL. When the stacked structure is subsequently etched to form trenches as well as vias through the stacked structure to underlying layers, the dielectric ESL reduces or eliminates RIE lag by ensuring that trenches (regardless of width) stop on the dielectric ESL. The dielectric ESL also acts as a protective layer to protect corners from chamfer erosion during via and trench etch processes.

公开(公告)号：US10964587B2

公开(公告)日：2021-03-30

申请号：US16415687

申请日：2019-05-17

Applicant: Tokyo Electron Limited

Inventor： Yen-Tien Lu ,  David O'Meara ,  Angelique Raley ,  Xinghua Sun

IPC: H01L21/768 ,  H01L21/762 ,  H01L21/308

Abstract: An atomic layer deposition (ALD) technique is used to deposit one or more layers on hard mask layers and the sidewalls of low-K dielectric trench as part of the trench etch process. The ALD layer(s) can prevent the hard mask from being eroded during various hard mask open processes. Further, the ALD layer(s) may be utilized to prevent the low-K dielectric sidewall from being laterally etched during the low-K dielectric trench etch. Hence, better control of the trench profile and better critical dimension control may be provided.

公开(公告)号：US20240371655A1

公开(公告)日：2024-11-07

申请号：US18312427

申请日：2023-05-04

Applicant: Tokyo Electron Limited

Inventor： Yen-Tien Lu ,  Shihsheng Chang ,  Nicholas Joy

IPC: H01L21/3213 ,  H01L21/02 ,  H01L21/033 ,  H01L21/56

Abstract: A method of processing a substrate that includes: forming a patterned hardmask layer over a conductive layer to be etched, the conductive layer disposed over a substrate; and patterning the conductive layer using the patterned hardmask layer as an etch mask, by performing a cyclic plasma etch process to gradually form a recess in the conductive layer, each cycle of the cyclic plasma etch process including exposing the substrate to a first plasma including a halogen to etch the conductive layer, and exposing the substrate to a second plasma including a silicon-containing precursor to deposit a silicon-containing protective layer over a top surface of the patterned hardmask layer.

公开(公告)号：US11688604B2

公开(公告)日：2023-06-27

申请号：US16582297

申请日：2019-09-25

Applicant: Tokyo Electron Limited

Inventor： Yen-Tien Lu ,  Kai-Hung Yu ,  Angelique Raley

IPC: H01L21/033 ,  H01L21/311 ,  H01L21/768 ,  H01L21/3213

CPC classification number: H01L21/0337 ,  H01L21/0332 ,  H01L21/31144 ,  H01L21/32136 ,  H01L21/76802

Abstract: A method of processing substrates, in one example microelectronic workpieces, is disclosed that includes forming a multi-layer metal hard mask (MHM) layer in which at least one lower layer of the multi-layer MHM is comprised of ruthenium (Ru). The Ru MHM layer may be an atomic layer deposition (ALD) Ru MHM layer formed over one or more underlying layers on a substrate. The ALD Ru MHM layer may be etched to provide a patterned ALD Ru MHM layer, and then the one or more underlying layers may be etched using, at least in part, the patterned ALD Ru MHM layer as a mask to protect portion of the one or more underlying layers. In one embodiment, at least one of the underlying layers is a hard mask layer.

公开(公告)号：US11164781B2

公开(公告)日：2021-11-02

申请号：US16508923

申请日：2019-07-11

Applicant: Tokyo Electron Limited

Inventor： Xinghua Sun ,  Yen-Tien Lu ,  Angelique Raley ,  David O'Meara ,  Jeffrey Smith

IPC: H01L21/768 ,  H01L21/02

Abstract: Methods are disclosed that provide improved via profile control by forming atomic layer deposition (ALD) liners to protect side walls of vias during subsequent etch processes. ALD liners can be used for BEOL etch processes as well as for full self-aligned via (FSAV) processes and/or other processes. For one embodiment, ALD liners are used as protection or sacrificial layers for vias to reduce damage during multilayer via or trench etch processes. The ALD liners can also be deposited at different points within process flows, for example, before or after removal of organic planarization layers. The use of ALD liners facilitates shrinking of via critical dimensions (CDs) while still controlling via profiles for various process applications including dual Damascene processes and FSAV processes. In addition, the use of ALD liners improves overall CD control for via or hole formation as well as device yield and reliability.

公开(公告)号：US20210028017A1

公开(公告)日：2021-01-28

申请号：US16582297

申请日：2019-09-25

Applicant: Tokyo Electron Limited

Inventor： Yen-Tien Lu ,  Kai-Hung Yu ,  Angelique Raley

IPC: H01L21/033 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/311

Abstract: A method of processing substrates, in one example microelectronic workpieces, is disclosed that includes forming a multi-layer metal hard mask (MHM) layer in which at least one lower layer of the multi-layer MHM is comprised of ruthenium (Ru). The Ru MHM layer may be an atomic layer deposition (ALD) Ru MHM layer formed over one or more underlying layers on a substrate. The ALD Ru MHM layer may be etched to provide a patterned ALD Ru MHM layer, and then the one or more underlying layers may be etched using, at least in part, the patterned ALD Ru MHM layer as a mask to protect portion of the one or more underlying layers. In one embodiment, at least one of the underlying layers is a hard mask layer.

公开(公告)号：US11742241B2

公开(公告)日：2023-08-29

申请号：US17487987

申请日：2021-09-28

Applicant: TOKYO ELECTRON LIMITED

Inventor： Xinghua Sun ,  Yen-Tien Lu ,  Angelique Raley ,  David O'Meara ,  Jeffrey Smith

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/311 ,  H01L21/027 ,  H01L21/3205

CPC classification number: H01L21/76897 ,  H01L21/0228 ,  H01L21/0274 ,  H01L21/31116 ,  H01L21/32056 ,  H01L21/76807 ,  H01L21/76811 ,  H01L21/76814 ,  H01L21/76816 ,  H01L21/76831

Abstract: Methods are disclosed that provide improved via profile control by forming atomic layer deposition (ALD) liners to protect side walls of vias during subsequent etch processes. ALD liners can be used for BEOL etch processes as well as for full self-aligned via (FSAV) processes and/or other processes. For one embodiment, ALD liners are used as protection or sacrificial layers for vias to reduce damage during multilayer via or trench etch processes. The ALD liners can also be deposited at different points within process flows, for example, before or after removal of organic planarization layers. The use of ALD liners facilitates shrinking of via critical dimensions (CDs) while still controlling via profiles for various process applications including dual Damascene processes and FSAV processes. In addition, the use of ALD liners improves overall CD control for via or hole formation as well as device yield and reliability.

公开(公告)号：US11721578B2

公开(公告)日：2023-08-08

申请号：US17088136

申请日：2020-11-03

Applicant: Tokyo Electron Limited ,  International Business Machines Corporation

Inventor： Yen-Tien Lu ,  Angelique Raley ,  Joe Lee

IPC: H01L21/768 ,  H01L21/027

CPC classification number: H01L21/76814 ,  H01L21/0273 ,  H01L21/76816 ,  H01L21/76835

Abstract: Split ash processes are disclosed to suppress damage to low-dielectric-constant (low-K) layers during via formation. For one embodiment, ash processes used to remove an organic layer, such as an organic planarization layer (OPL), associated with via formation are split into multiple ash process steps that are separated by intervening process steps. A first ash process is performed to remove a portion of an organic layer after vias have been partially opened to a low-K layer. Subsequently, after the vias are fully opened through the low-K layer, an additional ash process is performed to remove the remaining organic material. Although some damage may still occur on via sidewalls due to this split ash processing, the damage is significantly reduced as compared to prior solutions, and device performance is improved. Target critical dimension (CD) for vias and effective dielectric constants for the low-K layer are achieved.

公开(公告)号：US10950444B2

公开(公告)日：2021-03-16

申请号：US16252949

申请日：2019-01-21

Applicant: Tokyo Electron Limited

Inventor： Yen-Tien Lu ,  Kai-Hung Yu ,  Andrew Metz

IPC: H01L21/00 ,  H01L21/033 ,  H01L21/768 ,  H01L21/311

Abstract: Embodiments are disclosed for a method to process microelectronic workpieces including forming a metal hard mask layer including ruthenium (Ru MHM layer) over one or more underlying layers on a substrate for a microelectronic workpiece, etching the Ru MHM layer to provide a patterned Ru MHM layer, and etching the one or more underlying layers using the patterned Ru MHM layer as a mask to protect portion of the one or more underlying layers. For one embodiment, the Ru MHM layer is a material including 95 percent or more of ruthenium (Ru). For another embodiment, the Ru MHM layer is a material including 70 percent or more of ruthenium (Ru). Further, the Ru MHM layer preferably has a selectivity of 10 or greater with respect to a next underlying layer adjacent to the Ru MHM layer, such as a SiN hard mask layer.