公开(公告)号：US5426390A

公开(公告)日：1995-06-20

申请号：US323570

申请日：1994-10-17

申请人： Tomoaki Yabe ,  Masataka Matsui ,  Kouichi Satou

发明人： Tomoaki Yabe ,  Masataka Matsui ,  Kouichi Satou

IPC分类号： H03K5/1532 ,  H03K5/00 ,  H03K3/86

CPC分类号： H03K5/1532

摘要： In input transition detection pulse generators used in semiconductor memory devices, etc., in order to permit a designer to arbitrarily design the power supply voltage dependency of an output pulse width in accordance with use, a scheme is employed such that the functional block for detecting transition of an input or inputs to generate a pulse signal or signals, or the functional block for setting the width of each pulse signal is caused to have a function to generate pulse signals having different power supply voltage dependencies of pulse widths to perform a predetermined logical operation by a logical operation unit on the basis of pulse signals from the input transition detection pulse generation block or the pulse width setting block, thus to output a pulse having a pulse width optimum for a power supply voltage used. In place of the logical operation unit, an approach may be employed to select any one of a plurality of units as the input transition detection pulse generation block or the pulse width setting block by using a control signal to output a pulse having any pulse width. Further, the input transition pulse generation block or the pulse width setting block may be constructed to set at least one pulse width of pulses generated therefrom on the basis of a delay time generated by using an RC delay line.

摘要翻译： 在用于半导体存储器件等的输入转换检测脉冲发生器中，为了允许设计者根据使用任意地设计输出脉冲宽度的电源电压依赖性，采用一种方案，使得用于检测的功能块 导致用于产生脉冲信号或信号的输入或输入的转换或用于设置每个脉冲信号的宽度的功能块被用于产生具有不同的脉冲宽度的电源电压依赖性的脉冲信号，以执行预定的逻辑 基于来自输入转移检测脉冲发生块或脉冲宽度设定块的脉冲信号，通过逻辑运算部进行运算，从而输出对所使用的电源电压具有最佳的脉冲宽度的脉冲。 代替逻辑运算单元，通过使用控制信号输出具有任何脉冲宽度的脉冲，可以采用多种单元中的任意一个来选择输入转移检测脉冲生成块或脉冲宽度设定块的方法。 此外，输入转移脉冲产生块或脉冲宽度设置块可以被构造为基于通过使用RC延迟线产生的延迟时间来设置从其产生的脉冲的至少一个脉冲宽度。

公开(公告)号：US07613032B2

公开(公告)日：2009-11-03

申请号：US12027548

申请日：2008-02-07

申请人： Tomoaki Yabe

发明人： Tomoaki Yabe

IPC分类号： G11C11/00

CPC分类号： G11C7/02 ,  G11C11/406 ,  G11C11/412

摘要： A semiconductor memory device includes a plurality of memory cells each including a first inverter and a second inverter, a first storage node connected to an output terminal of the first inverter and an input terminal of the second inverter, and a second storage node connected to an input terminal of the first inverter and an output terminal of the second inverter, a word line connected to the memory cells, and a plurality of bit lines connected to the memory cells, respectively. Input data is written to a selected memory cell, and data read from a non-selected memory cell is written again to the non-selected memory cell in write operation.

摘要翻译： 半导体存储器件包括多个存储单元，每个存储单元包括第一反相器和第二反相器，连接到第一反相器的输出端的第一存储节点和第二反相器的输入端，以及连接到第一反相器的第二存储节点 第一反相器的输入端子和第二反相器的输出端子，连接到存储单元的字线和分别连接到存储单元的多个位线。 输入数据被写入所选择的存储单元，并且在写入操作中从未选择的存储单元读取的数据被再次写入未选择的存储单元。

公开(公告)号：US20090213635A1

公开(公告)日：2009-08-27

申请号：US12430253

申请日：2009-04-27

申请人： Akihito Tohata ,  Tomoaki Yabe

发明人： Akihito Tohata ,  Tomoaki Yabe

IPC分类号： G11C5/06 ,  G11C7/06

CPC分类号： G11C7/14 ,  G11C7/22 ,  G11C7/227 ,  G11C11/413

摘要： A semiconductor memory device includes first and second cell arrays which have memory cells arrayed in row and column directions, first and second bit lines which are connected to the memory cells arrayed in the column direction, and first and second sense amplifiers which are connected to the first, second bit lines, respectively. The device also includes first and second dummy cell arrays which have dummy cells arrayed in the row and column directions, a dummy word line which is connected to the dummy cells arrayed in the row direction, first and second dummy bit lines which are connected to the dummy cells arrayed in the column direction and receive an output from the dummy word line, and first and second sense amplifier activation circuits which activate the first, second sense amplifiers in accordance with first and second control signals output from the first and second dummy bit lines, respectively.

摘要翻译： 一种半导体存储器件包括第一和第二单元阵列，其具有排列在行和列方向上的存储单元，连接到沿列方向排列的存储单元的第一和第二位线以及连接到列方向的第一和第二读出放大器 第一位，第二位线。 该装置还包括第一和第二虚拟单元阵列，其具有排列在行和列方向上的虚设单元，连接到沿行方向排列的虚拟单元的虚拟字线，连接到行方向的第一和第二虚拟位线 虚拟单元，沿列方向排列并接收来自虚拟字线的输出，以及第一和第二读出放大器激活电路，其根据从第一和第二虚拟位线输出的第一和第二控制信号激活第一，第二读出放大器 ， 分别。

公开(公告)号：US20070127286A1

公开(公告)日：2007-06-07

申请号：US11538983

申请日：2006-10-05

申请人： Tomoaki Yabe

发明人： Tomoaki Yabe

IPC分类号： G11C11/00

CPC分类号： G11C11/412

摘要： A semiconductor memory device includes a plurality of word lines, first and second bit lines, a plurality of memory cells which are connected to the first and second bit lines, a differential amplifier which is connected to one end of the first bit line and one end of the second bit line, a reference-current generating circuit which is connected to the other end of the second bit line and which generates a reference-current smaller than the cell current of the memory cells, and a dummy word line which is connected to the reference-current generating circuit, to activate the reference-current generating circuit in order to read data.

摘要翻译： 半导体存储器件包括多个字线，第一和第二位线，连接到第一和第二位线的多个存储器单元，连接到第一位线的一端和一端的差分放大器 第二位线的基准电流产生电路，连接到第二位线的另一端并产生小于存储单元的单元电流的参考电流;以及虚拟字线，其连接到 参考电流产生电路，以激活参考电流产生电路以便读取数据。

公开(公告)号：US20050232058A1

公开(公告)日：2005-10-20

申请号：US10918642

申请日：2004-08-16

申请人： Tomoaki Yabe

发明人： Tomoaki Yabe

IPC分类号： G11C11/41 ,  G11C11/00 ,  G11C11/412

CPC分类号： G11C11/412 ,  Y10S257/903 ,  Y10S257/904

摘要： A semiconductor integrated circuit device is configured by eight transistors including the six transistors configuring the data holding section and the two NMOS transistors configuring the reading stage. The threshold voltage of the NMOS transistors configuring the reading stage is set low and the threshold voltage of the six transistors configuring the data holding section is set higher than the threshold voltage of the NMOS transistors configuring the reading stage. The cell current flowing from the bit line to the ground terminal can be set large and the large static noise margin (SNM) can be attained.

摘要翻译： 半导体集成电路器件由包括配置数据保持部分的六个晶体管和配置读取级的两个NMOS晶体管的八个晶体管构成。 配置读取级的NMOS晶体管的阈值电压被设置为低，并且将构成数据保持部分的六个晶体管的阈值电压设置为高于构成读取级的NMOS晶体管的阈值电压。 可以将从位线流到接地端子的电池电流设定得较大，可以获得大的静态噪声容限（SNM）。

公开(公告)号：US6002631A

公开(公告)日：1999-12-14

申请号：US982534

申请日：1997-12-02

申请人： Ryo Haga ,  Tomoaki Yabe ,  Shinji Miyano

发明人： Ryo Haga ,  Tomoaki Yabe ,  Shinji Miyano

IPC分类号： G11C11/409 ,  G11C7/10 ,  G11C8/12 ,  G11C11/401 ,  G11C11/407 ,  G11C11/408 ,  G11C8/00

CPC分类号： G11C7/1018 ,  G11C7/1045 ,  G11C8/12

摘要： Even-numbered columns are arranged in the first memory cell array (bank), and odd-numbered columns are arranged in the second memory cell array (bank). A column address signal is input to an adder through a buffer. When data is read out of two or more columns, the adder generates a column address signal whose address value is more than that of the column address signal by one. The adder supplies a first column decoder with a column address signal for addressing an even-numbered column and supplies a second column decoder with a column address signal for addressing an odd-numbered column. Since the even-numbered columns and odd-numbered columns are arranged in their separate memory cell arrays, data read out of continuous two or more columns do not collide with each other.

摘要翻译： 偶数列布置在第一存储单元阵列（bank）中，奇数列排列在第二存储单元阵列（bank）中。 列地址信号通过缓冲器输入到加法器。 当从两个或多个列读出数据时，加法器产生地址值大于列地址信号的列地址信号。 加法器为第一列解码器提供列地址信号，用于寻址偶数列，并向第二列解码器提供用于寻址奇数列的列地址信号。 由于偶数列和奇数列排列在其分开的存储单元阵列中，所以从连续的两个或更多个列读出的数据不会彼此冲突。

公开(公告)号：US06429521B1

公开(公告)日：2002-08-06

申请号：US09531177

申请日：2000-03-21

申请人： Osamu Wada ,  Ryo Haga ,  Tomoaki Yabe ,  Shinji Miyano

发明人： Osamu Wada ,  Ryo Haga ,  Tomoaki Yabe ,  Shinji Miyano

IPC分类号： H01L2348

CPC分类号： H01L23/528 ,  H01L27/118 ,  H01L2924/0002 ,  Y10S257/903 ,  H01L2924/00

摘要： On a semiconductor substrate, there are formed a first macro cell having wiring layers of three layers each formed of a metal wiring layer (for example, an aluminum wiring) and a second macro cell having wiring layers of three layers each formed of a metal wiring layer similar to the first macro cell. The first macro cell is formed to have a wiring structure of three wiring layers though the originally necessary number of metal wiring layers is two. The metal wiring layer of each layer on the first macro cell is formed of the same material as the metal wiring layer of the corresponding each layer on the second macro cell. Moreover, the metal wiring layer of each layer is formed to have the same film thickness. In order to connect the first and second macro cells to each other, a macro interconnection wiring is formed to be included in the third wiring layer (uppermost wiring layer).

摘要翻译： 在半导体基板上，形成有由金属布线层（例如铝布线）形成的具有三层布线层的第一宏观单元和具有由金属布线形成的三层布线层的第二宏观单元 层与第一个宏单元类似。 第一宏单元形成为具有三个布线层的布线结构，尽管最初所需数量的金属布线层是两个。 第一宏单元上的各层的金属布线层由与第二宏单元上的各层的金属布线层相同的材料形成。 此外，各层的金属布线层形成为具有相同的膜厚度。 为了将第一和第二宏单元彼此连接，形成宏布线布置在第三布线层（最上布线层）中。

公开(公告)号：US5754481A

公开(公告)日：1998-05-19

申请号：US857559

申请日：1997-05-16

申请人： Tomoaki Yabe ,  Kenji Numata ,  Katsuhiko Sato ,  Ryo Haga ,  Shinji Miyano ,  Tohru Furuyama

发明人： Tomoaki Yabe ,  Kenji Numata ,  Katsuhiko Sato ,  Ryo Haga ,  Shinji Miyano ,  Tohru Furuyama

IPC分类号： G11C7/10 ,  G11C11/407 ,  G11C7/00

CPC分类号： G11C7/1006 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1072 ,  G11C7/1078

摘要： A semiconductor memory device includes a memory cell array, row decoder, bit line pairs, sense amplifier, sense amplifier control circuit, data latch, transfer gate, transfer gate control circuit, and write circuit. The memory cell array has dynamic memory cells arranged in an array form. The row decoder decodes a row address signal to select a desired one of rows of the memory cell array. Each of the bit line pairs is connected to those of the memory cells which are arranged on a corresponding one of columns of the memory cell array. The sense amplifier amplifies data read out on the paired bit lines and positively feeding data back to the paired bit lines to hold the data. The sense amplifier control circuit controls the operation of the sense amplifier. The data latch latches readout data and write data. The transfer gate transfers data between the data latch and the sense amplifier. The transfer gate control circuit controls the transfer gate. The write circuit writes data into the data latch in synchronism with a clock signal. At the time of writing data into the memory cells, data is previously supplied to the data latch by the write circuit and latched in the data latch, and after the transfer gate control circuit controls the transfer gate to supply data to the bit line pairs from the data latch, the sense amplifier control circuit activates the sense amplifier.

摘要翻译： 半导体存储器件包括存储单元阵列，行解码器，位线对，读出放大器，读出放大器控制电路，数据锁存器，传输门，传输门控制电路和写电路。 存储单元阵列具有以阵列形式排列的动态存储单元。 行解码器解码行地址信号以选择存储单元阵列的所需行中的一行。 每个位线对连接到布置在存储单元阵列的相应列上的存储单元的每一个。 读出放大器放大在配对位线上读出的数据，并将数据反馈给配对的位线以保存数据。 读出放大器控制电路控制读出放大器的工作。 数据锁存器锁存读出数据和写入数据。 传输门在数据锁存器和读出放大器之间传送数据。 传输门控制电路控制传输门。 写入电路与时钟信号同步地将数据写入数据锁存器。 在将数据写入存储器单元时，数据预先由写入电路提供给数据锁存器并锁存在数据锁存器中，并且在传输门控制电路控制传输门以向位线对提供数据之后 数据锁存器，读出放大器控制电路激活读出放大器。

公开(公告)号：US5698876A

公开(公告)日：1997-12-16

申请号：US576477

申请日：1995-12-21

申请人： Tomoaki Yabe ,  Shinji Miyano ,  Katsuhiko Sato ,  Kenji Numata

发明人： Tomoaki Yabe ,  Shinji Miyano ,  Katsuhiko Sato ,  Kenji Numata

IPC分类号： G11C11/401 ,  G11C11/00 ,  G11C11/4074 ,  G11C29/14 ,  H01L21/82 ,  H01L27/02 ,  H01L27/10 ,  H01L27/118 ,  H01L27/108

CPC分类号： G11C29/14 ,  G11C11/005 ,  G11C11/4074 ,  H01L27/0207 ,  Y10S257/909

摘要： A semiconductor device of a memory-macro type can be designed within a short time to have a desired storage capacity, which does not occupy a large area, so as to reduce the chip cost. The semiconductor device includes a memory macro having sub-memory macros, each sub-memory macro having a DRAM memory-cell array, and a row decoder and a column decoder for selecting any desired memory-cell from the memory cell of the array. The memory macro also includes a control-section macro having a DC potential generating circuit for generating various DC potentials required to drive the sub-memory macros. At least one of the sub-memory macros is combined with the control-section macro to form the memory macro as a one-chip memory capable of storing an integral multiple of N bits.

摘要翻译： 可以在短时间内设计存储器 - 宏型半导体器件以具有不占用大面积的期望的存储容量，从而降低芯片成本。 半导体器件包括具有子存储器宏的存储器宏，每个子存储器宏具有DRAM存储单元阵列，以及用于从阵列的存储器单元中选择任何所需存储单元的行解码器和列解码器。 存储器宏还包括具有DC电位产生电路的控制部分宏，用于产生驱动子存储器宏所需的各种DC电位。 子存储器宏中的至少一个与控制部分宏组合以形成作为能够存储N位的整数倍的单片存储器的存储器宏。

公开(公告)号：US5640365A

公开(公告)日：1997-06-17

申请号：US524630

申请日：1995-09-07

申请人： Keniti Imamiya ,  Shinji Miyano ,  Katsuhiko Sato ,  Tomoaki Yabe

发明人： Keniti Imamiya ,  Shinji Miyano ,  Katsuhiko Sato ,  Tomoaki Yabe

IPC分类号： G11C7/22 ,  G11C8/18 ,  G11C29/00 ,  G11C7/00

CPC分类号： G11C29/842 ,  G11C29/844 ,  G11C7/22 ,  G11C8/18

摘要： A data register that stores the data corresponding to the selected memory cell in a memory cell array is provided near the memory cell array. A decoder that selects the data from the data register starts decoding in response to an address signal accessing the memory cells in synchronization with a clock signal determining the operation period. In the first half of an operation period of the clock signal, the decoder outputs a signal in response to a signal corresponding to the address signal determined in the preceding operation period. According to the output of the decoder, the data register is selected. In the latter half of the operation period, a signal corresponding to a new address signal for the next operation period is transferred to the decoder. By doing this, the output control signal in the decoder is caused to synchronize with a signal driving an address signal, enabling the proper address to be selected without fail.

摘要翻译： 在存储单元阵列附近提供将存储单元阵列中与所选存储单元对应的数据存储的数据寄存器。 从数据寄存器中选择数据的解码器响应于与确定操作周期的时钟信号同步地访问存储器单元的地址信号开始解码。 在时钟信号的运算周期的前半部分中，解码器响应于与前一操作周期中确定的地址信号对应的信号输出信号。 根据解码器的输出，选择数据寄存器。 在操作期间的后半部分，将与下一个操作期间的新的地址信号对应的信号传送到解码器。 通过这样做，使解码器中的输出控制信号与驱动地址信号的信号同步，使得能够选择合适的地址。