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21 条记录 (耗时 0.029 秒)

    FLASH MEMORY
    1.
    发明申请
    FLASH MEMORY 有权
    闪存

    公开(公告)号：US20070223277A1

    公开(公告)日：2007-09-27

    申请号：US11747225

    申请日：2007-05-10

    申请人： Tomoharu TANAKA ,  Noboru SHIBATA ,  Toru TANZAWA

    发明人： Tomoharu TANAKA ,  Noboru SHIBATA ,  Toru TANZAWA

    IPC分类号： G11C16/06

    CPC分类号： G06F11/10 ,  G06F11/1008 ,  G06F11/1068 ,  G06F11/1072 ,  G11C7/1006 ,  G11C16/0483 ,  G11C16/10 ,  G11C2029/0411 ,  G11C2207/104

    摘要： A flash memory includes a memory sector, a command interface, a first signal buffer, a control signal generation circuit, a data input buffer, an error correction circuit, an address buffer, an address signal generation circuit, a plurality of data memory circuits, and write circuit. The command interface receives a write data input instruction from an external device to generate a write data input instruction signal, and receives a write instruction from the external device to generate a write instruction signal. The error correction circuit is activated by the write data input instruction signal to receive the write data in synchronization with the write enable signal, and is activated by the write instruction signal to generate a check data for an error correction in synchronization with the control signal.

    摘要翻译： 闪速存储器包括存储器扇区，命令接口，第一信号缓冲器，控制信号生成电路，数据输入缓冲器，纠错电路，地址缓冲器，地址信号生成电路，多个数据存储电路， 和写电路。 命令接口从外部设备接收写入数据输入指令，生成写入数据输入指令信号，并从外部设备接收写入指令，生成写入指令信号。 误差校正电路由写数据输入指令信号激活，以与写使能信​​号同步地接收写入数据，并由写指令信号激活，以产生与控制信号同步的纠错校验数据。

    FLASH MEMORY
    2.
    发明申请
    FLASH MEMORY 有权
    闪存

    公开(公告)号：US20090164712A1

    公开(公告)日：2009-06-25

    申请号：US12371659

    申请日：2009-02-16

    申请人： Tomoharu TANAKA ,  Noboru SHIBATA ,  Toru TANZAWA

    发明人： Tomoharu TANAKA ,  Noboru SHIBATA ,  Toru TANZAWA

    IPC分类号： G06F12/02 ,  G06F12/00 ,  G06F11/16

    CPC分类号： G06F11/10 ,  G06F11/1008 ,  G06F11/1068 ,  G06F11/1072 ,  G11C7/1006 ,  G11C16/0483 ,  G11C16/10 ,  G11C2029/0411 ,  G11C2207/104

    摘要： A flash memory includes a memory sector, a command interface, a first signal buffer, a control signal generation circuit, a data input buffer, an error correction circuit, an address buffer, an address signal generation circuit, a plurality of data memory circuits, and write circuit. The command interface receives a write data input instruction from an external device to generate a write data input instruction signal, and receives a write instruction from the external device to generate a write instruction signal. The error correction circuit is activated by the write data input instruction signal to receive the write data in synchronization with the write enable signal, and is activated by the write instruction signal to generate a check data for an error correction in synchronization with the control signal.

    摘要翻译： 闪速存储器包括存储器扇区，命令接口，第一信号缓冲器，控制信号生成电路，数据输入缓冲器，纠错电路，地址缓冲器，地址信号生成电路，多个数据存储电路， 和写电路。 命令接口从外部设备接收写入数据输入指令，生成写入数据输入指令信号，并从外部设备接收写入指令，生成写入指令信号。 误差校正电路由写数据输入指令信号激活，以与写使能信​​号同步地接收写入数据，并由写指令信号激活，以产生与控制信号同步的纠错校验数据。

    FLASH MEMORY
    3.
    发明申请
    FLASH MEMORY 有权

    公开(公告)号：US20130097473A1

    公开(公告)日：2013-04-18

    申请号：US13708222

    申请日：2012-12-07

    申请人： Tomoharu TANAKA ,  Noboru SHIBATA ,  Toru TANZAWA

    发明人： Tomoharu TANAKA ,  Noboru SHIBATA ,  Toru TANZAWA

    IPC分类号： G06F11/10

    CPC分类号： G06F11/10 ,  G06F11/1008 ,  G06F11/1068 ,  G06F11/1072 ,  G11C7/1006 ,  G11C16/0483 ,  G11C16/10 ,  G11C2029/0411 ,  G11C2207/104

    摘要： A flash memory includes a memory sector, a command interface, a first signal buffer, a control signal generation circuit, a data input buffer, an error correction circuit, an address buffer, an address signal generation circuit, a plurality of data memory circuits, and write circuit. The command interface receives a write data input instruction from an external device to generate a write data input instruction signal, and receives a write instruction from the external device to generate a write instruction signal. The error correction circuit is activated by the write data input instruction signal to receive the write data in synchronization with the write enable signal, and is activated by the write instruction signal to generate a check data for an error correction in synchronization with the control signal.

    FLASH MEMORY
    4.
    发明申请
    FLASH MEMORY 有权
    闪存

    公开(公告)号：US20110167320A1

    公开(公告)日：2011-07-07

    申请号：US13046333

    申请日：2011-03-11

    申请人： Tomoharu TANAKA ,  Noboru SHIBATA ,  Toru TANZAWA

    发明人： Tomoharu TANAKA ,  Noboru SHIBATA ,  Toru TANZAWA

    IPC分类号： G06F11/10

    CPC分类号： G06F11/10 ,  G06F11/1008 ,  G06F11/1068 ,  G06F11/1072 ,  G11C7/1006 ,  G11C16/0483 ,  G11C16/10 ,  G11C2029/0411 ,  G11C2207/104

    摘要： A flash memory includes a memory sector, a command interface, a first signal buffer, a control signal generation circuit, a data input buffer, an error correction circuit, an address buffer, an address signal generation circuit, a plurality of data memory circuits, and write circuit. The command interface receives a write data input instruction from an external device to generate a write data input instruction signal, and receives a write instruction from the external device to generate a write instruction signal. The error correction circuit is activated by the write data input instruction signal to receive the write data in synchronization with the write enable signal, and is activated by the write instruction signal to generate a check data for an error correction in synchronization with the control signal.

    摘要翻译： 闪速存储器包括存储器扇区，命令接口，第一信号缓冲器，控制信号生成电路，数据输入缓冲器，纠错电路，地址缓冲器，地址信号生成电路，多个数据存储电路， 和写电路。 命令接口从外部设备接收写入数据输入指令，生成写入数据输入指令信号，并从外部设备接收写入指令，生成写入指令信号。 误差校正电路由写数据输入指令信号激活，以与写使能信​​号同步地接收写入数据，并由写指令信号激活，以产生与控制信号同步的纠错校验数据。

    SEMICONDUCTOR MEMORY DEVICE
    5.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 有权
    半导体存储器件

    公开(公告)号：US20100110790A1

    公开(公告)日：2010-05-06

    申请号：US12632203

    申请日：2009-12-07

    申请人： Tomoharu TANAKA ,  Hiroshi NAKAMURA ,  Toru TANZAWA

    发明人： Tomoharu TANAKA ,  Hiroshi NAKAMURA ,  Toru TANZAWA

    IPC分类号： G11C16/04 ,  G11C16/06

    CPC分类号： G11C16/0483 ,  G11C7/1048 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C11/565 ,  G11C16/26 ,  G11C2211/5642

    摘要： A semiconductor memory device comprises memory cells, a bitline connected to the memory cells, a read circuit including a precharge circuit, and a first transistor connected between the bitline and the read circuit, wherein a first voltage is applied to a gate of the first transistor when the precharge circuit precharges the bitline, and a second voltage which is different from the first voltage is applied to the gate of the first transistor when the read circuit senses a change in a voltage of the bitline.

    摘要翻译： 半导体存储器件包括存储器单元，连接到存储器单元的位线，包括预充电电路的读取电路和连接在位线和读取电路之间的第一晶体管，其中第一电压施加到第一晶体管的栅极 当预充电电路对位线进行预充电，并且当读取电路感测到位线的电压变化时，与第一电压不同的第二电压被施加到第一晶体管的栅极。

    SEMICONDUCTOR MEMORY DEVICE
    6.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 有权
    半导体存储器件

    公开(公告)号：US20080175067A1

    公开(公告)日：2008-07-24

    申请号：US12040457

    申请日：2008-02-29

    申请人： Tomoharu TANAKA ,  Hiroshi NAKAMURA ,  Toru TANZAWA

    发明人： Tomoharu TANAKA ,  Hiroshi NAKAMURA ,  Toru TANZAWA

    IPC分类号： G11C16/06 ,  G11C7/00

    CPC分类号： G11C16/0483 ,  G11C7/1048 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C11/565 ,  G11C16/26 ,  G11C2211/5642

    摘要： A semiconductor memory device comprises memory cells, a bitline connected to the memory cells, a read circuit including a precharge circuit, and a first transistor connected between the bitline and the read circuit, wherein a first voltage is applied to a gate of the first transistor when the precharge circuit precharges the bitline, and a second voltage which is different from the first voltage is applied to the gate of the first transistor when the read circuit senses a change in a voltage of the bitline.

    摘要翻译： 半导体存储器件包括存储器单元，连接到存储器单元的位线，包括预充电电路的读取电路和连接在位线和读取电路之间的第一晶体管，其中第一电压施加到第一晶体管的栅极 当预充电电路对位线进行预充电，并且当读取电路感测到位线的电压变化时，与第一电压不同的第二电压被施加到第一晶体管的栅极。

    SEMICONDUCTOR MEMORY DEVICE
    7.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 有权
    半导体存储器件

    公开(公告)号：US20110222343A1

    公开(公告)日：2011-09-15

    申请号：US13100020

    申请日：2011-05-03

    申请人： Tomoharu TANAKA ,  Hiroshi NAKAMURA ,  Toru TANZAWA

    发明人： Tomoharu TANAKA ,  Hiroshi NAKAMURA ,  Toru TANZAWA

    IPC分类号： G11C16/10 ,  G11C16/04

    CPC分类号： G11C16/0483 ,  G11C7/1048 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C11/565 ,  G11C16/26 ,  G11C2211/5642

    摘要： A semiconductor memory device comprises memory cells, a bitline connected to the memory cells, a read circuit including a precharge circuit, and a first transistor connected between the bitline and the read circuit, wherein a first voltage is applied to a gate of the first transistor when the precharge circuit precharges the bitline, and a second voltage which is different from the first voltage is applied to the gate of the first transistor when the read circuit senses a change in a voltage of the bitline.

    摘要翻译： 半导体存储器件包括存储器单元，连接到存储器单元的位线，包括预充电电路的读取电路和连接在位线和读取电路之间的第一晶体管，其中第一电压施加到第一晶体管的栅极 当预充电电路对位线进行预充电，并且当读取电路感测到位线的电压变化时，与第一电压不同的第二电压被施加到第一晶体管的栅极。

    Semiconductor Memory Device for Storing Multivalued Data
    9.
    发明申请
    Semiconductor Memory Device for Storing Multivalued Data 有权
    用于存储多值数据的半导体存储器件

    公开(公告)号：US20100277980A1

    公开(公告)日：2010-11-04

    申请号：US12837595

    申请日：2010-07-16

    申请人： Noboru SHIBATA ,  Tomoharu TANAKA

    发明人： Noboru SHIBATA ,  Tomoharu TANAKA

    IPC分类号： G11C16/04

    CPC分类号： G11C16/3427 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/12 ,  G11C16/3459 ,  G11C2211/5621 ,  G11C2211/5646 ,  G11C2211/5648 ,  G11C2216/14

    摘要： Data storage circuits are connected to the bit lines in a one-to-one correspondence. A write circuit writes the data on a first page into a plurality of first memory cells selected simultaneously by a word line. Thereafter, the write circuit writes the data on a second page into the plurality of first memory cell. Then, the write circuit writes the data on the first and second pages into second memory cells adjoining the first memory cells in the bit line direction.

    摘要翻译： 数据存储电路以一一对应的方式连接到位线。 写电路将第一页上的数据写入由字线同时选择的多个第一存储单元。 此后，写电路将第二页上的数据写入多个第一存储单元。 然后，写入电路将第一和第二页面上的数据写入与位线方向相邻的第一存储单元的第二存储单元。