公开(公告)号：US06303422B1

公开(公告)日：2001-10-16

申请号：US09329647

申请日：1999-06-09

申请人： Tomohisa Abe ,  Masaru Ushiroda ,  Toshio Komuro

发明人： Tomohisa Abe ,  Masaru Ushiroda ,  Toshio Komuro

IPC分类号： H01L218234

CPC分类号： H01L27/11 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/5228 ,  H01L23/5286 ,  H01L23/53223 ,  H01L27/1112 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor memory in which a layout margin at the contact hole between wiring layers of a SRAM does not need and the wiring capacity at bit lines is reduced and the high speed processing is made to be possible is provided. The SRAM is constituted of a pair of driving transistors Qd1 and Qd2, a pair of transferring transistors Qt1 and Qt2, high resistance loads R1 and R2, a pair of bit lines BL1 and BL2, and a VCC line and a GND line. Gate electrodes of each transistor and word lines are formed at a first layer, the high resistance loads are formed at a second layer, the VCC line and the GND line are formed at a third layer, and the bit lines are formed at a fourth layer. A shared contact hole using for connecting the high resistance loads to the source/drain area of transistors does not penetrate the other conductive layers. Therefore, the layout margin between the shared contact hole and the other conductive layers becomes unnecessary and the reduction of the cell size becomes possible.

摘要翻译： 提供了一种半导体存储器，其中SRAM的布线层之间的接触孔处的布局边缘不需要，并且位线处的布线容量减小，并且提供了高速处理。 SRAM由一对驱动晶体管Qd1和Qd2，一对转移晶体管Qt1和Qt2，高电阻负载R1和R2，一对位线BL1和BL2以及VCC线和GND线构成。 每个晶体管的栅电极和字线形成在第一层，高电阻负载形成在第二层，VCC线和GND线形成在第三层，并且位线形成在第四层 。 用于将高电阻负载连接到晶体管的源极/漏极区域的共用接触孔不会穿透其它导电层。 因此，共用接触孔和其它导电层之间的布局裕度变得不必要，并且可以减小电池尺寸。

公开(公告)号：US6084436A

公开(公告)日：2000-07-04

申请号：US957134

申请日：1997-10-24

申请人： Toshio Komuro

发明人： Toshio Komuro

IPC分类号： H01L29/78 ,  H01L21/8234 ,  H01L27/02 ,  H01L27/088 ,  H03K19/20 ,  H01L29/76

CPC分类号： H01L27/088 ,  H01L27/0207

摘要： A multi-input semiconductor logic device capable of high-speed operation includes a first to fifth source/drain regions formed in an active area, and first to fourth gate electrodes formed over the active area through a gate insulating layer. The first to fifth source/drain regions are arranged along an axis of the active area. The second and fourth source/drain regions are located to be adjacent to the first source/drain region at each side of the first source/drain region. The third and fifth source/drain regions are located to be adjacent to the second and fourth source/drain regions, respectively. The first gate electrode is located between the first and second source/drain regions. The second gate electrode is located between the first and fourth source/drain regions. The third gate electrode is located between the second and third source/drain regions. The fourth gate electrode is located between the fourth and fifth source/drain regions. The first and fourth gate electrodes are electrically connected to be applied with a first digital input signal. The second and third gate electrodes are electrically connected to be applied with a second digital input signal. The third and fifth source/drain regions are electrically connected.

摘要翻译： 能够进行高速操作的多输入半导体逻辑器件包括形成在有源区中的第一至第五源极/漏极区域和通过栅极绝缘层形成在有源区域上的第一至第四栅极电极。 第一至第五源极/漏极区域沿着有源区域的轴线布置。 第二和第四源极/漏极区域被定位成与第一源极/漏极区域的每一侧处的第一源极/漏极区域相邻。 第三和第五源极/漏极区分别被定位成与第二和第四源极/漏极区相邻。 第一栅电极位于第一和第二源/漏区之间。 第二栅电极位于第一和第四源/漏区之间。 第三栅电极位于第二和第三源极/漏极区之间。 第四栅电极位于第四和第五源/漏区之间。 第一和第四栅电极电连接以施加第一数字输入信号。 第二和第三栅电极电连接以施加第二数字输入信号。 第三和第五源/漏区电连接。

公开(公告)号：US5451897A

公开(公告)日：1995-09-19

申请号：US936653

申请日：1992-08-28

申请人： Toshio Komuro

发明人： Toshio Komuro

IPC分类号： G11C11/419 ,  G05F1/46 ,  G05F1/56 ,  G05F3/26 ,  G11C11/407 ,  G11C11/409 ,  H03F3/45 ,  H03K5/24 ,  G05F3/02

CPC分类号： H03F3/45076 ,  G05F1/465 ,  G05F3/262 ,  H03K5/249

摘要： A built-in supply voltage dropping circuit according to the present invention includes a current mirror amplifier, a drive transistor with a gate connected to an output of the current mirror amplifier and a drain connected to the output terminal, and a current limiting device connected in series to the current mirror amplifier and adapted for controlling the current flow through the current mirror amplifier by control signals. This construction enables reduction of current consumption without lowering response speed.

摘要翻译： 根据本发明的内置电源降压电路包括电流镜放大器，具有连接到电流镜放大器的输出的栅极的驱动晶体管和连接到输出端子的漏极以及连接到 串联到电流镜放大器，并适用于通过控制信号控制通过电流镜放大器的电流。 该结构能够降低电流消耗而不降低响应速度。

公开(公告)号：US20060171193A1

公开(公告)日：2006-08-03

申请号：US11318777

申请日：2005-12-28

申请人： Shinobu Asayama ,  Toshio Komuro

发明人： Shinobu Asayama ,  Toshio Komuro

IPC分类号： G11C11/00

CPC分类号： G11C11/413 ,  G11C8/08

摘要： An SRAM cell 1 includes inverters 10, 20, N-type FETs 32, 34, 36, 38, word lines 42, 44, bit lines 46, 48, and voltage applying circuits 50, 60. The voltage applying circuits 50, 60 apply a voltage Vdd to the word lines 42, 44 at the time of a read operation of the SRAM cell 1. The voltage applying circuits 50, 60 apply a voltage (Vdd+α) to the word lines 42, 44 at the time of a write operation of the SRAM cell 1. Here, α>0. Namely, the SRAM cell 1 is configured in such a manner that a voltage applied to word lines 42, 44 at the time of the write operation is higher than at the time of the read operation.

摘要翻译： SRAM单元1包括反相器10,20，N型FET32,34,36,38，字线42,44，位线46,48和电压施加电路50,60。 电压施加电路50,60在SRAM单元1的读取操作时对字线42,44施加电压V dd。 电压施加电路50,60在SRAM单元1的写入操作时对字线42,44施加电压（V SUB +Δ+α）。 这里，alpha> 0。 也就是说，SRAM单元1被配置成使得在写入操作时施加到字线42,44的电压高于读取操作时的电压。

公开(公告)号：US6072659A

公开(公告)日：2000-06-06

申请号：US31720

申请日：1998-02-27

申请人： Toshio Komuro

发明人： Toshio Komuro

IPC分类号： G11B15/17 ,  G11B15/675 ,  G11B33/02 ,  G11B5/008

CPC分类号： G11B15/17 ,  G11B15/67584 ,  G11B33/027

摘要： A recording and/or playback apparatus that uses a tape cassette having protrusions is equipped with a mounting section, a lid, a holder, and a detection mechanism. The mounting section is to be mounted with a tape cassette. The lid, which is to open or close the mounting section, is provided so as to be movable between a closed position for closing the mounting section and an open position for opening the mounting section. The lid is provided in front of the holder. The holder holds a tape cassette that has been inserted in the apparatus, and causes the tape cassette held by the holder to be mounted in the mounting section when the lid is moved to the closed position. The detection mechanism indicates whether a tape cassette is mounted in the mounting section. When the lid is located at the closed position, the protrusion of the tape cassette that is mounted in the mounting section manipulates the detection mechanism so that the detection mechanism projects from the front surface of the lid.

摘要翻译： 使用具有突起的带盒的记录和/或播放装置配备有安装部分，盖子，保持器和检测机构。 安装部分安装有磁带盒。 打开或关闭安装部的盖被设置成能够在关闭安装部的关闭位置和用于打开安装部的打开位置之间移动。 盖子设置在支架前面。 保持器保持已经插入设备中的磁带盒，并且当盖子移动到关闭位置时，使由保持器保持的带盒安装在安装部分中。 检测机构指示磁带盒是否安装在安装部分中。 当盖位于关闭位置时，安装在安装部中的带盒的突出部操纵检测机构，使得检测机构从盖的前表面突出。

公开(公告)号：US5377151A

公开(公告)日：1994-12-27

申请号：US767774

申请日：1991-09-30

申请人： Toshio Komuro

发明人： Toshio Komuro

IPC分类号： G11C7/06 ,  G11C7/18

CPC分类号： G11C7/18 ,  G11C7/06

摘要： The semiconductor memory device according to this invention includes a memory cell array which comprises plural memory cells arranged in row and column direction in the form of an array, plural bit line pairs for connecting these memory cells in the unit of a column and word lines for connecting these memory cells in the unit of a row, sense amplifiers which are respectively connected to each of the bit line pairs at one end thereof and which amplify the potential difference between the bit lines of each pair in response to activation signals, and transfer gate means which divide said plural bit lines respectively into at least two portions corresponding to control signals, the sense amplifiers for the bit line pairs which belong to the nth columns (n is an odd numbered integer) thereof being arranged on one end of the bit line pairs and on the other end thereof for the those which belong to the (n+1)th columns. This construction of the device can prevent crosstalk which would otherwise caused between adjacent bit line pairs immediately after the sense amplifiers are activated.

摘要翻译： 根据本发明的半导体存储器件包括存储单元阵列，该存储单元阵列包括以阵列形式排列成行和列方向的多个存储单元，用于以列为单位连接这些存储单元的多个位线对和用于单元的字线 以行为单位连接这些存储单元，读出放大器，其分别连接到其一端的每个位线对，并且响应于激活信号放大每对的位线之间的电位差，以及传输门 将所述多个位线分别分成对应于控制信号的至少两个部分的装置，用于位于第n列（n为奇数编号的整数）的位线对的读出放大器布置在位线的一端 对，其另一端为属于第（n + 1）列的那些。 器件的这种结构可以防止在感测放大器被激活之后紧邻的相邻位线对之间的串扰。

公开(公告)号：US5258228A

公开(公告)日：1993-11-02

申请号：US507532

申请日：1990-04-11

申请人： Toshio Komuro

发明人： Toshio Komuro

IPC分类号： C09K5/00 ,  C09K5/16 ,  C09K9/00 ,  D01F1/10 ,  B32B18/00 ,  B32B19/00

CPC分类号： D01F1/10 ,  Y10T428/29 ,  Y10T428/2918 ,  Y10T428/2982

摘要： This invention relates to infrared slight energy radiation powder and synthetic fiber containing the radiation powder mixed therein and fiber articles made of the synthetic fiber.The radiation powder comprising chiefly alumina, titanium and platinum or palladium, or, alumina, silica and palladium provides sufficient quantities of infrared slight energy radiation having a wide wavelength range. The clothes and bedding made of the synthetic fiber containing infrared slight energy radiation powder are warm and heat-retaining. And the wrapping articles for fresh meat and fish made in relation with the present invention are antibacterial and effective for keeping freshness of the wrapped food.

摘要翻译： 本发明涉及红外线微能量辐射粉末和含有散射粉末的合成纤维和由合成纤维制成的纤维制品。 主要包含氧化铝，钛和铂或钯，或氧化铝，二氧化硅和钯的辐射粉末提供足够量的具有宽波长范围的红外线轻微的能量辐射。 由含有红外线轻微能量辐射粉末的合成纤维制成的衣服和床上用品是保暖和保温的。 并且与本发明相关的新鲜肉类和鱼类的包装物品对于保持包装食品的新鲜度是抗菌的和有效的。

公开(公告)号：US5151616A

公开(公告)日：1992-09-29

申请号：US644655

申请日：1991-01-23

申请人： Toshio Komuro

发明人： Toshio Komuro

IPC分类号： H03K3/356 ,  H03K19/017 ,  H03K19/0185

CPC分类号： H03K3/356147 ,  H03K19/01721 ,  H03K19/018521 ,  G09G2310/0289

摘要： Two switches are provided to a semiconductor circuit which includes cascade connected first circuit section and second circuit section, each having an inverter formed by complementary transistors connected between a power terminal and a grounding terminal. The first switch is inserted between the first circuit section and the second circuit section and forms a current path of the electrical charge during the state transition of the circuit. The second switch is inserted between the input end and the power terminal of the second circuit section and controlled by the output signal for the second circuit section.

公开(公告)号：US20100073982A1

公开(公告)日：2010-03-25

申请号：US12458330

申请日：2009-07-08

申请人： Shinobu Asayama ,  Toshio Komuro

发明人： Shinobu Asayama ,  Toshio Komuro

IPC分类号： G11C5/02 ,  G11C11/00 ,  G11C5/06 ,  H01S4/00 ,  G11C7/02 ,  H03K3/03

CPC分类号： G11C29/50 ,  G11C8/08 ,  G11C11/41 ,  G11C11/413 ,  G11C11/419 ,  G11C29/025 ,  G11C29/12015 ,  G11C29/24 ,  Y10T29/49002

摘要： Disclosed herewith is a semiconductor device having an SRAM cell array capable of easily evaluating the performance of transistors and the systematic fluctuation of wiring capacity/resistance. In order to form an inversion circuit required to form a ring oscillator, a test cell is disposed at each of the four corners of the SRAM cell array and the ring oscillator is operated while charging/discharging the subject bit line. Concretely, the ring oscillator is formed on a memory cell array and the ring oscillator includes test cells disposed at least at the four corners of the memory cell array respectively. At this time, a wiring that is equivalent to a bit line is used to connect the test cells to each another.

摘要翻译： 这里公开了具有能够容易地评估晶体管的性能和布线容量/电阻的系统波动的SRAM单元阵列的半导体器件。 为了形成形成环形振荡器所需的反相电路，在SRAM单元阵列的四个角的每一个处设置测试单元，并且在对主体位线进行充电/放电的同时操作环形振荡器。 具体地，环形振荡器形成在存储单元阵列上，并且环形振荡器分别包括设置在存储单元阵列的至少四个角的测试单元。 此时，使用等同于位线的布线来将测试单元彼此连接。

公开(公告)号：US07239538B2

公开(公告)日：2007-07-03

申请号：US11318776

申请日：2005-12-28

申请人： Shinobu Asayama ,  Toshio Komuro

发明人： Shinobu Asayama ,  Toshio Komuro

IPC分类号： G11C11/40

CPC分类号： G11C11/413

摘要： The SRAM cell 1 includes inverters 10, 20, N-type FETs (Field Effect Transistors) 32, 34, 36, 38, word lines 42, 44, and bit lines 46, 48. A gate width W2 and gate length L2 of the FETs 32, 34, 36, 38 are equal to a gate width W3 and gate length L3 of the FETs 12, 22, respectively. In particular, in this embodiment, a gate width W4 and gate length L4 of the FETs 14, 24 are also equal to W2 (=W3) and L2 (=L3), respectively. Namely, the SRAM cell 1 is designed in such a manner that W2=W3=W4, and L2=L3=L4.

摘要翻译： SRAM单元1包括反相器10,20，N型FET（场效应晶体管）32,34,36,38，字线42,44和位线46,48。 FET32,34,36,38的栅极宽度W 2和栅极长度L 2分别等于FET 12,22的栅极宽度W 3和栅极长度L 3。 特别地，在本实施例中，FET 14,24的栅极宽度W 4和栅极长度L 4也分别等于W 2（= W 3）和L 2（= L 3）。 即，SRAM单元1以W 2 = W 3 = W 4，L 2 = L 3 = L 4的方式设计。